Change in coreboot[master]: arch/riscv: Add soc interface to get mtime frequency

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37549 )


Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................

arch/riscv: Add soc interface to get mtime frequency

The mtime clock is not microseconds, but is determined by the
specific platform. So timer_monotonic_get needs to know the
frequency of mtime.

Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Signed-off-by: Xiang Wang <[e-mail]>
---
M src/arch/riscv/arch_timer.c
M src/arch/riscv/include/mcall.h
M src/mainboard/emulation/qemu-riscv/Makefile.inc
M src/mainboard/emulation/qemu-riscv/clint.c
M src/mainboard/emulation/spike-riscv/Makefile.inc
M src/mainboard/emulation/spike-riscv/clint.c
M src/soc/sifive/fu540/clint.c
7 files changed, 25 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37549/1

diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c
index 55b1f72..1353abd 100644
--- a/src/arch/riscv/arch_timer.c
+++ b/src/arch/riscv/arch_timer.c
@@ -24,5 +24,6 @@
 {
 	if (HLS()->time == NULL)
 		die("time not set in HLS");
-	mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time)));
+	long time = (long)read64((void *)(HLS()->time));
+	mono_time_set_usecs(mt, time / (mtime_frequency() / 1000000));
 }
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index d7d67ce..24b46a7 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -93,6 +93,12 @@
  */
 void set_msip(int hartid, int val);
 
+/*
+ * This function is used to get frequency of mtime,
+ * need be implement by SoC code
+ */
+long mtime_frequency(void);
+
 #endif // __ASSEMBLER__
 
 #endif
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc
index eb99544..2ca75fd 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.inc
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc
@@ -19,6 +19,7 @@
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
+romstage-y += clint.c
 
 ramstage-y += uart.c
 ramstage-y += rom_media.c
diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c
index 367d48d..96d0f1d 100644
--- a/src/mainboard/emulation/qemu-riscv/clint.c
+++ b/src/mainboard/emulation/qemu-riscv/clint.c
@@ -23,3 +23,8 @@
 	HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8);
 	HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id);
 }
+
+long mtime_frequency(void)
+{
+	return 1000000;
+}
diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc
index 38977b6..bfeaf58 100644
--- a/src/mainboard/emulation/spike-riscv/Makefile.inc
+++ b/src/mainboard/emulation/spike-riscv/Makefile.inc
@@ -18,6 +18,7 @@
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
+romstage-y += clint.c
 ramstage-y += uart.c
 ramstage-y += rom_media.c
 ramstage-y += clint.c
diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c
index 7ad3f5a..4c2b8fa 100644
--- a/src/mainboard/emulation/spike-riscv/clint.c
+++ b/src/mainboard/emulation/spike-riscv/clint.c
@@ -24,3 +24,8 @@
 	HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8);
 	HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id);
 }
+
+long mtime_frequency(void)
+{
+	return 1000000;
+}
diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c
index 699273e..09ec719 100644
--- a/src/soc/sifive/fu540/clint.c
+++ b/src/soc/sifive/fu540/clint.c
@@ -29,3 +29,8 @@
 {
 	write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val);
 }
+
+long mtime_frequency(void)
+{
+	return 1000000;
+}

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-MessageType: newchange

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37549 )

Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................


Patch Set 1:

Please refer to https://github.com/riscv/riscv-isa-manual/blob/45e063b17f98b980efe9dd8a75a49...


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-Reviewer: Martin Roth <[e-mail]>
Gerrit-Reviewer: Patrick Georgi <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Xiang Wang <[e-mail]>
Gerrit-Reviewer: ron minnich <[e-mail]>
Gerrit-CC: Shawn C <[e-mail]>
Gerrit-Comment-Date: Fri, 06 Dec 2019 09:13:42 +0000
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[Xiang Wang (Code Review)]

Hello ron minnich, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/37549

to look at the new patch set (#2).

Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................

arch/riscv: Add soc interface to get mtime frequency

The mtime clock is not microseconds, but is determined by the
specific platform. So timer_monotonic_get needs to know the
frequency of mtime.

Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Signed-off-by: Xiang Wang <[e-mail]>
---
M src/arch/riscv/arch_timer.c
M src/arch/riscv/include/mcall.h
M src/mainboard/emulation/qemu-riscv/clint.c
M src/mainboard/emulation/spike-riscv/clint.c
M src/soc/sifive/fu540/clint.c
5 files changed, 23 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37549/2
-- 
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-Reviewer: Martin Roth <[e-mail]>
Gerrit-Reviewer: Patrick Georgi <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Xiang Wang <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Reviewer: ron minnich <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-CC: Shawn C <[e-mail]>
Gerrit-MessageType: newpatchset

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37549 )

Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................


Patch Set 2:

Have anything update ?


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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-Reviewer: Martin Roth <[e-mail]>
Gerrit-Reviewer: Patrick Georgi <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Xiang Wang <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Reviewer: ron minnich <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-CC: Shawn C <[e-mail]>
Gerrit-Comment-Date: Fri, 10 Jan 2020 04:10:48 +0000
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[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37549 )

Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................


Patch Set 2:

Have anything update?


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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-Reviewer: Martin Roth <[e-mail]>
Gerrit-Reviewer: Patrick Georgi <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Xiang Wang <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Reviewer: ron minnich <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-CC: Shawn C <[e-mail]>
Gerrit-Comment-Date: Mon, 03 Feb 2020 07:16:39 +0000
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[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37549 )

Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................


Patch Set 2:

Have anything update?


-- 
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-Reviewer: Martin Roth <[e-mail]>
Gerrit-Reviewer: Patrick Georgi <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Xiang Wang <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Reviewer: ron minnich <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-CC: Shawn C <[e-mail]>
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[S] Change in coreboot[master]: arch/riscv: Add soc interface to get mtime frequency

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37549?usp=email )

Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................


Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Gerrit-PatchSet: 2
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Gerrit-Reviewer: Martin L Roth <[e-mail]>
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