coreboot-gerrit February 2020

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Change in coreboot[master]: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34517 ) Change subject: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides ...................................................................... soc/intel/{cnl,icl}: Enable support to configure interrupt overrides This implementation selects SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE config. It would enable support from SOC to dynamically populate the PCI IRQ routing table based on the devices enabled from the mainboard. And pass the same to FSP to configure the IRQ entries in ITSS PIRx register. The same table can be used to generate the ACPI PIRQ mapping table. Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34517/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..0283f2c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 5dca44b..79a19ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Gerrit-Change-Number: 34517 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34349 ) Change subject: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides ...................................................................... src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/fsp_params.c 4 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34349/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4235b7a..c8dfc13 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fe5b3dd..4eef58e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -408,6 +409,11 @@ configure_gspi_cs(i, config, &params->SerialIoSpiCsPolarity[0], NULL, NULL); #endif + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2261a0..d31c8eb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ed86c27..ee45024 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -241,6 +242,12 @@ params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Gerrit-Change-Number: 34349 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: src/soc/intel/*/include: Get list of devices that needs IRQ programming
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 ) Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming ...................................................................... src/soc/intel/*/include: Get list of devices that needs IRQ programming This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices. Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..ed0d09c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/cannonlake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd02934..2973e15 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/icelake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Gerrit-Change-Number: 34348 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: libpayload: Add support for link time optimization
by Jacob Garber (Code Review) 03 Nov '20

03 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38291 ) Change subject: libpayload: Add support for link time optimization ...................................................................... libpayload: Add support for link time optimization Link time optimization is a technique for whole-program optimization. Instead of doing code generation during compilation, the compiler saves its intermediate representation to the object files. During the final linking step, it will then merge all the object files together and perform optimizations on the entire program. This can often reduce the final binary size, but also may increase the total compilation time. This patch introduces a Kconfig option for enabling link time optimization in libpayload. Since libpayload does no linking of its own, its LTO archive files will contain only IR and no generated code. Downstream projects will need to use LTO-aware tools when manipulating the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use LTO themselves -- the compiler will recognize which files are LTO and which are not, so enabling this option should mostly be "drop in". For example, when building coreinfo.elf using tinycurses libpayload: binary size compilation time default 149K 11.49s LTO 125K 10.36s In this case the total compilation time was actually shorter -- despite the final linking step taking longer, this was offset by the shorter compilation times for each individual file (since there is no code gen until the very end). Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38291/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7501e3..9312f19 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -80,6 +80,13 @@ endchoice +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config REMOTEGDB bool "Remote GDB stub" default n diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 1b7986c..ecf7937 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -65,6 +65,10 @@ CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror +ifeq ($(CONFIG_LP_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Gerrit-Change-Number: 38291 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: coreinfo: Add support for link time optimization
by Jacob Garber (Code Review) 02 Nov '20

02 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38293 ) Change subject: coreinfo: Add support for link time optimization ...................................................................... coreinfo: Add support for link time optimization This introduces a Kconfig option for compiling coreinfo with LTO. This option can be used independently of LTO in libpayload, though will benefit most if that is enabled as well. If both are enabled, the final size of coreinfo.elf is reduced from 125K to 122K. Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/coreinfo/Kconfig M payloads/coreinfo/Makefile 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38293/1 diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index fd4c1b4..5fb17bb 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -56,6 +56,13 @@ help The version number of this payload. +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + endmenu menu "Modules" diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 34c45d9..6452c00 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -90,9 +90,13 @@ include $(src)/.config real-all: $(TARGET) +ifeq ($(CONFIG_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) -o $@ $(OBJS) + $(LPCC) $(CFLAGS) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Gerrit-Change-Number: 38293 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

8 18

Change in coreboot[master]: soc/intel/fsp-car: Use the coreboot defined stack
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37278 ) Change subject: soc/intel/fsp-car: Use the coreboot defined stack ...................................................................... soc/intel/fsp-car: Use the coreboot defined stack The stack needs to be in the coreboot defined region to not collide with other symbols. Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37278/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index ec43311..d7ef834 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,7 +87,7 @@ jnz .halt_forever /* Setup bootblock stack */ - mov %edx, %esp + movl _ecar_stack, %esp /* coreboot assumes CAR region will be zero */ cld -- To view, visit https://review.coreboot.org/c/coreboot/+/37278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Gerrit-Change-Number: 37278 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
by Arthur Heymans (Code Review) 30 Oct '20

30 Oct '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35872 ) Change subject: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg ...................................................................... {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg The last argument for acpi_fill_mcfg is the last PCI bus, not the total number of busses. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/northbridge.c M src/soc/amd/stoneyridge/northbridge.c M src/southbridge/amd/pi/hudson/lpc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35872/1 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f9..756537b 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -167,7 +167,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..2304e73 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -183,7 +183,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 02123a1..cf73a8c 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -336,7 +336,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Gerrit-Change-Number: 35872 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: cbfs: Hook up to new CBFS implmentation
by Julius Werner (Code Review) 30 Oct '20

30 Oct '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38422 to review the following change. Change subject: cbfs: Hook up to new CBFS implmentation ...................................................................... cbfs: Hook up to new CBFS implmentation This patch hooks coreboot up to the new commonlib/bsd CBFS implementation. This is intended as the "minimum viable patch" that makes the new implementation useable with the smallest amount of changes -- that is why some of this may look a bit roundabout (returning the whole metadata for a file but then just using that to fill out the rdevs of the existing struct cbfsf). Future changes will migrate the higher level CBFS APIs one-by-one to use the new implementation directly (rather than translated into the results of the old one), at which point this will become more efficient. Change-Id: I4d112d1239475920de2d872dac179c245275038d Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/Makefile.inc A src/include/cbfs_glue.h M src/lib/cbfs.c 3 files changed, 63 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38422/1 diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 5bd6cf9..b2225cb 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -30,6 +30,13 @@ smm-y += cbfs.c postcar-y += cbfs.c +bootblock-y += bsd/cbfs_private.c +verstage-y += bsd/cbfs_private.c +romstage-y += bsd/cbfs_private.c +postcar-y += bsd/cbfs_private.c +ramstage-y += bsd/cbfs_private.c +smm-y += bsd/cbfs_private.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h new file mode 100644 index 0000000..10f4187 --- /dev/null +++ b/src/include/cbfs_glue.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include <commonlib/region.h> +#include <console/console.h> + +#define ENABLE_HASHING 0 + +#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) +#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#if CONFIG(DEBUG_CBFS) +#define DEBUG(...) printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__) +#else +#define DEBUG(...) +#endif + +typedef const struct region_device *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + return rdev_readat(dev, buffer, offset, size); +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return region_device_sz(dev); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c712f76..d6fb99c 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <boot_device.h> #include <cbfs.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/bsd/compression.h> #include <endian.h> #include <lib.h> @@ -29,14 +30,6 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { struct region_device rdev; @@ -44,28 +37,35 @@ if (cbfs_boot_region_device(&rdev)) return -1; - int ret = cbfs_locate(fh, &rdev, name, type); + union cbfs_mdata mdata; + size_t data_offset; + cb_err_t err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) { + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + return -1; + err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); + } + if (err) + return -1; - /* - * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the - * active RW region, the RO (COREBOOT) region will be used to locate the file. - * - * This functionality makes it possible to avoid duplicate files in the RO - * and RW partitions while maintaining updateability. - * - * Files can be added to the RO_REGION_ONLY config option to use this feature. - */ - printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); - ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type); + size_t msize = be32toh(mdata.h.offset); + if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) + return -1; + if (type) { + if (!*type) + *type = be32toh(mdata.h.type); + else if (*type != be32toh(mdata.h.type)) + return -1; } - if (!ret) - if (vboot_measure_cbfs_hook(fh, name)) - return -1; + if (vboot_measure_cbfs_hook(fh, name)) + return -1; - return ret; + return 0; } void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/38422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d112d1239475920de2d872dac179c245275038d Gerrit-Change-Number: 38422 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: commonlib/bsd: Add new CBFS core implementation
by Julius Werner (Code Review) 30 Oct '20

30 Oct '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38421 to review the following change. Change subject: commonlib/bsd: Add new CBFS core implementation ...................................................................... commonlib/bsd: Add new CBFS core implementation This patch adds a new CBFS implementation that is intended to replace the existing commonlib/cbfs.c. The new implementation is designed to meet a bunch of current and future goals that in aggregate make it easier to start from scratch than to adapt the exisiting implementation: 1. Be BSD-licensed so it can evetually be shared with libpayload. 2. Allow generating/verifying a master hash for future CBFS per-file verification (see [1][2]). 3. Be very careful about reading (not mmaping) all data only once, to be suitable for eventual TOCTOU-safe verification. 4. Make it possibly to efficiently implement all current and future firmware use cases (both with and without verification). The main primitive is the cbfs_walk() function which will traverse a CBFS and call a callback for every file. cbfs_lookup() uses this to implement the most common use case of finding a file so that it can be read. A host application using this code (e.g. coreboot, libpayload, cbfstool) will need to provide a <cbfs_glue.h> header to provide the glue to access the respective CBFS storage backend implementation. This patch merely adds the code, the next patch will integrate it into coreboot. [1]: https://www.youtube.com/watch?v=Hs_EhewBgtM [2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_i… Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M MAINTAINERS A src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cb_err.h A src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h 5 files changed, 284 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38421/1 diff --git a/MAINTAINERS b/MAINTAINERS index 77769c0..b5cad10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -489,8 +489,13 @@ F: src/device/oprom/ CBFS -F: src/include/cbfs.h -F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +M: Julius Werner <jwerner(a)chromium.org> +F: src/include/cbfs* +F: src/commonlib/bsd/include/commonlib/bsd/cbfs* +F: src/commonlib/bsd/cbfs* +F: src/lib/cbfs.c + +CBFSTOOL F: util/cbfstool/ CBMEM diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c new file mode 100644 index 0000000..4dd14cb --- /dev/null +++ b/src/commonlib/bsd/cbfs_private.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include <commonlib/bsd/cbfs_private.h> +#include <assert.h> + +static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer) +{ + DEBUG("Looking for next file @%#zx...\n", *offset); + *offset = ALIGN_UP(*offset, CBFS_ALIGNMENT); + while (*offset + sizeof(*buffer) < cbfs_dev_size(dev)) { + if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer)) + return CB_CBFS_IO; + + if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0) + return CB_SUCCESS; + + *offset += CBFS_ALIGNMENT; + } + + DEBUG("End of CBFS reached\n"); + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + union cbfs_mdata *mdata, bool do_hash, + void *arg), + void *arg, struct vb2_hash *master_hash, enum cbfs_walk_flags flags) +{ + bool do_hash = ENABLE_HASHING && master_hash; + struct vb2_digest_context dc; + vb2_error_t vbrv; + + assert(ENABLE_HASHING || (!master_hash && !(flags & CBFS_WALK_WRITEBACK_HASH))); + if (do_hash && (vbrv = vb2_digest_init(&dc, master_hash->algo))) { + ERROR("Master hash algo %d digest init error: %#x\n", master_hash->algo, vbrv); + return CB_ERR_ARG; + } + + size_t offset = 0; + cb_err_t ret_header; + cb_err_t ret_walker = CB_CBFS_NOT_FOUND; + union cbfs_mdata mdata; + while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) { + const uint32_t attr_offset = be32toh(mdata.h.attributes_offset); + const uint32_t data_offset = be32toh(mdata.h.offset); + const uint32_t data_length = be32toh(mdata.h.len); + const uint32_t type = be32toh(mdata.h.type); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2); + + DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", + offset, be32toh(mdata.h.type), attr_offset, data_offset, data_length); + if (data_offset > sizeof(mdata)) { + ERROR("File metadata @%#zx too large\n", offset); + goto next_file; + } + if (offset + data_offset >= cbfs_dev_size(dev)) { + ERROR("Device ends in middle of metadata @%#zx\n", offset); + goto next_file; + } + + if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY)) + goto next_file; + + /* When hashing we need to read everything. Otherwise skip the attributes. + attr_offset may be 0, which means there are no attributes. */ + ssize_t todo; + if (do_hash || attr_offset == 0) + todo = data_offset - sizeof(mdata.h); + else + todo = attr_offset - sizeof(mdata.h); + if (todo <= 0 || data_offset < attr_offset) { + ERROR("Corrupt file header @%#zx\n", offset); + goto next_file; + } + + /* Read the rest of the metadata (filename, and possibly attributes). */ + if (cbfs_dev_read(dev, (uint8_t *)&mdata + sizeof(mdata.h), + offset + sizeof(mdata.h), todo) != todo) + return CB_CBFS_IO; + DEBUG("File name: '%s'\n", mdata.filename); + + if (do_hash && !empty && vb2_digest_extend(&dc, (void *)&mdata, data_offset)) + return CB_ERR; + + if (ret_walker == CB_CBFS_NOT_FOUND) + ret_walker = walker(dev, offset, &mdata, do_hash, arg); + + /* Return IO errors immediately. For others, finish the hash first if needed. */ + if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash)) + return ret_walker; + +next_file: + offset += data_offset + data_length; + } + + if (ret_header != CB_CBFS_NOT_FOUND) + return ret_header; + + if (do_hash) { + uint8_t real_hash[VB2_MAX_DIGEST_SIZE]; + size_t hash_size = vb2_digest_size(master_hash->algo); + if (vb2_digest_finalize(&dc, real_hash, sizeof(real_hash))) + return CB_ERR; + if (flags & CBFS_WALK_WRITEBACK_HASH) + memcpy(master_hash->bytes.raw, real_hash, hash_size); + else if (memcmp(master_hash->bytes.raw, real_hash, hash_size) != 0) + return CB_CBFS_HASH; + } + + return ret_walker; +} + +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, union cbfs_mdata *src, + cbfs_dev_t dev, size_t offset, bool do_hash) +{ + const size_t attr_offset = be32toh(src->h.attributes_offset); + + /* In the hashing case or when there are no attributes, we already have everything. */ + if (do_hash || attr_offset == 0) { + memcpy(dst, src, be32toh(src->h.offset)); + return CB_SUCCESS; + } + + /* Otherwise we'll need to copy what we have and read in the rest. */ + const size_t todo = be32toh(src->h.offset) - attr_offset; + memcpy(dst, src, attr_offset); + void *dst_attrs = (uint8_t *)dst + attr_offset; + if (cbfs_dev_read(dev, dst_attrs, offset + attr_offset, todo) != todo) + return CB_CBFS_IO; + return CB_SUCCESS; +} + +uint32_t cbfs_filename_size(struct cbfs_file *h) +{ + uint32_t end_offset = be32toh(h->attributes_offset); + if (end_offset == 0) + end_offset = be32toh(h->offset); + return end_offset - sizeof(struct cbfs_file); +} + +struct cbfs_lookup_args { + union cbfs_mdata *mdata_out; + const char *name; + size_t namesize; + size_t *data_offset_out; +}; + +static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, union cbfs_mdata *mdata, + bool do_hash, void *arg) +{ + struct cbfs_lookup_args *args = arg; + if (args->namesize > cbfs_filename_size(&mdata->h) || + memcmp(args->name, mdata->filename, args->namesize) != 0) + return CB_CBFS_NOT_FOUND; + + LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); + if (cbfs_copy_fill_metadata(args->mdata_out, mdata, dev, offset, do_hash) != CB_SUCCESS) + return CB_CBFS_IO; + + *args->data_offset_out = offset + be32toh(mdata->h.offset); + return CB_SUCCESS; +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *master_hash) +{ + struct cbfs_lookup_args args = { + .mdata_out = mdata_out, + .name = name, + .namesize = strlen(name) + 1, /* Count trailing \0 so we can memcmp() it. */ + .data_offset_out = data_offset_out, + }; + return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab419a7..ab422e1 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -34,6 +34,11 @@ CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave device response, try again? */ CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ + + /* CBFS errors */ + CB_CBFS_IO = -400, /**< Underlying I/O error */ + CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ + CB_CBFS_HASH = -402, /**< Master hash validation failed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h new file mode 100644 index 0000000..b4fc1c7 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_ +#define _COMMONLIB_BSD_CBFS_PRIVATE_H_ + +#include <commonlib/bsd/cb_err.h> +#include <commonlib/bsd/cbfs_serialized.h> +#include <endian.h> +#include <stdbool.h> +#include <stdint.h> +#include <vb2_sha.h> + +/* + * This file needs to be provided by the host application using this CBFS library. It must + * define the following type, macros and functions: + * + * cbfs_dev_t An opaque type representing a CBFS storage backend. + * ENABLE_HASHING Should be 0 to avoid linking hashing features, 1 otherwise. + * ERROR(...) printf-style macro to print errors. + * LOG(...) printf-style macro to print normal-operation log messages. + * DEBUG(...) printf-style macro to print detailed debug output. + * + * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size); + * Read |size| bytes starting at |offset| from |dev| into |buffer|. + * Returns amount of bytes read on success and < 0 on error. + * + * size_t cbfs_dev_size(cbfs_dev_t dev); + * Return the total size in bytes of the CBFS storage (actual CBFS area). + */ +#include <cbfs_glue.h> + +/* Helper structure to allocate space for a blob of metadata on the stack. */ +#define CBFS_METADATA_MAX_SIZE 256 +union cbfs_mdata { + struct { + struct cbfs_file h; + char filename[]; + }; + uint8_t raw[CBFS_METADATA_MAX_SIZE]; +}; + +/* Flags that modify behavior of cbfs_walk(). */ +enum cbfs_walk_flags { + /* Write the calculated hash back out to |master_hash->hash|, rather than comparing it. + |master_hash->algo| must still have been initialized by the caller. */ + CBFS_WALK_WRITEBACK_HASH = (1 << 0), + /* Call |walker| for empty file entries. Otherwise, empty entries will be skipped. + Either way, empty entries are never included in master_hash calculation. */ + CBFS_WALK_INCLUDE_EMPTY = (1 << 1), +}; + +/* + * Traverse a CBFS and call a |walker| callback function for every file. Can additionally + * calculate a master hash over the metadata of all files in the CBFS. If |master_hash| is NULL, + * hashing is disabled. + * + * |arg| and |dev| will be passed through to |walker| unmodified. |do_hash| is true iff + * hashing is enabled (master_hash != NULL). |offset| is the total offset in |dev| at which the + * current file metadata starts. |mdata| is a temporary buffer (only valid for the duration of + * this call to |walker|) containing already read metadata from the current file: if |do_hash| + * is true, all metadata in |mdata| (header, filename and attributes) will be valid, otherwise + * only the header and the filename (not attributes) will be valid. |walker| should call into + * cbfs_copy_fill_medadata() to copy the metadata of a file to a persistent buffer and + * automatically load remaining attributes from |dev| as needed based on |do_hash|. + * + * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further + * files. Any other return code will be used as the final return code for cbfs_walk(). It will + * return immediately unless it needs to calculate a hash in which case it will still traverse + * the remaining CBFS (but not call |walker| anymore). + */ +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + union cbfs_mdata *mdata, bool do_hash, + void *arg), + void *arg, struct vb2_hash *master_hash, enum cbfs_walk_flags); + + +/* + * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata + * of a file into a permanent buffer. Will copy the metadata from |src| into |dst| and load + * additional attributes from |dev| to copy behind that if |do_hash| is false. (|offset| is the + * offset of the whole file metadata, not just of the attributes.) + */ +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, union cbfs_mdata *src, + cbfs_dev_t dev, size_t offset, bool do_hash); + +/* Helper function to determine the size of the filename part in a CBFS header. The actual + filename is NUL-terminated and due to alignment likely a bit shorter than this. */ +uint32_t cbfs_filename_size(struct cbfs_file *h); + +/* Find a file named |name| in the CBFS on |dev| and copy its metadata (including attributes) + * into |mdata_out|. Pass out offset to the file data and verify |master_hash| (if provided). */ +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *master_hash); + +#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index d2fc626..556c8e4 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -4,6 +4,7 @@ #define _CBFS_SERIALIZED_H_ #include <stdint.h> +#include <vb2_sha.h> /** These are standard values for the known compression algorithms that coreboot knows about for stages and @@ -123,12 +124,11 @@ uint32_t decompressed_size; } __packed; +/* Actual size in CBFS may be larger/smaller than struct size! */ struct cbfs_file_attr_hash { uint32_t tag; uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; + struct vb2_hash hash; } __packed; struct cbfs_file_attr_position { -- To view, visit https://review.coreboot.org/c/coreboot/+/38421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Gerrit-Change-Number: 38421 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

7 66

Change in coreboot[master]: mb/google/samus: Fix touchscreen wake GPIO
by Matt DeVillier (Code Review) 22 Oct '20

22 Oct '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37892 ) Change subject: mb/google/samus: Fix touchscreen wake GPIO ...................................................................... mb/google/samus: Fix touchscreen wake GPIO Wrong macro was copy/pasted at some point Change-Id: I92826cbac599c50ce7f7c5dabde066367edc3053 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37892/1 diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 40a4df0..802e827 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -201,7 +201,7 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) + Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) -- To view, visit https://review.coreboot.org/c/coreboot/+/37892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92826cbac599c50ce7f7c5dabde066367edc3053 Gerrit-Change-Number: 37892 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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