coreboot-gerrit November 2020

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Change in coreboot[master]: [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541
by Peter Lemenkov (Code Review) 26 Apr '21

26 Apr '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38733 ) Change subject: [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541 ...................................................................... [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541 UNTESTED. Change-Id: I315627cba495bfc376321c632248e50734daac71 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- A src/mainboard/lenovo/w541/Kconfig A src/mainboard/lenovo/w541/Kconfig.name A src/mainboard/lenovo/w541/Makefile.inc A src/mainboard/lenovo/w541/acpi/ec.asl A src/mainboard/lenovo/w541/acpi/platform.asl A src/mainboard/lenovo/w541/acpi/superio.asl A src/mainboard/lenovo/w541/acpi_tables.c A src/mainboard/lenovo/w541/board_info.txt A src/mainboard/lenovo/w541/data.vbt A src/mainboard/lenovo/w541/devicetree.cb A src/mainboard/lenovo/w541/dsdt.asl A src/mainboard/lenovo/w541/gma-mainboard.ads A src/mainboard/lenovo/w541/gpio.c A src/mainboard/lenovo/w541/hda_verb.c A src/mainboard/lenovo/w541/mainboard.c A src/mainboard/lenovo/w541/romstage.c A src/mainboard/lenovo/w541/smihandler.c 17 files changed, 807 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38733/1 diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig new file mode 100644 index 0000000..4c016fa --- /dev/null +++ b/src/mainboard/lenovo/w541/Kconfig @@ -0,0 +1,42 @@ +if BOARD_LENOVO_THINKPAD_W541 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "lenovo/w541" + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad W541" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/w541/Kconfig.name b/src/mainboard/lenovo/w541/Kconfig.name new file mode 100644 index 0000000..f2ee59c --- /dev/null +++ b/src/mainboard/lenovo/w541/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_W541 + bool "ThinkPad W541" diff --git a/src/mainboard/lenovo/w541/Makefile.inc b/src/mainboard/lenovo/w541/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/w541/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/w541/acpi/ec.asl b/src/mainboard/lenovo/w541/acpi/ec.asl new file mode 100644 index 0000000..3ff0ff7 --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/ec.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/w541/acpi/platform.asl b/src/mainboard/lenovo/w541/acpi/platform.asl new file mode 100644 index 0000000..add8c2d --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/w541/acpi/superio.asl b/src/mainboard/lenovo/w541/acpi/superio.asl new file mode 100644 index 0000000..3139e35 --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/w541/acpi_tables.c b/src/mainboard/lenovo/w541/acpi_tables.c new file mode 100644 index 0000000..ff6c05a --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi_tables.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* the lid is open by default */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/w541/board_info.txt b/src/mainboard/lenovo/w541/board_info.txt new file mode 100644 index 0000000..cd1d140 --- /dev/null +++ b/src/mainboard/lenovo/w541/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support +Board URL: https://www.lenovo.com/us/en/laptops/thinkpad/w-series/w541/ +Release year: 2015 diff --git a/src/mainboard/lenovo/w541/data.vbt b/src/mainboard/lenovo/w541/data.vbt new file mode 100644 index 0000000..4471ca1 --- /dev/null +++ b/src/mainboard/lenovo/w541/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/w541/devicetree.cb b/src/mainboard/lenovo/w541/devicetree.cb new file mode 100644 index 0000000..d7057e4 --- /dev/null +++ b/src/mainboard/lenovo/w541/devicetree.cb @@ -0,0 +1,123 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x2211 inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x221e + end + device pci 03.0 on end # Mini-HD audio Audio controller + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00040291" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x87" + register "pirqd_routing" = "0x86" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x89" + register "sata_ahci" = "1" + register "sata_port_map" = "0x21" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x2210 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on end # dummy + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventb_enable" = "0x08" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBus + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/w541/dsdt.asl b/src/mainboard/lenovo/w541/dsdt.asl new file mode 100644 index 0000000..69cd416 --- /dev/null +++ b/src/mainboard/lenovo/w541/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/w541/gma-mainboard.ads b/src/mainboard/lenovo/w541/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/lenovo/w541/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/w541/gpio.c b/src/mainboard/lenovo/w541/gpio.c new file mode 100644 index 0000000..23d4cdb --- /dev/null +++ b/src/mainboard/lenovo/w541/gpio.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/w541/hda_verb.c b/src/mainboard/lenovo/w541/hda_verb.c new file mode 100644 index 0000000..6c9c43c --- /dev/null +++ b/src/mainboard/lenovo/w541/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2211, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa2211), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/w541/mainboard.c b/src/mainboard/lenovo/w541/mainboard.c new file mode 100644 index 0000000..c53471b --- /dev/null +++ b/src/mainboard/lenovo/w541/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/w541/romstage.c b/src/mainboard/lenovo/w541/romstage.c new file mode 100644 index 0000000..eb95283 --- /dev/null +++ b/src/mainboard/lenovo/w541/romstage.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + /* note that SPD addresses are left-shifted by 1. */ + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .gbe_enable = 0, /* FIXME: check this */ + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/w541/smihandler.c b/src/mainboard/lenovo/w541/smihandler.c new file mode 100644 index 0000000..29bf797 --- /dev/null +++ b/src/mainboard/lenovo/w541/smihandler.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I315627cba495bfc376321c632248e50734daac71 Gerrit-Change-Number: 38733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/tigerlake: Implmement soc_get_north_xhci_usb_info
by Tim Wawrzynczak (Code Review) 26 Apr '21

26 Apr '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47412 ) Change subject: soc/intel/tigerlake: Implmement soc_get_north_xhci_usb_info ...................................................................... soc/intel/tigerlake: Implmement soc_get_north_xhci_usb_info TGL's North XHCI controller supports 1 USB2 port and 4 USB3 ports; add the register offset information in order to log wakes from these ports. Change-Id: I90b5baba0bcc0228f6f21977e96cde774a608e59 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/soc/intel/tigerlake/north_xhci.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47412/1 diff --git a/src/soc/intel/tigerlake/north_xhci.c b/src/soc/intel/tigerlake/north_xhci.c new file mode 100644 index 0000000..5ca6430 --- /dev/null +++ b/src/soc/intel/tigerlake/north_xhci.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/north_xhci.h> + +#define USB2_PORT_STATUS_REG 0x480 +#define USB3_PORT_STATUS_REG 0x490 +#define USB2_PORT_NUM 1 +#define USB3_PORT_NUM 4 + +static const struct north_xhci_usb_info usb_info = { + .usb2_port_status_reg = USB2_PORT_STATUS_REG, + .num_usb2_ports = USB2_PORT_NUM, + .usb3_port_status_reg = USB3_PORT_STATUS_REG, + .num_usb3_ports = USB3_PORT_NUM, +}; + +const struct north_xhci_usb_info *soc_get_north_xhci_usb_info(void) +{ + return &usb_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b5baba0bcc0228f6f21977e96cde774a608e59 Gerrit-Change-Number: 47412 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/clevo/kbl-u: Install Intel VGA INT15 handler
by Paul Menzel (Code Review) 23 Apr '21

23 Apr '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43852 ) Change subject: mb/clevo/kbl-u: Install Intel VGA INT15 handler ...................................................................... mb/clevo/kbl-u: Install Intel VGA INT15 handler Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs Change-Id: I126481c745ae701dc438ac664be0f8ff5f6250c1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- A src/mainboard/clevo/kbl-u/mainboard.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43852/1 diff --git a/src/mainboard/clevo/kbl-u/mainboard.c b/src/mainboard/clevo/kbl-u/mainboard.c new file mode 100644 index 0000000..01cfef4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_CENTERING, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/43852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126481c745ae701dc438ac664be0f8ff5f6250c1 Gerrit-Change-Number: 43852 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: [WIP] mainboard/acer: Add TravelMate X314
by Felix Singer (Code Review) 23 Apr '21

23 Apr '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35461 ) Change subject: [WIP] mainboard/acer: Add TravelMate X314 ...................................................................... [WIP] mainboard/acer: Add TravelMate X314 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Ia9a1c3492aa41ef20a4408cc91370b8f94adbe47 --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/travelmate-x314/Kconfig A src/mainboard/acer/travelmate-x314/Kconfig.name A src/mainboard/acer/travelmate-x314/acpi_tables.c A src/mainboard/acer/travelmate-x314/board_info.txt A src/mainboard/acer/travelmate-x314/devicetree.cb A src/mainboard/acer/travelmate-x314/dsdt.asl 8 files changed, 211 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35461/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..28a2945 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/travelmate-x314/Kconfig b/src/mainboard/acer/travelmate-x314/Kconfig new file mode 100644 index 0000000..8b71cbd --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/Kconfig @@ -0,0 +1,70 @@ +if BOARD_ACER_TRAVELMATE_X314 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_WHISKEYLAKE +# select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "TravelMate" + +config MAINBOARD_PART_NUMBER + string + default "X314" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "acer/travelmate-x314" + +config SUBSYSTEM_VENDOR_ID + hex + default 0xdead + +config SUBSYSTEM_DEVICE_ID + hex + default 0xbeef + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config PXE_ROM_ID + string + default "dead,beef" + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +endif # BOARD_ACER_TRAVELMATE_X314 diff --git a/src/mainboard/acer/travelmate-x314/Kconfig.name b/src/mainboard/acer/travelmate-x314/Kconfig.name new file mode 100644 index 0000000..61b4b2c --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_TRAVELMATE_X314 + bool "TravelMate X314" diff --git a/src/mainboard/acer/travelmate-x314/acpi_tables.c b/src/mainboard/acer/travelmate-x314/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/acpi_tables.c diff --git a/src/mainboard/acer/travelmate-x314/board_info.txt b/src/mainboard/acer/travelmate-x314/board_info.txt new file mode 100644 index 0000000..92ee253 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: TravelMate X314 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2019 diff --git a/src/mainboard/acer/travelmate-x314/devicetree.cb b/src/mainboard/acer/travelmate-x314/devicetree.cb new file mode 100644 index 0000000..7c519b0 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/devicetree.cb @@ -0,0 +1,57 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/acer/travelmate-x314/dsdt.asl b/src/mainboard/acer/travelmate-x314/dsdt.asl new file mode 100644 index 0000000..daddd97 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/cannonlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/cannonlake/acpi/sleepstates.asl> +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9a1c3492aa41ef20a4408cc91370b8f94adbe47 Gerrit-Change-Number: 35461 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset...
by Usha P (Code Review) 22 Apr '21

22 Apr '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40363 ) Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ...................................................................... soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation. Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC. 2. Common code takes care of setting the right value for pciex length. TEST=Able to build CNL, SKL, APL platforms. Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 44 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6d88cbc..db0cdbd 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -11,12 +11,28 @@ config SA_PCIEX_LENGTH_MIB hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 0x1000 if (PCIEX_LENGTH_4096MB) + default 0x800 if (PCIEX_LENGTH_2048MB) + default 0x400 if (PCIEX_LENGTH_1024MB) + default 0x200 if (PCIEX_LENGTH_512MB) + default 0x100 if (PCIEX_LENGTH_256MB) + default 0x80 if (PCIEX_LENGTH_128MB) + default 0x40 if (PCIEX_LENGTH_64MB) + default 0x100 help - This option allows you to select length of PCIEX region. + This option allows you to select length of PCIEX region in MiB. + +config PCIEX_LENGTH_4096MB + bool + +config PCIEX_LENGTH_2048MB + bool + +config PCIEX_LENGTH_1024MB + bool + +config PCIEX_LENGTH_512MB + bool config PCIEX_LENGTH_256MB bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..91595c2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -19,6 +19,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_64MB 2 #define PCIEXBAR_LENGTH_128MB 1 #define PCIEXBAR_LENGTH_256MB 0 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 79a6628..ff806ac 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -28,13 +28,29 @@ /* Get PCI Express Region Length */ switch (CONFIG_SA_PCIEX_LENGTH_MIB) { - case 256 * MiB: + /* + * Length of PCIEXBAR region would be more than 256MB if + * PCIEXBAR.LENGTH width is 3. + */ + case 4096: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; + break; + case 2048: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 1024: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 512: + pciexbar_length = PCIEXBAR_LENGTH_512MB; + break; + case 256: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: + case 128: pciexbar_length = PCIEXBAR_LENGTH_128MB; break; - case 64 * MiB: + case 64: pciexbar_length = PCIEXBAR_LENGTH_64MB; break; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/40363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Gerrit-Change-Number: 40363 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Add Initial support for Intel PSE
by Lean Sheng Tan (Code Review) 22 Apr '21

22 Apr '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47336 ) Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ...................................................................... soc/intel/elkhartlake: Add Initial support for Intel PSE Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. This patch add initial PSE loading support for EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I96e779021938689e0f9a96046b9c292f3ff1db4e --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47336/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 89da0be..7fc2e5f 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -194,6 +194,19 @@ config FSP_FD_PATH default "3rdparty/fsp/ElkhartLakeFspBinPkg/Fsp.fd" +config PSE_IMAGE + bool "Add a PSE binary to CBFS" + help + Add a PSE binary file to CBFS. The PSE describes the integrated + programmable service engine that is designed as an Asymmetric + Multi-Processing (AMP) system. + +config PSE_IMAGE_FILE + string "PSE binary path and filename" + depends on PSE_IMAGE + help + The path and filename of the PSE binary. + config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT int "Debug Consent for EHL" # USB DBC is more common for developers so make this default to 3 if diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..9456d4e 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -57,4 +57,10 @@ CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake/include +cbfs-files-$(CONFIG_PSE_IMAGE) += pse.bin +pse.bin-file := $(CONFIG_PSE_IMAGE_FILE) +pse.bin-type := raw +pse.bin-align := 0x1000 +pse.bin-compression := lzma + endif diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 3d740fb..4ec2cab 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -59,8 +59,14 @@ /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); - /* TODO: Update with UPD override as FSP matures */ + if (CONFIG(PSE_IMAGE)){ + //uint32_t psebase =0x0; + static char psefw[256 * KiB]; + size_t psefwsize = cbfs_boot_load_file("pse.bin", + psefw, sizeof(psefw), CBFS_TYPE_RAW); + params->SiipRegionBase = (uint32_t)&psefw; + params->SiipRegionSize = psefwsize; /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96e779021938689e0f9a96046b9c292f3ff1db4e Gerrit-Change-Number: 47336 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
by Lean Sheng Tan (Code Review) 22 Apr '21

22 Apr '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47388 ) Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ...................................................................... soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs Enabled PSE TSN feature & set the PSE TSN ports as host owned. Added options for user to add PSE TSN related configuration blobs to be consumed by FSP-S. THis patch also added PSE UPD related default settings. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7fc2e5f..0b005cc 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -207,6 +207,11 @@ help The path and filename of the PSE binary. +config ENABLE_TSN + bool "Enable TSN ethernet" + help + Enable the initialization of PCH & PSE TSN ethernet. + config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT int "Debug Consent for EHL" # USB DBC is more common for developers so make this default to 3 if @@ -226,4 +231,22 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1400 + +config TSN_MAC_ADDRESS_FILE + string "TSN MAC adress binary path and filename" + depends on ENABLE_TSN + help + The path and filename of the TSN mac adress binary. + +config TSN_CONFIG_FILE + string "TSN configuration binary path and filename" + depends on ENABLE_TSN + help + The path and filename of the TSN config file binary. + +config PSE_TSN_IP_FILE + string "PSE TSN configuration binary path and filename" + depends on ENABLE_TSN + help + The path and filename of the TSN config file binary. endif diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 9456d4e..2c02db4 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -63,4 +63,19 @@ pse.bin-align := 0x1000 pse.bin-compression := lzma +cbfs-files-$(CONFIG_ENABLE_TSN) += tsnmac.bin +tsnmac.bin-file := $(CONFIG_TSN_MAC_ADDRESS_FILE) +tsnmac.bin-type := raw +tsnmac.bin-align := 0x10 + +cbfs-files-$(CONFIG_ENABLE_TSN) += tsnconfig.bin +tsnconfig.bin-file := $(CONFIG_TSN_CONFIG_FILE) +tsnconfig.bin-type := raw +tsnconfig.bin-align := 0x10 + +cbfs-files-$(CONFIG_ENABLE_TSN) += psetsnipconfig.bin +psetsnipconfig.bin-file := $(CONFIG_PSE_TSN_IP_FILE) +psetsnipconfig.bin-type := raw +psetsnipconfig.bin-align := 0x10 + endif diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 4ec2cab..51c7d47 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -60,13 +60,97 @@ parse_devicetree(params); - if (CONFIG(PSE_IMAGE)){ + if (CONFIG(PSE_IMAGE)) + { //uint32_t psebase =0x0; static char psefw[256 * KiB]; size_t psefwsize = cbfs_boot_load_file("pse.bin", psefw, sizeof(psefw), CBFS_TYPE_RAW); params->SiipRegionBase = (uint32_t)&psefw; params->SiipRegionSize = psefwsize; + params->PchPseDmaEnable[0] = 0x1; + params->PchPseDmaEnable[1] = 0x1; + params->PchPseDmaEnable[2] = 0x1; + params->PchPseDmaSbInterruptEnable[0] = 0x0; + params->PchPseDmaSbInterruptEnable[1] = 0x1; + params->PchPseDmaSbInterruptEnable[2] = 0x1; + params->PchPseUartEnable[0] = 0x2; + params->PchPseUartEnable[1] = 0x1; + params->PchPseUartEnable[2] = 0x1; + params->PchPseHsuartEnable[0] = 0x1; + params->PchPseHsuartEnable[1] = 0x1; + params->PchPseHsuartEnable[2] = 0x1; + params->PchPseI2cEnable[2] = 0x1; + params->PchPseI2cEnable[7] = 0x1; + params->PchPseTimedGpioEnable[0] = 0x1; + params->PchPseTimedGpioEnable[1] = 0x1; + params->PchPseTimedGpioPinAllocation[0] = 0x0; + params->PchPseTimedGpioPinAllocation[1] = 0x0; + params->PchPseTimedGpioPinEnable[5] = 0x1; + params->PchPseTimedGpioPinEnable[6] = 0x1; + params->PchPseTimedGpioPinEnable[41] = 0x1; + params->PchPseTgpio6PinMux = 0x8B81A203; + params->PchPseTgpio7PinMux= 0x8B82A40B; + params->PchPseTgpio8PinMux= 0x8B80A607; + params->PchPseTgpio9PinMux= 0x8B80A808; + params->PchPseTgpio10PinMux= 0x8B86AA07; + params->PchPseTgpio11PinMux= 0x8B86AC0B; + params->PchPseTgpio12PinMux= 0x8B86AE13; + params->PchPseTgpio13PinMux= 0x8B85B00C; + params->PchPseTgpio14PinMux= 0x8B90B214; + params->PchPseTgpio15PinMux= 0x8B90B403; + params->PchPseTgpio16PinMux= 0x8B90B607; + params->PchPseTgpio17PinMux= 0x8B90B80F; + params->PchPseTgpio18PinMux= 0x8B90BA06; + params->PchPseTgpio19PinMux= 0x8B8DBC01; + params->PchPsePwmEnable = 0x1; + params->PchPsePwmPinEnable[15] = 0x0; + params->PchPsePwmPinMux[8]= 0x7B706604; + params->PchPsePwmPinMux[9]= 0x7B706805; + params->PchPsePwmPinMux[10]= 0x7B706A06; + params->PchPsePwmPinMux[11]= 0x7B706C11; + params->PchPsePwmPinMux[12]= 0x7B706E12; + params->PchPsePwmPinMux[13]= 0x7B707013; + params->PchPsePwmPinMux[14]= 0x4B64720A; + params->PchPsePwmPinMux[15]= 0x4B64740B; + params->PchPseSpiMosiPinMux[1]= 0x4B852003; + params->PchPseSpiMisoPinMux[1]= 0x4B853002; + params->PchPseSpiClkPinMux[1]= 0x4B854001; + params->PchPseSpiCs0PinMux[1]= 0x4B855000; + params->PchPseI2sTxPinMux[0]= 0x1B702610; + params->PchPseI2sRxPinMux[0]= 0x1B70160F; + params->PchPseI2sSfrmPinMux[0]= 0x1B704614; + params->PchPseI2sSclkPinMux[0]= 0x1B703615; + params->PchPseLh2PseSbInterruptEnable = 0x1; + params->PchPseLogOutputChannel = 0x3; + params->EnableAllThermalFunctions =0x1; + params->PchPseEcliteEnabled =0x0; + } + if (CONFIG(ENABLE_TSN)){ + params->PchPseGbeEnable[0]=config->PSE_TSN[0]; + params->PchPseGbeEnable[1]=config->PSE_TSN[1]; + + size_t sz; + params->TsnMacAddrBase = (uint32_t)cbfs_boot_map_with_leak(\ + "tsnmac.bin", \ + CBFS_TYPE_RAW, &sz); + params->TsnMacAddrSize = sz; + + params->TsnConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ + "tsnconfig.bin", \ + CBFS_TYPE_RAW, &sz); + params->TsnConfigSize = sz; + + params->PseTsnIpConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ + "psetsnipconfig.bin", \ + CBFS_TYPE_RAW, &sz); + params->PseTsnIpConfigSize = sz; + params->PchPseShellEnabled = 0x1; + params->PseTsnGbeSgmiiEnable[0]=0x1; + params->PseTsnGbeSgmiiEnable[1]=0x1; + params->PseTsnGbePhyInterfaceType[0]=0x1; + params->PseTsnGbePhyInterfaceType[1]=0x1; + } /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b Gerrit-Change-Number: 47388 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: generate ACPI BERT table
by Jonathan Zhang (Code Review) 21 Apr '21

21 Apr '21

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45392 ) Change subject: soc/intel/xeon_sp/cpx: generate ACPI BERT table ...................................................................... soc/intel/xeon_sp/cpx: generate ACPI BERT table This is a WIP patch to prove that the BERT memory region put directly above CBMEM top works well for the purpose. Right now dummy error records is used, next step is to get error record raw data from PREV_BOOT_ERR_SRC_HOB. Select ACPI_BERT as default, configure ACPI_BERT_SIZE. BERT memory region is placed directly above CBMEM top, with the size of CONFIG_ACPI_BERT_SIZE. Set up e820 memory entry for it as reserved. If ACPI_BERT is selected, fill in APEI BERT with dummy error record. When there are error records in APEI BERT region, generate ACPI BERT table. TESTED=booted on DeltaLake DVT, following are boot log excepts: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x00000000752b1fff] usable BIOS-e820: [mem 0x00000000752b2000-0x00000000777fbfff] type 16 BIOS-e820: [mem 0x00000000777fc000-0x00000000777fffff] reserved <-- BERT region BIOS-e820: [mem 0x0000000078000000-0x000000008fffffff] reserved BIOS-e820: [mem 0x00000000fd000000-0x00000000fdffffff] reserved BIOS-e820: [mem 0x00000000fed40000-0x00000000fed44fff] reserved BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000183fffffff] usable ... [ 13.624688] BERT: Error records from previous boot: [ 13.634676] [Hardware Error]: event severity: fatal [ 13.644666] [Hardware Error]: precise tstamp: 2020-09-15 02:15:53 [ 13.657329] [Hardware Error]: Error 0, type: fatal [ 13.667317] [Hardware Error]: section_type: general processor error [ 13.680509] [Hardware Error]: processor_type: 0, IA32/X64 [ 13.691919] [Hardware Error]: error_type: 0x02 [ 13.701368] [Hardware Error]: TLB error [ 13.709578] [Hardware Error]: version_info: 0x000000000005065b [ 13.721885] [Hardware Error]: processor_id: 0x0000000000000000 Change-Id: Ifb23883a6f0d4d737ba08e256fb927e9965cb803 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/uncore.c 3 files changed, 82 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45392/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 8e7e6f1..bba1eb3 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -87,4 +87,20 @@ int default 512 +config ACPI_BERT + bool "Build ACPI BERT Table" + default y + depends on HAVE_ACPI_TABLES + help + Report Machine Check errors identified in POST to the OS in an + ACPI Boot Error Record Table. + +config ACPI_BERT_SIZE + hex + default 0x4000 if ACPI_BERT + default 0x0 + help + Specify the amount of DRAM reserved for gathering the BERT error + records. + endif diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1328257..3abc530 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/bert_storage.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <assert.h> @@ -12,6 +13,7 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/acpi.h> +#include <lib.h> #include <hob_iiouds.h> #include <hob_memmap.h> #include <soc/acpi.h> @@ -878,6 +880,37 @@ return current; } +#ifdef CONFIG_ACPI_BERT +void bert_reserved_region(void **start, size_t *size) +{ + *start = cbmem_top(); + *size = CONFIG_ACPI_BERT_SIZE; + assert(*start); + memset(*start, 0, *size); + printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%lx\n", *start, *size); +} + +static bool fill_bert_region(void) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + cper_proc_generic_error_section_t *gen_sec; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status){ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); + return false; + } + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + gen_sec->error_type = GENPROC_ERRTYPE_TLB; + gen_sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; + + return true; +} +#endif + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) @@ -885,6 +918,7 @@ acpi_srat_t *srat; acpi_slit_t *slit; acpi_dmar_t *dmar; + acpi_bert_t *bert; const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device); @@ -917,5 +951,26 @@ acpi_add_table(rsdp, dmar); } + if (CONFIG(ACPI_BERT)) { + /* Fill BERT region. Return if not filled in. */ + if(!fill_bert_region()) + return current; + + void *rgn = NULL; + size_t size = 0; + bert_errors_region(&rgn, &size); + printk(BIOS_INFO, "BERT region base: %p, error record size: 0x%lx\n", rgn, size); + /* Add BERT table */ + if (rgn && size) { + hexdump(rgn, size); + current = ALIGN(current, 8); + bert = (acpi_bert_t *)current; + acpi_write_bert(bert, (uintptr_t)rgn, size); + acpi_add_table(rsdp, (void *)current); + current += bert->header.length; + } else { + printk(BIOS_ERR, "BERT region is not filled.\n"); + } + } return current; } diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a549acb..d640c1d 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -153,6 +153,7 @@ uint64_t mc_values[NUM_MAP_ENTRIES]; struct resource *resource; int index = *res_count; + uintptr_t cbmem_top_addr = (uintptr_t)cbmem_top(); fsp_find_reserved_memory(&fsp_mem); @@ -162,7 +163,7 @@ top_of_ram = range_entry_base(&fsp_mem) - 1; printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", - (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem), + cbmem_top_addr, range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ @@ -178,8 +179,7 @@ ram_resource(dev, index++, base_kb, size_kb); /* - * FSP meomoy, CBMem regions are already added as reserved - * Add TSEG and MESEG Regions as reserved memory + * FSP memory, CBMem regions are already added as reserved * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM reserved size * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE * typically 0x2000 @@ -192,6 +192,14 @@ * FspBootLoaderTolum Size : 2000 */ + /* Mark APEI BERT region as reserved */ + if (CONFIG(ACPI_BERT)) { + base_kb = (cbmem_top_addr >> 10); + size_kb = (CONFIG_ACPI_BERT_SIZE >> 10); + LOG_MEM_RESOURCE("apei_bert", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + } + /* Mark TSEG/SMM region as reserved */ base_kb = (mc_values[TSEG_BASE_REG] >> 10); size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10; -- To view, visit https://review.coreboot.org/c/coreboot/+/45392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb23883a6f0d4d737ba08e256fb927e9965cb803 Gerrit-Change-Number: 45392 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: cpu/x86/smm: Always use SMM_LOADER_VERSION2
by Arthur Heymans (Code Review) 21 Apr '21

21 Apr '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47073 ) Change subject: cpu/x86/smm: Always use SMM_LOADER_VERSION2 ...................................................................... cpu/x86/smm: Always use SMM_LOADER_VERSION2 This removes the old SMM_LOADER_VERSION1. The version 2 should now work in all the cases version 1 supported. This might need a bit more testing. TODO: The save state handling inside the smihandler code is only correct for the code that previously worked for V1. This needs to be fixed for systems with a large amount of CPUs Change-Id: If52e38ebd2baf4fc80d433e65626c537c0c1f1aa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c D src/cpu/x86/smm/smm_module_loaderv2.c M src/include/cpu/x86/smm.h 7 files changed, 407 insertions(+), 846 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/47073/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index b3a16bc..5394cd0 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -121,14 +121,6 @@ endif -config X86_SMM_LOADER_VERSION2 - bool - default n - depends on HAVE_SMI_HANDLER - help - This option enables SMM module loader that works with server - platforms which may contain more than 32 CPU threads. - config SMM_LAPIC_REMAP_MITIGATION bool default y if NORTHBRIDGE_INTEL_I945 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3deab6d..f880c87 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -726,17 +726,12 @@ * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. */ -#if CONFIG(X86_SMM_LOADER_VERSION2) perm_smbase = smm_get_cpu_smbase(cpu); mp_state.perm_smbase = perm_smbase; if (!perm_smbase) { printk(BIOS_ERR, "%s: bad SMBASE for CPU %d\n", __func__, cpu); return; } -#else - perm_smbase = mp_state.perm_smbase; - perm_smbase -= cpu * runtime->save_state_size; -#endif /* Setup code checks this callback for validity. */ printk(BIOS_INFO, "%s : curr_smbase 0x%x perm_smbase 0x%x, cpu = %d\n", @@ -772,7 +767,7 @@ smm_stacks = memalign(16, num_cpus * CONFIG_SMM_STUB_STACK_SIZE); if (smm_stacks == NULL) { - printk(BIOS_ERR, "%s: failed to allocate stacks.\n"); + printk(BIOS_ERR, "%s: failed to allocate stacks.\n", __func__); return -1; } diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 1273a6c..dbe567a 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,10 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_X86_SMM_LOADER_VERSION2),y) -ramstage-y += smm_module_loaderv2.c -else ramstage-y += smm_module_loader.c -endif ramstage-y += smi_trigger.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684..b6ef077 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -91,6 +91,7 @@ struct global_nvs *gnvs; +/* TODO: handle multiple segments! */ void *smm_get_save_state(int cpu) { char *base; diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 3c0ed7e..54e46d4 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stdint.h> #include <string.h> -#include <acpi/acpi_gnvs.h> #include <rmodule.h> #include <cpu/x86/smm.h> #include <commonlib/helpers.h> @@ -9,7 +9,7 @@ #include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 - +#define SMM_CODE_SEGMENT_SIZE 0x10000 /* FXSAVE area during relocation. While it may not be strictly needed the SMM stub code relies on the FXSAVE area being non-zero to enable SSE instructions within SMM mode. */ @@ -47,65 +47,239 @@ /* Per CPU minimum stack size. */ #define SMM_MINIMUM_STACK_SIZE 32 +struct cpu_smm_info { + uint8_t active; + uintptr_t smbase; + uintptr_t entry; + uintptr_t ss_start; + uintptr_t code_start; + uintptr_t code_end; +}; +struct cpu_smm_info cpus[CONFIG_MAX_CPUS] = { 0 }; + /* - * The smm_entry_ins consists of 3 bytes. It is used when staggering SMRAM entry - * addresses across CPUs. + * This method creates a map of all the CPU entry points, save state locations + * and the beginning and end of code segments for each CPU. This map is used + * during relocation to properly align as many CPUs that can fit into the SMRAM + * region. For more information on how SMRAM works, refer to the latest Intel + * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the + * following regions: + * +-----------------+ Top of SMRAM + * | | <- MSEG, FXSAVE + * +-----------------+ + * | common | + * | smi handler | 64K + * | | + * +-----------------+ + * | CPU 0 code seg | + * +-----------------+ + * | CPU 1 code seg | + * +-----------------+ + * | CPU x code seg | + * +-----------------+ + * | | + * | | + * +-----------------+ + * | stacks | + * +-----------------+ <- START of SMRAM * - * 0xe9 <16-bit relative target> ; jmp <relative-offset> + * The code below checks when a code segment is full and begins placing the remainder + * CPUs in the lower segments. The entry point for each CPU is smbase + 0x8000 + * and save state is smbase + 0x8000 + (0x8000 - state save size). Save state + * area grows downward into the CPUs entry point. Therefore staggering too many + * CPUs in one 32K block will corrupt CPU0's entry code as the save states move + * downward. + * input : smbase of first CPU (all other CPUs + * will go below this address) + * input : num_cpus in the system. The map will + * be created from 0 to num_cpus. */ -struct smm_entry_ins { - char jmp_rel; - uint16_t rel16; -} __packed; - -/* - * Place the entry instructions for num entries beginning at entry_start with - * a given stride. The entry_start is the highest entry point's address. All - * other entry points are stride size below the previous. - */ -static void smm_place_jmp_instructions(void *entry_start, size_t stride, - size_t num, void *jmp_target) +static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, + const struct smm_loader_params *params) { - size_t i; - char *cur; - struct smm_entry_ins entry = { .jmp_rel = 0xe9 }; + unsigned int i; + struct rmodule smm_stub; + unsigned int ss_size = params->per_cpu_save_state_size, stub_size; + unsigned int smm_entry_offset = params->smm_main_entry_offset; + unsigned int seg_count = 0, segments = 0, available; + unsigned int cpus_in_segment = 0; + unsigned int base = smbase; - /* Each entry point has an IP value of 0x8000. The SMBASE for each - * CPU is different so the effective address of the entry instruction - * is different. Therefore, the relative displacement for each entry - * instruction needs to be updated to reflect the current effective - * IP. Additionally, the IP result from the jmp instruction is - * calculated using the next instruction's address so the size of - * the jmp instruction needs to be taken into account. */ - cur = entry_start; - for (i = 0; i < num; i++) { - uint32_t disp = (uintptr_t)jmp_target; - - disp -= sizeof(entry) + (uintptr_t)cur; - printk(BIOS_DEBUG, - "SMM Module: placing jmp sequence at %p rel16 0x%04x\n", - cur, disp); - entry.rel16 = disp; - memcpy(cur, &entry, sizeof(entry)); - cur -= stride; + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__); + return 0; } + + stub_size = rmodule_memory_size(&smm_stub); + /* How many CPUs can fit into one 64K segment? */ + available = 0xFFFF - smm_entry_offset - ss_size - stub_size; + if (available > 0) { + cpus_in_segment = available / ss_size; + /* minimum segments needed will always be 1 */ + segments = num_cpus / cpus_in_segment + 1; + printk(BIOS_DEBUG, + "%s: cpus allowed in one segment %d\n", __func__, cpus_in_segment); + printk(BIOS_DEBUG, + "%s: min # of segments needed %d\n", __func__, segments); + } else { + printk(BIOS_ERR, "%s: not enough space in SMM to setup all CPUs\n", __func__); + printk(BIOS_ERR, " save state & stub size need to be reduced\n"); + printk(BIOS_ERR, " or increase SMRAM size\n"); + return 0; + } + + if (sizeof(cpus) / sizeof(struct cpu_smm_info) < num_cpus) { + printk(BIOS_ERR, + "%s: increase MAX_CPUS in Kconfig\n", __func__); + return 0; + } + + if (stub_size > ss_size) { + printk(BIOS_ERR, "%s: Save state larger than SMM stub size\n", __func__); + printk(BIOS_ERR, " Decrease stub size or increase the size allocated for the save state\n"); + return 0; + } + + for (i = 0; i < num_cpus; i++) { + cpus[i].smbase = base; + cpus[i].entry = base + smm_entry_offset; + cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); + cpus[i].code_start = cpus[i].entry; + cpus[i].code_end = cpus[i].entry + stub_size; + cpus[i].active = 1; + base -= ss_size; + seg_count++; + if (seg_count >= cpus_in_segment) { + base -= smm_entry_offset; + seg_count = 0; + } + } + + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + seg_count = 0; + for (i = 0; i < num_cpus; i++) { + printk(BIOS_DEBUG, "CPU 0x%x\n", i); + printk(BIOS_DEBUG, + " smbase %zx entry %zx\n", + cpus[i].smbase, cpus[i].entry); + printk(BIOS_DEBUG, + " ss_start %zx code_end %zx\n", + cpus[i].ss_start, cpus[i].code_end); + seg_count++; + if (seg_count >= cpus_in_segment) { + printk(BIOS_DEBUG, + "-------------NEW CODE SEGMENT --------------\n"); + seg_count = 0; + } + } + } + return 1; } -/* Place stacks in base -> base + size region, but ensure the stacks don't - * overlap the staggered entry points. */ +/* + * This method expects the smm relocation map to be complete. + * This method does not read any HW registers, it simply uses a + * map that was created during SMM setup. + * input: cpu_num - cpu number which is used as an index into the + * map to return the smbase + */ +u32 smm_get_cpu_smbase(unsigned int cpu_num) +{ + if (cpu_num < CONFIG_MAX_CPUS) { + if (cpus[cpu_num].active) + return cpus[cpu_num].smbase; + } + return 0; +} + +/* + * This method assumes that at least 1 CPU has been set up from + * which it will place other CPUs below its smbase ensuring that + * save state does not clobber the first CPUs init code segment. The init + * code which is the smm stub code is the same for all CPUs. They enter + * smm, setup stacks (based on their apic id), enter protected mode + * and then jump to the common smi handler. The stack is allocated + * at the beginning of smram (aka tseg base, not smbase). The stack + * pointer for each CPU is calculated by using its apic id + * (code is in smm_stub.s) + * Each entry point will now have the same stub code which, sets up the CPU + * stack, enters protected mode and then jumps to the smi handler. It is + * important to enter protected mode before the jump because the "jump to + * address" might be larger than the 20bit address supported by real mode. + * SMI entry right now is in real mode. + * input: smbase - this is the smbase of the first cpu not the smbase + * where tseg starts (aka smram_start). All CPUs code segment + * and stack will be below this point except for the common + * SMI handler which is one segment above + * input: num_cpus - number of cpus that need relocation including + * the first CPU (though its code is already loaded) + * input: top of stack (stacks work downward by default in Intel HW) + * output: return -1, if runtime smi code could not be installed. In + * this case SMM will not work and any SMI's generated will + * cause a CPU shutdown or general protection fault because + * the appropriate smi handling code was not installed + */ + +static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, + unsigned int stack_top, const struct smm_loader_params *params) +{ + unsigned int i; + unsigned int size; + if (smm_create_map(smbase, num_cpus, params)) { + /* + * Ensure there was enough space and the last CPUs smbase + * did not encroach upon the stack. Stack top is smram start + * + size of stack. + */ + if (cpus[num_cpus].active) { + if (cpus[num_cpus - 1].smbase + + params->smm_main_entry_offset < stack_top) { + printk(BIOS_ERR, "%s: stack encroachment\n", __func__); + printk(BIOS_ERR, "%s: smbase %zx, stack_top %x\n", + __func__, cpus[num_cpus].smbase, stack_top); + return 0; + } + } + } else { + printk(BIOS_ERR, "%s: unable to place smm entry code\n", __func__); + return 0; + } + + printk(BIOS_INFO, "%s: smbase %zx, stack_top %x\n", + __func__, cpus[num_cpus-1].smbase, stack_top); + + /* start at 1, the first CPU stub code is already there */ + size = cpus[0].code_end - cpus[0].code_start; + for (i = 1; i < num_cpus; i++) { + memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); + printk(BIOS_DEBUG, + "SMM Module: placing smm entry code at %zx, cpu # 0x%x\n", + cpus[i].code_start, i); + printk(BIOS_DEBUG, "%s: copying from %zx to %zx 0x%x bytes\n", + __func__, cpus[0].code_start, cpus[i].code_start, size); + } + return 1; +} + +/* + * Place stacks in base -> base + size region, but ensure the stacks don't + * overlap the staggered entry points. + */ static void *smm_stub_place_stacks(char *base, size_t size, struct smm_loader_params *params) { size_t total_stack_size; char *stacks_top; - if (params->stack_top != NULL) - return params->stack_top; - /* If stack space is requested assume the space lives in the lower * half of SMRAM. */ total_stack_size = params->per_cpu_stack_size * params->num_concurrent_stacks; + printk(BIOS_DEBUG, "%s: cpus: %zx : stack space: needed -> %zx\n", + __func__, params->num_concurrent_stacks, + total_stack_size); + printk(BIOS_DEBUG, " available -> %zx : per_cpu_stack_size : %zx\n", + size, params->per_cpu_stack_size); /* There has to be at least one stack user. */ if (params->num_concurrent_stacks < 1) @@ -117,51 +291,53 @@ /* Stacks extend down to SMBASE */ stacks_top = &base[total_stack_size]; + printk(BIOS_DEBUG, "%s: exit, stack_top %p\n", __func__, stacks_top); return stacks_top; } -/* Place the staggered entry points for each CPU. The entry points are +/* + * Place the staggered entry points for each CPU. The entry points are * staggered by the per CPU SMM save state size extending down from - * SMM_ENTRY_OFFSET. */ -static void smm_stub_place_staggered_entry_points(char *base, + * SMM_ENTRY_OFFSET. + */ +static int smm_stub_place_staggered_entry_points(char *base, const struct smm_loader_params *params, const struct rmodule *smm_stub) { size_t stub_entry_offset; - + int rc = 1; stub_entry_offset = rmodule_entry_offset(smm_stub); - - /* If there are staggered entry points or the stub is not located - * at the SMM entry point then jmp instructions need to be placed. */ + /* Each CPU now has its own stub code, which enters protected mode, + * sets up the stack, and then jumps to common SMI handler + */ if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { - size_t num_entries; - - base += SMM_ENTRY_OFFSET; - num_entries = params->num_concurrent_save_states; - /* Adjust beginning entry and number of entries down since - * the initial entry point doesn't need a jump sequence. */ - if (stub_entry_offset == 0) { - base -= params->per_cpu_save_state_size; - num_entries--; - } - smm_place_jmp_instructions(base, - params->per_cpu_save_state_size, - num_entries, - rmodule_entry(smm_stub)); + rc = smm_place_entry_code((unsigned int)base, + params->num_concurrent_save_states, + (unsigned int)params->stack_top, params); } + return rc; } /* * The stub setup code assumes it is completely contained within the - * default SMRAM size (0x10000). There are potentially 3 regions to place + * default SMRAM size (0x10000) for the default SMI handler (entry at + * 0x30000), but no assumption should be made for the permanent SMI handler. + * The placement of CPU entry points for permanent handler are determined + * by the number of CPUs in the system and the amount of SMRAM. + * There are potentially 3 regions to place * within the default SMRAM size: * 1. Save state areas * 2. Stub code * 3. Stack areas * - * The save state and stack areas are treated as contiguous for the number of - * concurrent areas requested. The save state always lives at the top of SMRAM - * space, and the entry point is at offset 0x8000. + * The save state and smm stack are treated as contiguous for the number of + * concurrent areas requested. The save state always lives at the top of the + * the CPUS smbase (and the entry point is at offset 0x8000). This allows only a certain + * number of CPUs with staggered entry points until the save state area comes + * down far enough to overwrite/corrupt the entry code (stub code). Therefore, + * an SMM map is created to avoid this corruption, see smm_create_map() above. + * This module setup code works for the default (0x30000) SMM handler setup and the + * permanent SMM handler. */ static int smm_module_setup_stub(void *smbase, size_t smm_size, struct smm_loader_params *params, @@ -177,73 +353,67 @@ size_t i; struct smm_stub_params *stub_params; struct rmodule smm_stub; - + unsigned int total_size_all; base = smbase; - size = SMM_DEFAULT_SIZE; + size = smm_size; /* The number of concurrent stacks cannot exceed CONFIG_MAX_CPUS. */ - if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) + if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) { + printk(BIOS_ERR, "%s: not enough stacks\n", __func__); return -1; + } /* Fail if can't parse the smm stub rmodule. */ - if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s: unable to parse smm stub\n", __func__); return -1; + } /* Adjust remaining size to account for save state. */ total_save_state_size = params->per_cpu_save_state_size * params->num_concurrent_save_states; - if (total_save_state_size > size) + if (total_save_state_size > size) { + printk(BIOS_ERR, + "%s: more state save space needed:need -> %zx:available->%zx\n", + __func__, total_save_state_size, size); return -1; + } + size -= total_save_state_size; /* The save state size encroached over the first SMM entry point. */ - if (size <= SMM_ENTRY_OFFSET) + if (size <= params->smm_main_entry_offset) { + printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); + printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %x\n", + __func__, size, params->smm_main_entry_offset); return -1; + } /* Need a minimum stack size and alignment. */ if (params->per_cpu_stack_size <= SMM_MINIMUM_STACK_SIZE || - (params->per_cpu_stack_size & 3) != 0) + (params->per_cpu_stack_size & 3) != 0) { + printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); return -1; + } smm_stub_loc = NULL; smm_stub_size = rmodule_memory_size(&smm_stub); stub_entry_offset = rmodule_entry_offset(&smm_stub); - if (smm_stub_size > params->per_cpu_save_state_size) { - printk(BIOS_ERR, "SMM Module: SMM stub size larger than save state size\n"); - printk(BIOS_ERR, "SMM Module: Staggered entry points will overlap stub\n"); - return -1; - } - - /* Assume the stub is always small enough to live within upper half of - * SMRAM region after the save state space has been allocated. */ - smm_stub_loc = &base[SMM_ENTRY_OFFSET]; - - /* Adjust for jmp instruction sequence. */ - if (stub_entry_offset != 0) { - size_t entry_sequence_size = sizeof(struct smm_entry_ins); - /* Align up to 16 bytes. */ - entry_sequence_size = ALIGN_UP(entry_sequence_size, 16); - smm_stub_loc += entry_sequence_size; - smm_stub_size += entry_sequence_size; - } + /* Put the stub at the main entry point */ + smm_stub_loc = &base[params->smm_main_entry_offset]; /* Stub is too big to fit. */ - if (smm_stub_size > (size - SMM_ENTRY_OFFSET)) + if (smm_stub_size > (size - params->smm_main_entry_offset)) { + printk(BIOS_ERR, "%s: stub is too big to fit\n", __func__); return -1; - - /* The stacks, if requested, live in the lower half of SMRAM space. */ - size = SMM_ENTRY_OFFSET; - - /* Ensure stacks don't encroach onto staggered SMM - * entry points. The staggered entry points extend - * below SMM_ENTRY_OFFSET by the number of concurrent - * save states - 1 and save state size. */ - if (params->num_concurrent_save_states > 1) { - size -= total_save_state_size; - size += params->per_cpu_save_state_size; } + /* The stacks, if requested, live in the lower half of SMRAM space + * for default handler, but for relocated handler it lives at the beginning + * of SMRAM which is TSEG base + */ + const total_stack_size = params->num_concurrent_stacks * params->per_cpu_stack_size; /* Use the smbase as a proxy to know if we are installing the stub for relocation * or for permanent handling. In case of relocation the SMM relocation stack will * have been allocated on the ramstage heap and programmed in the smm loader params. @@ -251,18 +421,25 @@ if (smbase == (void *)SMM_DEFAULT_BASE) stacks_top = params->stack_top; else - /* Place the stacks in the lower half of SMRAM. */ - stacks_top = smm_stub_place_stacks(base, size, params); + stacks_top = smm_stub_place_stacks((char *)params->smram_start, size, params); - if (stacks_top == NULL) + if (stacks_top == NULL) { + printk(BIOS_ERR, "%s: not enough space for stacks\n", __func__); + printk(BIOS_ERR, "%s: ....need -> %p : available -> %zx\n", __func__, + base, total_stack_size); return -1; - + } + params->stack_top = stacks_top; /* Load the stub. */ - if (rmodule_load(smm_stub_loc, &smm_stub)) + if (rmodule_load(smm_stub_loc, &smm_stub)) { + printk(BIOS_ERR, "%s: load module failed\n", __func__); return -1; + } - /* Place staggered entry points. */ - smm_stub_place_staggered_entry_points(base, params, &smm_stub); + if (!smm_stub_place_staggered_entry_points(base, params, &smm_stub)) { + printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); + return -1; + } /* Setup the parameters for the stub code. */ stub_params = rmodule_parameters(&smm_stub); @@ -276,7 +453,31 @@ stub_params->runtime.smm_size = smm_size; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; stub_params->runtime.num_cpus = params->num_concurrent_stacks; - stub_params->runtime.gnvs_ptr = (uintptr_t)acpi_get_gnvs(); + + printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", + __func__, stub_params->stack_top - total_stack_size); + printk(BIOS_DEBUG, + "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); + printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n", + __func__, stub_params->stack_size); + printk(BIOS_DEBUG, "%s: runtime.smbase = 0x%x\n", + __func__, stub_params->runtime.smbase); + printk(BIOS_DEBUG, "%s: runtime.start32_offset = 0x%x\n", __func__, + stub_params->runtime.start32_offset); + printk(BIOS_DEBUG, "%s: runtime.smm_size = 0x%zx\n", + __func__, smm_size); + printk(BIOS_DEBUG, "%s: per_cpu_save_state_size = 0x%x\n", + __func__, stub_params->runtime.save_state_size); + printk(BIOS_DEBUG, "%s: num_cpus = 0x%x\n", __func__, + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s: total_save_state_size = 0x%x\n", + __func__, (stub_params->runtime.save_state_size * + stub_params->runtime.num_cpus)); + total_size_all = stub_params->stack_size + + (stub_params->runtime.save_state_size * + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s: total_size_all = 0x%x\n", __func__, + total_size_all); /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) @@ -287,7 +488,6 @@ printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", smm_stub_loc, params->handler, params->handler_arg); - return 0; } @@ -299,8 +499,8 @@ */ int smm_setup_relocation_handler(struct smm_loader_params *params) { - void *smram = (void *)SMM_DEFAULT_BASE; - + void *smram = (void *)(SMM_DEFAULT_BASE); + printk(BIOS_SPEW, "%s: enter\n", __func__); /* There can't be more than 1 concurrent save state for the relocation * handler because all CPUs default to 0x30000 as SMBASE. */ if (params->num_concurrent_save_states > 1) @@ -315,27 +515,35 @@ if (params->num_concurrent_stacks == 0) params->num_concurrent_stacks = CONFIG_MAX_CPUS; + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + params->smram_start = SMM_DEFAULT_BASE; + params->smram_end = SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE; return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, - params, fxsave_area_relocation); + params, fxsave_area_relocation); + printk(BIOS_SPEW, "%s: exit\n", __func__); } -/* The SMM module is placed within the provided region in the following +/* + *The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size * | BIOS resource | * | list (STM) | - * +-----------------+ <- smram + size - CONFIG_BIOS_RESOURCE_LIST_SIZE - * | stacks | - * +-----------------+ <- .. - total_stack_size + * +-----------------+ * | fxsave area | - * +-----------------+ <- .. - total_stack_size - fxsave_size + * +-----------------+ + * | smi handler | * | ... | - * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE - * | handler | - * +-----------------+ <- smram + SMM_DEFAULT_SIZE - * | stub code | - * +-----------------+ <- smram - * + * +-----------------+ <- cpu0 + * | stub code | <- cpu1 + * | stub code | <- cpu2 + * | stub code | <- cpu3, etc + * | | + * | | + * | | + * | stacks | + * +-----------------+ <- smram start + * It should be noted that this algorithm will not work for * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm * expects a region large enough to encompass the handler and stacks @@ -350,12 +558,21 @@ size_t alignment_size; size_t fxsave_size; void *fxsave_area; - size_t total_size; + size_t total_size = 0; char *base; if (size <= SMM_DEFAULT_SIZE) return -1; + /* Load main SMI handler at the top of SMRAM + * everything else will go below + */ + base = smram; + base += size; + params->smram_start = (uintptr_t)smram; + params->smram_end = params->smram_start + size; + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + /* Fail if can't parse the smm rmodule. */ if (rmodule_parse(&_binary_smm_start, &smm_mod)) return -1; @@ -366,21 +583,30 @@ total_stack_size = params->per_cpu_stack_size * params->num_concurrent_stacks; + total_size += total_stack_size; + /* Stacks are the base of SMRAM */ + params->stack_top = smram + total_stack_size; - /* Stacks start at the top of the region. */ - base = smram; - base += size; - - if (CONFIG(STM)) + /* MSEG starts at the top of SMRAM and works down */ + if (CONFIG(STM)) { base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + } - params->stack_top = base; + /* FXSAVE goes below MSEG */ + if (CONFIG(SSE)) { + fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; + fxsave_area = base - fxsave_size; + base -= fxsave_size; + total_size += fxsave_size; + } else { + fxsave_size = 0; + fxsave_area = NULL; + } - /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment - * taken into account. */ - base = smram; - base += SMM_DEFAULT_SIZE; handler_size = rmodule_memory_size(&smm_mod); + base -= handler_size; + total_size += handler_size; module_alignment = rmodule_load_alignment(&smm_mod); alignment_size = module_alignment - ((uintptr_t)base % module_alignment); @@ -389,22 +615,20 @@ base += alignment_size; } - if (CONFIG(SSE)) { - fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; - /* FXSAVE area below all the stacks stack. */ - fxsave_area = params->stack_top; - fxsave_area -= total_stack_size + fxsave_size; - } else { - fxsave_size = 0; - fxsave_area = NULL; - } + printk(BIOS_DEBUG, + "%s: total_smm_space_needed %zx, available -> %zx\n", + __func__, total_size, size); /* Does the required amount of memory exceed the SMRAM region size? */ - total_size = total_stack_size + handler_size; - total_size += fxsave_size + SMM_DEFAULT_SIZE; - - if (total_size > size) + if (total_size > size) { + printk(BIOS_ERR, "%s: need more SMRAM\n", __func__); return -1; + } + if (handler_size > SMM_CODE_SEGMENT_SIZE) { + printk(BIOS_ERR, "%s: increase SMM_CODE_SEGMENT_SIZE: handler_size = %zx\n", + __func__, handler_size); + return -1; + } if (rmodule_load(base, &smm_mod)) return -1; @@ -412,5 +636,33 @@ params->handler = rmodule_entry(&smm_mod); params->handler_arg = rmodule_parameters(&smm_mod); - return smm_module_setup_stub(smram, size, params, fxsave_area); + printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", + __func__, smram); + printk(BIOS_DEBUG, "%s: smram_end: %p\n", + __func__, smram + size); + printk(BIOS_DEBUG, "%s: stack_top: %p\n", + __func__, params->stack_top); + printk(BIOS_DEBUG, "%s: handler start %p\n", + __func__, params->handler); + printk(BIOS_DEBUG, "%s: handler_size %zx\n", + __func__, handler_size); + printk(BIOS_DEBUG, "%s: handler_arg %p\n", + __func__, params->handler_arg); + printk(BIOS_DEBUG, "%s: fxsave_area %p\n", + __func__, fxsave_area); + printk(BIOS_DEBUG, "%s: fxsave_size %zx\n", + __func__, fxsave_size); + printk(BIOS_DEBUG, "%s: CONFIG_MSEG_SIZE 0x%x\n", + __func__, CONFIG_MSEG_SIZE); + printk(BIOS_DEBUG, "%s: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x%x\n", + __func__, CONFIG_BIOS_RESOURCE_LIST_SIZE); + + /* CPU 0 smbase goes first, all other CPUs + * will be staggered below + */ + base -= SMM_CODE_SEGMENT_SIZE; + printk(BIOS_DEBUG, "%s: cpu0 entry: %p\n", + __func__, base); + params->smm_entry = (uintptr_t)base + params->smm_main_entry_offset; + return smm_module_setup_stub(base, size, params, fxsave_area); } diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c deleted file mode 100644 index 54e46d4..0000000 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ /dev/null @@ -1,668 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <string.h> -#include <rmodule.h> -#include <cpu/x86/smm.h> -#include <commonlib/helpers.h> -#include <console/console.h> -#include <security/intel/stm/SmmStm.h> - -#define FXSAVE_SIZE 512 -#define SMM_CODE_SEGMENT_SIZE 0x10000 -/* FXSAVE area during relocation. While it may not be strictly needed the - SMM stub code relies on the FXSAVE area being non-zero to enable SSE - instructions within SMM mode. */ -static uint8_t fxsave_area_relocation[CONFIG_MAX_CPUS][FXSAVE_SIZE] -__attribute__((aligned(16))); - -/* - * Components that make up the SMRAM: - * 1. Save state - the total save state memory used - * 2. Stack - stacks for the CPUs in the SMM handler - * 3. Stub - SMM stub code for calling into handler - * 4. Handler - C-based SMM handler. - * - * The components are assumed to consist of one consecutive region. - */ - -/* These parameters are used by the SMM stub code. A pointer to the params - * is also passed to the C-base handler. */ -struct smm_stub_params { - u32 stack_size; - u32 stack_top; - u32 c_handler; - u32 c_handler_arg; - u32 fxsave_area; - u32 fxsave_area_size; - struct smm_runtime runtime; -} __packed; - -/* - * The stub is the entry point that sets up protected mode and stacks for each - * CPU. It then calls into the SMM handler module. It is encoded as an rmodule. - */ -extern unsigned char _binary_smmstub_start[]; - -/* Per CPU minimum stack size. */ -#define SMM_MINIMUM_STACK_SIZE 32 - -struct cpu_smm_info { - uint8_t active; - uintptr_t smbase; - uintptr_t entry; - uintptr_t ss_start; - uintptr_t code_start; - uintptr_t code_end; -}; -struct cpu_smm_info cpus[CONFIG_MAX_CPUS] = { 0 }; - -/* - * This method creates a map of all the CPU entry points, save state locations - * and the beginning and end of code segments for each CPU. This map is used - * during relocation to properly align as many CPUs that can fit into the SMRAM - * region. For more information on how SMRAM works, refer to the latest Intel - * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the - * following regions: - * +-----------------+ Top of SMRAM - * | | <- MSEG, FXSAVE - * +-----------------+ - * | common | - * | smi handler | 64K - * | | - * +-----------------+ - * | CPU 0 code seg | - * +-----------------+ - * | CPU 1 code seg | - * +-----------------+ - * | CPU x code seg | - * +-----------------+ - * | | - * | | - * +-----------------+ - * | stacks | - * +-----------------+ <- START of SMRAM - * - * The code below checks when a code segment is full and begins placing the remainder - * CPUs in the lower segments. The entry point for each CPU is smbase + 0x8000 - * and save state is smbase + 0x8000 + (0x8000 - state save size). Save state - * area grows downward into the CPUs entry point. Therefore staggering too many - * CPUs in one 32K block will corrupt CPU0's entry code as the save states move - * downward. - * input : smbase of first CPU (all other CPUs - * will go below this address) - * input : num_cpus in the system. The map will - * be created from 0 to num_cpus. - */ -static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, - const struct smm_loader_params *params) -{ - unsigned int i; - struct rmodule smm_stub; - unsigned int ss_size = params->per_cpu_save_state_size, stub_size; - unsigned int smm_entry_offset = params->smm_main_entry_offset; - unsigned int seg_count = 0, segments = 0, available; - unsigned int cpus_in_segment = 0; - unsigned int base = smbase; - - if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { - printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__); - return 0; - } - - stub_size = rmodule_memory_size(&smm_stub); - /* How many CPUs can fit into one 64K segment? */ - available = 0xFFFF - smm_entry_offset - ss_size - stub_size; - if (available > 0) { - cpus_in_segment = available / ss_size; - /* minimum segments needed will always be 1 */ - segments = num_cpus / cpus_in_segment + 1; - printk(BIOS_DEBUG, - "%s: cpus allowed in one segment %d\n", __func__, cpus_in_segment); - printk(BIOS_DEBUG, - "%s: min # of segments needed %d\n", __func__, segments); - } else { - printk(BIOS_ERR, "%s: not enough space in SMM to setup all CPUs\n", __func__); - printk(BIOS_ERR, " save state & stub size need to be reduced\n"); - printk(BIOS_ERR, " or increase SMRAM size\n"); - return 0; - } - - if (sizeof(cpus) / sizeof(struct cpu_smm_info) < num_cpus) { - printk(BIOS_ERR, - "%s: increase MAX_CPUS in Kconfig\n", __func__); - return 0; - } - - if (stub_size > ss_size) { - printk(BIOS_ERR, "%s: Save state larger than SMM stub size\n", __func__); - printk(BIOS_ERR, " Decrease stub size or increase the size allocated for the save state\n"); - return 0; - } - - for (i = 0; i < num_cpus; i++) { - cpus[i].smbase = base; - cpus[i].entry = base + smm_entry_offset; - cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); - cpus[i].code_start = cpus[i].entry; - cpus[i].code_end = cpus[i].entry + stub_size; - cpus[i].active = 1; - base -= ss_size; - seg_count++; - if (seg_count >= cpus_in_segment) { - base -= smm_entry_offset; - seg_count = 0; - } - } - - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { - seg_count = 0; - for (i = 0; i < num_cpus; i++) { - printk(BIOS_DEBUG, "CPU 0x%x\n", i); - printk(BIOS_DEBUG, - " smbase %zx entry %zx\n", - cpus[i].smbase, cpus[i].entry); - printk(BIOS_DEBUG, - " ss_start %zx code_end %zx\n", - cpus[i].ss_start, cpus[i].code_end); - seg_count++; - if (seg_count >= cpus_in_segment) { - printk(BIOS_DEBUG, - "-------------NEW CODE SEGMENT --------------\n"); - seg_count = 0; - } - } - } - return 1; -} - -/* - * This method expects the smm relocation map to be complete. - * This method does not read any HW registers, it simply uses a - * map that was created during SMM setup. - * input: cpu_num - cpu number which is used as an index into the - * map to return the smbase - */ -u32 smm_get_cpu_smbase(unsigned int cpu_num) -{ - if (cpu_num < CONFIG_MAX_CPUS) { - if (cpus[cpu_num].active) - return cpus[cpu_num].smbase; - } - return 0; -} - -/* - * This method assumes that at least 1 CPU has been set up from - * which it will place other CPUs below its smbase ensuring that - * save state does not clobber the first CPUs init code segment. The init - * code which is the smm stub code is the same for all CPUs. They enter - * smm, setup stacks (based on their apic id), enter protected mode - * and then jump to the common smi handler. The stack is allocated - * at the beginning of smram (aka tseg base, not smbase). The stack - * pointer for each CPU is calculated by using its apic id - * (code is in smm_stub.s) - * Each entry point will now have the same stub code which, sets up the CPU - * stack, enters protected mode and then jumps to the smi handler. It is - * important to enter protected mode before the jump because the "jump to - * address" might be larger than the 20bit address supported by real mode. - * SMI entry right now is in real mode. - * input: smbase - this is the smbase of the first cpu not the smbase - * where tseg starts (aka smram_start). All CPUs code segment - * and stack will be below this point except for the common - * SMI handler which is one segment above - * input: num_cpus - number of cpus that need relocation including - * the first CPU (though its code is already loaded) - * input: top of stack (stacks work downward by default in Intel HW) - * output: return -1, if runtime smi code could not be installed. In - * this case SMM will not work and any SMI's generated will - * cause a CPU shutdown or general protection fault because - * the appropriate smi handling code was not installed - */ - -static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, - unsigned int stack_top, const struct smm_loader_params *params) -{ - unsigned int i; - unsigned int size; - if (smm_create_map(smbase, num_cpus, params)) { - /* - * Ensure there was enough space and the last CPUs smbase - * did not encroach upon the stack. Stack top is smram start - * + size of stack. - */ - if (cpus[num_cpus].active) { - if (cpus[num_cpus - 1].smbase + - params->smm_main_entry_offset < stack_top) { - printk(BIOS_ERR, "%s: stack encroachment\n", __func__); - printk(BIOS_ERR, "%s: smbase %zx, stack_top %x\n", - __func__, cpus[num_cpus].smbase, stack_top); - return 0; - } - } - } else { - printk(BIOS_ERR, "%s: unable to place smm entry code\n", __func__); - return 0; - } - - printk(BIOS_INFO, "%s: smbase %zx, stack_top %x\n", - __func__, cpus[num_cpus-1].smbase, stack_top); - - /* start at 1, the first CPU stub code is already there */ - size = cpus[0].code_end - cpus[0].code_start; - for (i = 1; i < num_cpus; i++) { - memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); - printk(BIOS_DEBUG, - "SMM Module: placing smm entry code at %zx, cpu # 0x%x\n", - cpus[i].code_start, i); - printk(BIOS_DEBUG, "%s: copying from %zx to %zx 0x%x bytes\n", - __func__, cpus[0].code_start, cpus[i].code_start, size); - } - return 1; -} - -/* - * Place stacks in base -> base + size region, but ensure the stacks don't - * overlap the staggered entry points. - */ -static void *smm_stub_place_stacks(char *base, size_t size, - struct smm_loader_params *params) -{ - size_t total_stack_size; - char *stacks_top; - - /* If stack space is requested assume the space lives in the lower - * half of SMRAM. */ - total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; - printk(BIOS_DEBUG, "%s: cpus: %zx : stack space: needed -> %zx\n", - __func__, params->num_concurrent_stacks, - total_stack_size); - printk(BIOS_DEBUG, " available -> %zx : per_cpu_stack_size : %zx\n", - size, params->per_cpu_stack_size); - - /* There has to be at least one stack user. */ - if (params->num_concurrent_stacks < 1) - return NULL; - - /* Total stack size cannot fit. */ - if (total_stack_size > size) - return NULL; - - /* Stacks extend down to SMBASE */ - stacks_top = &base[total_stack_size]; - printk(BIOS_DEBUG, "%s: exit, stack_top %p\n", __func__, stacks_top); - - return stacks_top; -} - -/* - * Place the staggered entry points for each CPU. The entry points are - * staggered by the per CPU SMM save state size extending down from - * SMM_ENTRY_OFFSET. - */ -static int smm_stub_place_staggered_entry_points(char *base, - const struct smm_loader_params *params, const struct rmodule *smm_stub) -{ - size_t stub_entry_offset; - int rc = 1; - stub_entry_offset = rmodule_entry_offset(smm_stub); - /* Each CPU now has its own stub code, which enters protected mode, - * sets up the stack, and then jumps to common SMI handler - */ - if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { - rc = smm_place_entry_code((unsigned int)base, - params->num_concurrent_save_states, - (unsigned int)params->stack_top, params); - } - return rc; -} - -/* - * The stub setup code assumes it is completely contained within the - * default SMRAM size (0x10000) for the default SMI handler (entry at - * 0x30000), but no assumption should be made for the permanent SMI handler. - * The placement of CPU entry points for permanent handler are determined - * by the number of CPUs in the system and the amount of SMRAM. - * There are potentially 3 regions to place - * within the default SMRAM size: - * 1. Save state areas - * 2. Stub code - * 3. Stack areas - * - * The save state and smm stack are treated as contiguous for the number of - * concurrent areas requested. The save state always lives at the top of the - * the CPUS smbase (and the entry point is at offset 0x8000). This allows only a certain - * number of CPUs with staggered entry points until the save state area comes - * down far enough to overwrite/corrupt the entry code (stub code). Therefore, - * an SMM map is created to avoid this corruption, see smm_create_map() above. - * This module setup code works for the default (0x30000) SMM handler setup and the - * permanent SMM handler. - */ -static int smm_module_setup_stub(void *smbase, size_t smm_size, - struct smm_loader_params *params, - void *fxsave_area) -{ - size_t total_save_state_size; - size_t smm_stub_size; - size_t stub_entry_offset; - char *smm_stub_loc; - void *stacks_top; - size_t size; - char *base; - size_t i; - struct smm_stub_params *stub_params; - struct rmodule smm_stub; - unsigned int total_size_all; - base = smbase; - size = smm_size; - - /* The number of concurrent stacks cannot exceed CONFIG_MAX_CPUS. */ - if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) { - printk(BIOS_ERR, "%s: not enough stacks\n", __func__); - return -1; - } - - /* Fail if can't parse the smm stub rmodule. */ - if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { - printk(BIOS_ERR, "%s: unable to parse smm stub\n", __func__); - return -1; - } - - /* Adjust remaining size to account for save state. */ - total_save_state_size = params->per_cpu_save_state_size * - params->num_concurrent_save_states; - if (total_save_state_size > size) { - printk(BIOS_ERR, - "%s: more state save space needed:need -> %zx:available->%zx\n", - __func__, total_save_state_size, size); - return -1; - } - - size -= total_save_state_size; - - /* The save state size encroached over the first SMM entry point. */ - if (size <= params->smm_main_entry_offset) { - printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); - printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %x\n", - __func__, size, params->smm_main_entry_offset); - return -1; - } - - /* Need a minimum stack size and alignment. */ - if (params->per_cpu_stack_size <= SMM_MINIMUM_STACK_SIZE || - (params->per_cpu_stack_size & 3) != 0) { - printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); - return -1; - } - - smm_stub_loc = NULL; - smm_stub_size = rmodule_memory_size(&smm_stub); - stub_entry_offset = rmodule_entry_offset(&smm_stub); - - /* Put the stub at the main entry point */ - smm_stub_loc = &base[params->smm_main_entry_offset]; - - /* Stub is too big to fit. */ - if (smm_stub_size > (size - params->smm_main_entry_offset)) { - printk(BIOS_ERR, "%s: stub is too big to fit\n", __func__); - return -1; - } - - /* The stacks, if requested, live in the lower half of SMRAM space - * for default handler, but for relocated handler it lives at the beginning - * of SMRAM which is TSEG base - */ - const total_stack_size = params->num_concurrent_stacks * params->per_cpu_stack_size; - /* Use the smbase as a proxy to know if we are installing the stub for relocation - * or for permanent handling. In case of relocation the SMM relocation stack will - * have been allocated on the ramstage heap and programmed in the smm loader params. - */ - if (smbase == (void *)SMM_DEFAULT_BASE) - stacks_top = params->stack_top; - else - stacks_top = smm_stub_place_stacks((char *)params->smram_start, size, params); - - if (stacks_top == NULL) { - printk(BIOS_ERR, "%s: not enough space for stacks\n", __func__); - printk(BIOS_ERR, "%s: ....need -> %p : available -> %zx\n", __func__, - base, total_stack_size); - return -1; - } - params->stack_top = stacks_top; - /* Load the stub. */ - if (rmodule_load(smm_stub_loc, &smm_stub)) { - printk(BIOS_ERR, "%s: load module failed\n", __func__); - return -1; - } - - if (!smm_stub_place_staggered_entry_points(base, params, &smm_stub)) { - printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); - return -1; - } - - /* Setup the parameters for the stub code. */ - stub_params = rmodule_parameters(&smm_stub); - stub_params->stack_top = (uintptr_t)stacks_top; - stub_params->stack_size = params->per_cpu_stack_size; - stub_params->c_handler = (uintptr_t)params->handler; - stub_params->c_handler_arg = (uintptr_t)params->handler_arg; - stub_params->fxsave_area = (uintptr_t)fxsave_area; - stub_params->fxsave_area_size = FXSAVE_SIZE; - stub_params->runtime.smbase = (uintptr_t)smbase; - stub_params->runtime.smm_size = smm_size; - stub_params->runtime.save_state_size = params->per_cpu_save_state_size; - stub_params->runtime.num_cpus = params->num_concurrent_stacks; - - printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", - __func__, stub_params->stack_top - total_stack_size); - printk(BIOS_DEBUG, - "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); - printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n", - __func__, stub_params->stack_size); - printk(BIOS_DEBUG, "%s: runtime.smbase = 0x%x\n", - __func__, stub_params->runtime.smbase); - printk(BIOS_DEBUG, "%s: runtime.start32_offset = 0x%x\n", __func__, - stub_params->runtime.start32_offset); - printk(BIOS_DEBUG, "%s: runtime.smm_size = 0x%zx\n", - __func__, smm_size); - printk(BIOS_DEBUG, "%s: per_cpu_save_state_size = 0x%x\n", - __func__, stub_params->runtime.save_state_size); - printk(BIOS_DEBUG, "%s: num_cpus = 0x%x\n", __func__, - stub_params->runtime.num_cpus); - printk(BIOS_DEBUG, "%s: total_save_state_size = 0x%x\n", - __func__, (stub_params->runtime.save_state_size * - stub_params->runtime.num_cpus)); - total_size_all = stub_params->stack_size + - (stub_params->runtime.save_state_size * - stub_params->runtime.num_cpus); - printk(BIOS_DEBUG, "%s: total_size_all = 0x%x\n", __func__, - total_size_all); - - /* Initialize the APIC id to CPU number table to be 1:1 */ - for (i = 0; i < params->num_concurrent_stacks; i++) - stub_params->runtime.apic_id_to_cpu[i] = i; - - /* Allow the initiator to manipulate SMM stub parameters. */ - params->runtime = &stub_params->runtime; - - printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", - smm_stub_loc, params->handler, params->handler_arg); - return 0; -} - -/* - * smm_setup_relocation_handler assumes the callback is already loaded in - * memory. i.e. Another SMM module isn't chained to the stub. The other - * assumption is that the stub will be entered from the default SMRAM - * location: 0x30000 -> 0x40000. - */ -int smm_setup_relocation_handler(struct smm_loader_params *params) -{ - void *smram = (void *)(SMM_DEFAULT_BASE); - printk(BIOS_SPEW, "%s: enter\n", __func__); - /* There can't be more than 1 concurrent save state for the relocation - * handler because all CPUs default to 0x30000 as SMBASE. */ - if (params->num_concurrent_save_states > 1) - return -1; - - /* A handler has to be defined to call for relocation. */ - if (params->handler == NULL) - return -1; - - /* Since the relocation handler always uses stack, adjust the number - * of concurrent stack users to be CONFIG_MAX_CPUS. */ - if (params->num_concurrent_stacks == 0) - params->num_concurrent_stacks = CONFIG_MAX_CPUS; - - params->smm_main_entry_offset = SMM_ENTRY_OFFSET; - params->smram_start = SMM_DEFAULT_BASE; - params->smram_end = SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE; - return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, - params, fxsave_area_relocation); - printk(BIOS_SPEW, "%s: exit\n", __func__); -} - -/* - *The SMM module is placed within the provided region in the following - * manner: - * +-----------------+ <- smram + size - * | BIOS resource | - * | list (STM) | - * +-----------------+ - * | fxsave area | - * +-----------------+ - * | smi handler | - * | ... | - * +-----------------+ <- cpu0 - * | stub code | <- cpu1 - * | stub code | <- cpu2 - * | stub code | <- cpu3, etc - * | | - * | | - * | | - * | stacks | - * +-----------------+ <- smram start - - * It should be noted that this algorithm will not work for - * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm - * expects a region large enough to encompass the handler and stacks - * as well as the SMM_DEFAULT_SIZE. - */ -int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) -{ - struct rmodule smm_mod; - size_t total_stack_size; - size_t handler_size; - size_t module_alignment; - size_t alignment_size; - size_t fxsave_size; - void *fxsave_area; - size_t total_size = 0; - char *base; - - if (size <= SMM_DEFAULT_SIZE) - return -1; - - /* Load main SMI handler at the top of SMRAM - * everything else will go below - */ - base = smram; - base += size; - params->smram_start = (uintptr_t)smram; - params->smram_end = params->smram_start + size; - params->smm_main_entry_offset = SMM_ENTRY_OFFSET; - - /* Fail if can't parse the smm rmodule. */ - if (rmodule_parse(&_binary_smm_start, &smm_mod)) - return -1; - - /* Clear SMM region */ - if (CONFIG(DEBUG_SMI)) - memset(smram, 0xcd, size); - - total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; - total_size += total_stack_size; - /* Stacks are the base of SMRAM */ - params->stack_top = smram + total_stack_size; - - /* MSEG starts at the top of SMRAM and works down */ - if (CONFIG(STM)) { - base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; - total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; - } - - /* FXSAVE goes below MSEG */ - if (CONFIG(SSE)) { - fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; - fxsave_area = base - fxsave_size; - base -= fxsave_size; - total_size += fxsave_size; - } else { - fxsave_size = 0; - fxsave_area = NULL; - } - - handler_size = rmodule_memory_size(&smm_mod); - base -= handler_size; - total_size += handler_size; - module_alignment = rmodule_load_alignment(&smm_mod); - alignment_size = module_alignment - - ((uintptr_t)base % module_alignment); - if (alignment_size != module_alignment) { - handler_size += alignment_size; - base += alignment_size; - } - - printk(BIOS_DEBUG, - "%s: total_smm_space_needed %zx, available -> %zx\n", - __func__, total_size, size); - - /* Does the required amount of memory exceed the SMRAM region size? */ - if (total_size > size) { - printk(BIOS_ERR, "%s: need more SMRAM\n", __func__); - return -1; - } - if (handler_size > SMM_CODE_SEGMENT_SIZE) { - printk(BIOS_ERR, "%s: increase SMM_CODE_SEGMENT_SIZE: handler_size = %zx\n", - __func__, handler_size); - return -1; - } - - if (rmodule_load(base, &smm_mod)) - return -1; - - params->handler = rmodule_entry(&smm_mod); - params->handler_arg = rmodule_parameters(&smm_mod); - - printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", - __func__, smram); - printk(BIOS_DEBUG, "%s: smram_end: %p\n", - __func__, smram + size); - printk(BIOS_DEBUG, "%s: stack_top: %p\n", - __func__, params->stack_top); - printk(BIOS_DEBUG, "%s: handler start %p\n", - __func__, params->handler); - printk(BIOS_DEBUG, "%s: handler_size %zx\n", - __func__, handler_size); - printk(BIOS_DEBUG, "%s: handler_arg %p\n", - __func__, params->handler_arg); - printk(BIOS_DEBUG, "%s: fxsave_area %p\n", - __func__, fxsave_area); - printk(BIOS_DEBUG, "%s: fxsave_size %zx\n", - __func__, fxsave_size); - printk(BIOS_DEBUG, "%s: CONFIG_MSEG_SIZE 0x%x\n", - __func__, CONFIG_MSEG_SIZE); - printk(BIOS_DEBUG, "%s: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x%x\n", - __func__, CONFIG_BIOS_RESOURCE_LIST_SIZE); - - /* CPU 0 smbase goes first, all other CPUs - * will be staggered below - */ - base -= SMM_CODE_SEGMENT_SIZE; - printk(BIOS_DEBUG, "%s: cpu0 entry: %p\n", - __func__, base); - params->smm_entry = (uintptr_t)base + params->smm_main_entry_offset; - return smm_module_setup_stub(base, size, params, fxsave_area); -} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 1073d03..7491d95 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -128,7 +128,6 @@ * into this field so the code doing the loading can manipulate the * runtime's assumptions. e.g. updating the APIC id to CPU map to * handle sparse APIC id space. - * The following parameters are only used when X86_SMM_LOADER_VERSION2 is enabled. * - smm_entry - entry address of first CPU thread, all others will be tiled * below this address. * - smm_main_entry_offset - default entry offset (e.g 0x8000) @@ -148,22 +147,16 @@ struct smm_runtime *runtime; - /* The following are only used by X86_SMM_LOADER_VERSION2 */ -#if CONFIG(X86_SMM_LOADER_VERSION2) unsigned int smm_entry; unsigned int smm_main_entry_offset; unsigned int smram_start; unsigned int smram_end; -#endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); - -#if CONFIG(X86_SMM_LOADER_VERSION2) u32 smm_get_cpu_smbase(unsigned int cpu_num); -#endif /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/47073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If52e38ebd2baf4fc80d433e65626c537c0c1f1aa Gerrit-Change-Number: 47073 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: lock TCO base address on pch finalize
by Michael Niewöhner (Code Review) 21 Apr '21

21 Apr '21

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35525 ) Change subject: soc/intel/skylake: lock TCO base address on pch finalize ...................................................................... soc/intel/skylake: lock TCO base address on pch finalize This is a follow-up on I5bd95b3580adc0f4cffa667f8979b7cf08925720 which already locks TCO itself but does not lock the base address. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35525/1 diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..a3ebe24 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -34,6 +34,7 @@ #define TCOBASE 0x50 #define TCOCTL 0x54 #define TCO_BASE_EN (1 << 8) +#define TCO_BASE_LOCK (1 << 0) /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) @@ -61,8 +62,13 @@ void tco_lockdown(void) { + uint32_t reg32; uint16_t tcocnt; + /* TCO base address lockdown */ + reg32 = pci_read_config32(dev, TCOCTL); + pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_LOCK); + /* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); tcocnt |= TCO_LOCK; -- To view, visit https://review.coreboot.org/c/coreboot/+/35525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Gerrit-Change-Number: 35525 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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