coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: tests: Add lib/bootmem-test test case
by Jan Dabros (Code Review) 12 Apr '21

12 Apr '21

Jan Dabros has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43510 ) Change subject: tests: Add lib/bootmem-test test case ...................................................................... tests: Add lib/bootmem-test test case Signed-off-by: Jan Dabros <jsd(a)semihalf.com> Change-Id: Ic1e539061ee5051d4158712a8a981a475ea7458a --- M tests/lib/Makefile.inc A tests/lib/bootmem-test.c A tests/lib/bootmem-test.ld 3 files changed, 296 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43510/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index dae406a..69e3fd4 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += memrange-test +tests-y += bootmem-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -19,3 +20,10 @@ memrange-test-srcs += src/lib/memrange.c memrange-test-srcs += tests/stubs/console.c memrange-test-srcs += tests/mocks/device/device_util.c + +bootmem-test-srcs += tests/lib/bootmem-test.c +bootmem-test-srcs += src/lib/bootmem.c +bootmem-test-srcs += src/lib/memrange.c +bootmem-test-srcs += tests/stubs/console.c +bootmem-test-srcs += tests/mocks/device/device_util.c +bootmem-test-cflags += -Wl,--script=tests/lib/bootmem-test.ld diff --git a/tests/lib/bootmem-test.c b/tests/lib/bootmem-test.c new file mode 100644 index 0000000..8082720 --- /dev/null +++ b/tests/lib/bootmem-test.c @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <stdlib.h> + +#include <bootmem.h> +#include <commonlib/coreboot_tables.h> +#include <device/device.h> +#include <device/resource.h> +#include <memrange.h> +#include <symbols.h> + +/* Stubs defined to satisfy linker dependencies */ +void cbmem_add_bootmem(void) +{ +} + +void bootmem_arch_add_ranges(void) +{ +} + +struct bootmem_ranges_t { + uint64_t start; + uint64_t size; + uint32_t type; +}; + +struct bootmem_ranges_t *os_ranges; +struct bootmem_ranges_t *ranges; + +/* See tests/lib/bootmem-test.ld for boundaries definitions */ +extern u8 _ramstage_size[]; +#define PROGRAM_START ((uintptr_t)_program) +#define RAMSTAGE_SIZE ((uintptr_t)_ramstage_size) +#define CACHEABLE_START PROGRAM_START +#define CACHEABLE_SIZE (1ULL << 32) +#define CACHEABLE_END (CACHEABLE_START + CACHEABLE_SIZE) +#define RESERVED_START (1ULL << 32) +#define RESERVED_SIZE 0x100000 +#define RESERVED_END (RESERVED_START + RESERVED_SIZE) +#define FIRST (RESERVED_END - CACHEABLE_START) + +/* Note that second region overlaps first */ +struct resource res_mock[] = { + { .base = CACHEABLE_START, .size = CACHEABLE_SIZE, .next = &res_mock[1], + .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM }, + { .base = RESERVED_START, .size = RESERVED_SIZE, .next = NULL, + .flags = IORESOURCE_RESERVE | IORESOURCE_MEM } +}; + +/* Device simulating RAM */ +struct device mem_device_mock = { + .enabled = 1, + .resource_list = res_mock, + .next = NULL +}; + +/* Simplified version for the purpose of tests */ +static uint32_t bootmem_to_lb_tag(const enum bootmem_type tag) +{ + switch (tag) { + case BM_MEM_RAM: + return LB_MEM_RAM; + case BM_MEM_RESERVED: + return LB_MEM_RESERVED; + default: + return LB_MEM_RESERVED; + } +} + +/* Bootmem layout for bootmem tests + * + * Regions marked with asteriks (***) are not visible for OS + * + * +-------+----CACHEABLE_MEMORY---------+-+ <-0x10000000 + * | | ***PROGRAM*** | | + * | +-----------------------------+ | <-0x10040000 + * | | ***STACK*** | | + * | +-----------------------------+ | <-0x10041000 + * | | + * | | + * | | + * | +-------RESERVED_MEMORY-------+ | <-0x100000000 + * | | | | + * | | | | + * | | | | + * | +-----------------------------+ | <-0x100100000 + * | | + * | | + * +---------------------------------------+ <-0x110000000 + * + */ +static int test_basic_setup(void **state) +{ + os_ranges = (struct bootmem_ranges_t *)malloc(3 * sizeof(*os_ranges)); + + if (!os_ranges) + return -1; + + os_ranges[0].start = CACHEABLE_START; + os_ranges[0].size = RESERVED_START - CACHEABLE_START; + os_ranges[0].type = BM_MEM_RAM; + + os_ranges[1].start = RESERVED_START; + os_ranges[1].size = RESERVED_SIZE; + os_ranges[1].type = BM_MEM_RESERVED; + + os_ranges[2].start = RESERVED_END; + os_ranges[2].size = CACHEABLE_END - RESERVED_END; + os_ranges[2].type = BM_MEM_RAM; + + return 0; +} + +static int test_basic_teardown(void **state) +{ + free(os_ranges); + + return 0; +} + +/* This test need to be run first, in order to use bootmem library API */ +static void test_bootmem_write_mem_table(void **state) +{ + int i; + struct lb_memory *lb_mem; + + will_return_always(search_global_resources, &mem_device_mock); + + /* Allocate space for 5 lb_mem entries to be safe */ + lb_mem = malloc(sizeof(*lb_mem) + 5 * sizeof(struct lb_memory_range)); + + bootmem_write_memory_table(lb_mem); + + /* There should be only three entries visible in coreboot table */ + assert_int_equal(lb_mem->size, 3 * sizeof(struct lb_memory_range)); + + for (i = 0; i < lb_mem->size / sizeof(struct lb_memory_range); i++) { + assert_int_equal(unpack_lb64(lb_mem->map[i].start), os_ranges[i].start); + assert_int_equal(unpack_lb64(lb_mem->map[i].size), os_ranges[i].size); + assert_int_equal(lb_mem->map[i].type, bootmem_to_lb_tag(os_ranges[i].type)); + } + + free(lb_mem); +} + +int os_bootmem_walk_cnt; +int bootmem_walk_cnt; + +static bool verify_os_bootmem_walk(const struct range_entry *r, void *arg) +{ + assert_int_equal(range_entry_base(r), os_ranges[os_bootmem_walk_cnt].start); + assert_int_equal(range_entry_size(r), os_ranges[os_bootmem_walk_cnt].size); + assert_int_equal(range_entry_tag(r), os_ranges[os_bootmem_walk_cnt].type); + + os_bootmem_walk_cnt++; + + return true; +} + +static bool verify_bootmem_walk(const struct range_entry *r, void *arg) +{ + assert_int_equal(range_entry_base(r), ranges[bootmem_walk_cnt].start); + assert_int_equal(range_entry_size(r), ranges[bootmem_walk_cnt].size); + assert_int_equal(range_entry_tag(r), ranges[bootmem_walk_cnt].type); + + bootmem_walk_cnt++; + + return true; +} + +static int test_bootmem_walk_setup(void **state) +{ + if (test_basic_setup(state) < 0) + return -1; + + /* program and stack regions should be merged since they are neighbors */ + ranges = (struct bootmem_ranges_t *)malloc(4 * sizeof(*os_ranges)); + + ranges[0].start = PROGRAM_START; + ranges[0].size = RAMSTAGE_SIZE; + ranges[0].type = BM_MEM_RAMSTAGE; + + ranges[1].start = CACHEABLE_START + RAMSTAGE_SIZE; + ranges[1].size = RESERVED_START - ranges[1].start; + ranges[1].type = BM_MEM_RAM; + + ranges[2].start = RESERVED_START; + ranges[2].size = RESERVED_SIZE; + ranges[2].type = BM_MEM_RESERVED; + + ranges[3].start = RESERVED_END; + ranges[3].size = CACHEABLE_END - RESERVED_END; + ranges[3].type = BM_MEM_RAM; + + os_bootmem_walk_cnt = 0; + bootmem_walk_cnt = 0; + + return 0; +} + +static int test_bootmem_walk_teardown(void **state) +{ + test_basic_teardown(state); + + free(ranges); + + return 0; +} + +static void test_bootmem_walk(void **state) +{ + bootmem_walk_os_mem(verify_os_bootmem_walk, NULL); + bootmem_walk(verify_bootmem_walk, NULL); + + assert_int_equal(os_bootmem_walk_cnt, 3); + assert_int_equal(bootmem_walk_cnt, 4); +} + +static void test_bootmem_region_targets_type(void **state) +{ + int ret; + + ret = bootmem_region_targets_type(PROGRAM_START, RAMSTAGE_SIZE, BM_MEM_RAMSTAGE); + assert_int_equal(ret, 1); + + /* Below range covers two differently tagged regions */ + ret = bootmem_region_targets_type(PROGRAM_START, RAMSTAGE_SIZE, BM_MEM_RAMSTAGE + 1); + assert_int_equal(ret, 0); +} + +static void test_bootmem_allocate_buffer(void **state) +{ + void *buf; + + /* All allocated buffers should be below 32bit boundary */ + buf = bootmem_allocate_buffer((1ULL << 32)); + assert_null(buf); + + /* Try too big size for our BM_MEM_RAM range below 32bit boundary */ + buf = bootmem_allocate_buffer(RESERVED_START - PROGRAM_START); + assert_null(buf); + + /* Two working cases */ + buf = bootmem_allocate_buffer(0xE0000000); + assert_non_null(buf); + assert_in_range((uintptr_t)buf, CACHEABLE_START + RAMSTAGE_SIZE, RESERVED_START); + + buf = bootmem_allocate_buffer(0xF000000); + assert_non_null(buf); + assert_in_range((uintptr_t)buf, CACHEABLE_START + RAMSTAGE_SIZE, RESERVED_START); + + /* Run out of memory for new allocations */ + buf = bootmem_allocate_buffer(0x1000000); + assert_null(buf); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_bootmem_write_mem_table, + test_basic_setup, + test_basic_teardown), + cmocka_unit_test_setup_teardown(test_bootmem_walk, + test_bootmem_walk_setup, + test_bootmem_walk_teardown), + cmocka_unit_test(test_bootmem_allocate_buffer), + cmocka_unit_test(test_bootmem_region_targets_type) + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} diff --git a/tests/lib/bootmem-test.ld b/tests/lib/bootmem-test.ld new file mode 100644 index 0000000..eefef63 --- /dev/null +++ b/tests/lib/bootmem-test.ld @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Below values needs to be in sync with tests/lib/bootmem-test.c code, + * since there are some assumptions about overlapping regions, neighboring + * ones etc. + */ +SECTIONS { + _program = 0x10000000; + _eprogram = _program + 0x40000; + _stack = _eprogram; + _estack = _stack + 0x1000; + _ramstage_size = _estack - _program; +} +/* Below instruction is just for the default script not being overwritten by this helper */ +INSERT AFTER .rodata; -- To view, visit https://review.coreboot.org/c/coreboot/+/43510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e539061ee5051d4158712a8a981a475ea7458a Gerrit-Change-Number: 43510 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newchange

5 31

Change in coreboot[master]: mb/ocp/tiogapass: Add UART init in bootblock
by David Hendricks (Code Review) 12 Apr '21

12 Apr '21

Hello Andrey Petrov, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39270 to review the following change. Change subject: mb/ocp/tiogapass: Add UART init in bootblock ...................................................................... mb/ocp/tiogapass: Add UART init in bootblock Based off code from CB:38840 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Signed-off-by: David Hendricks <dhendrix(a)fb.com> Change-Id: I9a5c17e29173110429d66ec551be5a77b1c15538 --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c M src/soc/intel/xeon_sp/bootblock/bootblock.c 4 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39270/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index dfa8f54..0a35697 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -25,6 +25,7 @@ select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 select FSP_CAR + select SUPERIO_ASPEED_AST2400 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index f5ea591..ae5fb70 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -15,6 +15,8 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.c + ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..bed8b1a --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <intelblocks/uart.h> +#include <soc/pci_devs.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define PID_DMI 0xef + +void bootblock_mainboard_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header and another is used as SOL. + */ + pcr_write32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + pcr_write32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + /* for unidentified reason lpc_io_setup_comm_a_b() doesn't work */ + /* enable com1 and com2 and 0x3f8 and 0x2f8, and 0x2e */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + if (CONFIG(BOOTBLOCK_CONSOLE)) { + console_init(); + } +} diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 9eb7ff9..a3b7bce 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -15,11 +15,11 @@ */ #include <bootblock_common.h> +#include <console/console.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> -#include <console/console.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -56,6 +56,9 @@ void bootblock_soc_init(void) { - if (CONFIG(BOOTBLOCK_CONSOLE)) + bootblock_mainboard_init(); + + if (CONFIG(BOOTBLOCK_CONSOLE)) { printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a5c17e29173110429d66ec551be5a77b1c15538 Gerrit-Change-Number: 39270 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: payloads/LinuxBoot: make linux kernel build reproducible
by Alexander Couzens (Code Review) 09 Apr '21

09 Apr '21

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35393 ) Change subject: payloads/LinuxBoot: make linux kernel build reproducible ...................................................................... payloads/LinuxBoot: make linux kernel build reproducible Reproducible builds have to be independent from user, host, domain, time. Taken from OpenWrt (GPL2). Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35393/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 8be0926..c676f68 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -30,7 +30,11 @@ OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy KERNEL_MAKE_FLAGS = \ - ARCH=$(ARCH-y) + ARCH=$(ARCH-y) \ + KBUILD_BUILD_USER="coreboot" \ + KBUILD_BUILD_HOST="reproducible" \ + KBUILD_BUILD_TIMESTAMP="$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')" \ + KBUILD_BUILD_VERSION="0" ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) -- To view, visit https://review.coreboot.org/c/coreboot/+/35393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 Gerrit-Change-Number: 35393 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: [WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_S...
by Jamie Ryu (Code Review) 09 Apr '21

09 Apr '21

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46622 ) Change subject: [WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_STAGED ...................................................................... [WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_STAGED This adds RW_UCODE_STAGED to flashmap descriptor to enable microcode update. BUG=b:149547271 TEST=Build and boot volteer2 to OS Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I0af7469cc2767cdf5933e65f81686f9edbfa830d --- M src/mainboard/google/volteer/chromeos.fmd 1 file changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46622/1 diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 07a5464..dc0aa9d 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -8,17 +8,17 @@ # of BIOS regions start at 16MiB boundary. Since this is a 32MiB # SPI flash only the top 16MiB actually gets memory mapped. RW_LEGACY(CBFS)@0x0 0xb00000 - RW_SECTION_A@0xb00000 0x5e0000 { + RW_SECTION_A@0xb00000 0x5c0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x5cffc0 - RW_FWID_A@0x5dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x5affc0 + RW_FWID_A@0x5bffc0 0x40 } - RW_SECTION_B@0x10e0000 0x5e0000 { + RW_SECTION_B@0x10c0000 0x5c0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x5cffc0 - RW_FWID_B@0x5dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x5affc0 + RW_FWID_B@0x5bffc0 0x40 } - RW_MISC@0x16c0000 0x40000 { + RW_MISC@0x1680000 0x80000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 @@ -30,6 +30,7 @@ } RW_VPD(PRESERVE)@0x38000 0x2000 RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_UCODE_STAGED@0x40000 0x40000 } # Make WP_RO region align with SPI vendor # memory protected range specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/46622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7469cc2767cdf5933e65f81686f9edbfa830d Gerrit-Change-Number: 46622 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: cpu/smm/ssm_stub: Add x86_64 support
by Patrick Rudolph (Code Review) 08 Apr '21

08 Apr '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37392 ) Change subject: cpu/smm/ssm_stub: Add x86_64 support ...................................................................... cpu/smm/ssm_stub: Add x86_64 support Enable long mode in SMM handler. x86_32 isn't affected from this change. * Enter long mode * Add 64bit entry to GDT * Use x86_64 SysV ABI calling conventions for C code entry * Change smm_module_params' cpu to size_t as 'push' is native integer Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 2 files changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37392/1 diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f0e55f9..3feee9b 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -90,6 +90,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 smm_relocate_gdt_end: .align 4 @@ -172,11 +176,30 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#ifdef __x86_64__ + /* entry64.inc preserves ebx, esi, edi */ + mov %ecx, %edi +#include <cpu/x86/64bit/entry64.inc> + mov %edi, %ecx + +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ +#ifdef __x86_64__ + push %rbx /* uintptr_t *canary */ + push $(smm_runtime) + push %rcx /* int cpu */ + push c_handler_arg /* void *arg */ + + mov %rsp, %rdi /* *arg */ + + movl c_handler, %eax + call *%rax +#else push $0x0 /* Padding */ push $0x0 /* Padding */ push $0x0 /* Padding */ @@ -187,7 +210,7 @@ push %esp /* smm_module_params *arg (allocated on stack). */ mov c_handler, %eax call *%eax - +#endif /* Retrieve fxsave location. */ mov -4(%ebp), %edi test %edi, %edi diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b1..0de08b6 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -75,7 +75,7 @@ struct smm_module_params { void *arg; - int cpu; + size_t cpu; const struct smm_runtime *runtime; /* A canary value that has been placed at the end of the stack. * If (uintptr_t)canary != *canary then a stack overflow has occurred. -- To view, visit https://review.coreboot.org/c/coreboot/+/37392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Gerrit-Change-Number: 37392 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 36

Change in coreboot[master]: [WIP] mb/google/kahlee,zork: Remove special GPIO_2 override
by Kyösti Mälkki (Code Review) 08 Apr '21

08 Apr '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43049 ) Change subject: [WIP] mb/google/kahlee,zork: Remove special GPIO_2 override ...................................................................... [WIP] mb/google/kahlee,zork: Remove special GPIO_2 override Change-Id: I44661f05c8f517ece88714c625603579731d174b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/padmelon/gpio.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/picasso/gpio.c M src/soc/amd/stoneyridge/gpio.c 7 files changed, 3 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43049/1 diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index 7897d7b..966c69c 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -28,7 +28,7 @@ /* WLAND */ PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), #else - /* PCIE_WAKE */ + /* PCIE_WAKE, SCI */ PAD_GPI(GPIO_2, PULL_DOWN), /* DEVSLP1 - default as GPIO, do not program */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 59d7631..27db3fb 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -81,7 +81,7 @@ /* GPIO_1 - SYS_RST_ODL */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), - /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ + /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL, SCI*/ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* GPIO_3 - MEM_VOLT_SEL */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 2191793..5d5dd11 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -73,7 +73,7 @@ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ + /* PCIE_WAKE_L, SCI */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ PAD_GPI(GPIO_4, PULL_UP), diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 1bcfc8b..f66921d 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -173,8 +173,6 @@ return gpio; } -__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} - static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_cfg) { static const struct soc_amd_event *gev_tbl; @@ -184,8 +182,6 @@ iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK); iomux_read8(g->gpio); /* Flush posted write */ - soc_gpio_hook(g->gpio, g->function); - /* Clear interrupt and wake status (write 1-to-clear bits) */ uint32_t control = g->control | GPIO_INT_STATUS | GPIO_WAKE_STATUS; __gpio_setbits32(g->gpio, PAD_CFG_MASK, control); diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 92eae73..4143e81 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -340,7 +340,5 @@ int gpio_interrupt_status(gpio_t gpio); /* Implemented by soc, provides table of available GPIO mapping to Gevents */ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items); -/* May be implemented by soc to handle special cases */ -void soc_gpio_hook(uint8_t gpio, uint8_t mux); #endif /* __AMDBLOCK_GPIO_BANKS_H__ */ diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index 47c005e..78c15fe 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -38,10 +38,3 @@ *table = gpio_event_table; *items = ARRAY_SIZE(gpio_event_table); } - -void soc_gpio_hook(uint8_t gpio, uint8_t mux) -{ - /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ - if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) - soc_route_sci(GPIO_2_EVENT); -} diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index bd9d1b1..26dec3f 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -38,10 +38,3 @@ *table = gpio_event_table; *items = ARRAY_SIZE(gpio_event_table); } - -void soc_gpio_hook(uint8_t gpio, uint8_t mux) -{ - /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ - if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) - soc_route_sci(GPIO_2_EVENT); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44661f05c8f517ece88714c625603579731d174b Gerrit-Change-Number: 43049 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 17

Change in ...coreboot[master]: libpayload: nvme driver
by Thomas Heijligen (Code Review) 07 Apr '21

07 Apr '21

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33582 Change subject: libpayload: nvme driver ...................................................................... libpayload: nvme driver Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M payloads/libpayload/drivers/Makefile.inc M payloads/libpayload/drivers/storage/Kconfig A payloads/libpayload/drivers/storage/nvme.c M payloads/libpayload/drivers/storage/storage.c A payloads/libpayload/include/storage/nvme.h M payloads/libpayload/include/storage/storage.h M payloads/libpayload/include/x86/arch/io.h A payloads/libpayload/sample/nvme_test.c 8 files changed, 429 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33582/1 diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 40e587c..676dbd3 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -77,6 +77,7 @@ libc-$(CONFIG_LP_STORAGE) += storage/storage.c libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci_common.c +libc-$(CONFIG_LP_STORAGE_NVME) += storage/nvme.c ifeq ($(CONFIG_LP_STORAGE_ATA),y) libc-$(CONFIG_LP_STORAGE_ATA) += storage/ata.c libc-$(CONFIG_LP_STORAGE_ATA) += storage/ahci_ata.c diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig index 04e9a29..3eabf6a 100644 --- a/payloads/libpayload/drivers/storage/Kconfig +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -57,3 +57,10 @@ help If this option is selected only AHCI controllers which are known to work will be used. + +config STORAGE_NVME + bool "Support for NVMe devices" + depends on STORAGE && PCI + default y + help + Select this option if you want support for NVMe devices diff --git a/payloads/libpayload/drivers/storage/nvme.c b/payloads/libpayload/drivers/storage/nvme.c new file mode 100644 index 0000000..871759d --- /dev/null +++ b/payloads/libpayload/drivers/storage/nvme.c @@ -0,0 +1,331 @@ +#include <libpayload.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <pci.h> +#include <pci/pci.h> +#include <storage/nvme.h> +#include <storage/storage.h> + +#define PCI_CLASS_CODE_NVME 0x0108 + +// NVME Controller Configuration +#define NVME_CC_EN (1 << 0) +#define NVME_CC_CSS (0 << 4) +#define NVME_CC_MPS (0 << 7) +#define NVME_CC_AMS (0 << 11) +#define NVME_CC_SHN (0 << 14) +#define NVME_CC_IOSQES (6 << 16) +#define NVME_CC_IOCQES (4 << 20) + +#define NVME_QUEUE_SIZE 2 +#define NVME_SQ_ENTRY_SIZE 64 +#define NVME_CQ_ENTRY_SIZE 16 + +struct nvme_s_queue_entry { + uint32_t dw[16]; +}; + +struct nvme_c_queue_entry { + uint32_t dw[4]; +}; + +enum nvme_queue { + NVME_ADMIN_QUEUE = 0, + NVME_IO_QUEUE = 2, + ads = 0, + adc = 1, + ios = 2, + ioc = 3, +}; + +static storage_poll_t nvme_poll(struct storage_dev *dev); +static void nvme_detach_device(struct storage_dev *dev); +static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf); + +static int create_admin_queues(struct nvme_dev *nvme); +static int create_io_submission_queue(struct nvme_dev *nvme); +static int create_io_completion_queue(struct nvme_dev *nvme); +static void delete_admin_queues(struct nvme_dev *nvme); +static void delete_io_submission_queue(struct nvme_dev *nvme); +static void delete_io_completion_queue(struct nvme_dev *nvme); +static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd); +static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count); + + +static storage_poll_t nvme_poll(struct storage_dev *dev) +{ + return POLL_MEDIUM_PRESENT; +} + +static void nvme_detach_device(struct storage_dev *dev) +{ + //nvme_free(dev->driver_struct); + // FIXME remove from list +} + +static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf) +{ + void *buffer = memalign(0x1000, count * 512); + if (!buffer) + return 0; + + for (int i = 0; i < count; i++) { + if (read((struct nvme_dev*)dev, buffer+(i*512), start + i, 1)) { + free(buffer); + return 0; + } + } + + memcpy(buf, buffer, count * 512); + free(buffer); + return count; +} + +static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count) +{ + if (count == 0) + return -1; + + struct nvme_s_queue_entry e = { + .dw[0] = 0x02, + .dw[1] = 0x1, + .dw[6] = virt_to_phys(buffer), + .dw[10] = base, + .dw[11] = base >> 32, + .dw[12] = count - 1, + }; + return nvme_cmd(nvme, ios, &e); +} + +static void delete_io_submission_queue(struct nvme_dev *nvme) +{ + // TODO +} + +static int create_io_submission_queue(struct nvme_dev *nvme) +{ + void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + if (!sq_buffer) { + printf("NVMe ERROR: Faild to allocate memory for io submission queue.\n"); + return -1; + } + memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + + struct nvme_s_queue_entry e = { + .dw[0] = 0x01, + .dw[6] = virt_to_phys(sq_buffer), + .dw[10] = (NVME_QUEUE_SIZE << 16) | ios >> 1, + .dw[11] = (1 << 16) | 1, + }; + + int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e); + if (res) { + printf("NVMe ERROR: nvme_cmd returned with %i.\n", res); + free(sq_buffer); + return res; + } + + uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf; + nvme->queue[ios].base = sq_buffer; + nvme->queue[ios].bell = nvme->config + 0x1000 + (ios * (4 << cap_dstrd)); + nvme->queue[ios].idx = 0; + return 0; +} + +static void delete_io_completion_queue(struct nvme_dev *nvme) +{ + // TODO +} + +static int create_io_completion_queue(struct nvme_dev *nvme) +{ + void *const cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + if (!cq_buffer) { + printf("NVMe ERROR: Faild to allocate memory for io competion queue.\n"); + return -1; + } + memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + + const struct nvme_s_queue_entry e = { + .dw[0] = 0x05, + .dw[6] = virt_to_phys(cq_buffer), + .dw[10] = (NVME_QUEUE_SIZE << 16) | ioc >> 1, + .dw[11] = 1, + }; + + int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e); + if (res) { + printf("NVMe ERROR: nvme_cmd returned with %i.\n", res); + free(cq_buffer); + return res; + } + + uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf; + nvme->queue[ioc].base = cq_buffer; + nvme->queue[ioc].bell = nvme->config + 0x1000 + (ioc * (4 << cap_dstrd)); + nvme->queue[ioc].idx = 0; + nvme->queue[ioc].round = 0; + + return 0; +} + +static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd) +{ + int sq = q, cq = q+1; + + void *s_entry = nvme->queue[sq].base + (nvme->queue[sq].idx * NVME_SQ_ENTRY_SIZE); + memcpy(s_entry, cmd, NVME_SQ_ENTRY_SIZE); + write32(nvme->queue[sq].bell, nvme->queue[sq].idx + 1); + nvme->queue[sq].idx = (nvme->queue[sq].idx + 1) & 1; + + struct nvme_c_queue_entry *c_entry = nvme->queue[cq].base + (nvme->queue[cq].idx * NVME_CQ_ENTRY_SIZE); + while (((c_entry->dw[3] >> 16 ) & 0x1) == nvme->queue[cq].round) + ; // FIXME timeout + write32(nvme->queue[cq].bell, nvme->queue[cq].idx + 1); + nvme->queue[cq].idx = (nvme->queue[cq].idx + 1) & 1; + if (nvme->queue[cq].idx == 0) + nvme->queue[cq].round = (nvme->queue[cq].round + 1) & 1; + return c_entry->dw[3] >> 17; +} + +static void delete_admin_queues(struct nvme_dev *nvme) +{ + free(nvme->queue[ads].base); + free(nvme->queue[adc].base); + // TODO clean nvme admin queue struct ??? +} + +static int create_admin_queues(struct nvme_dev *nvme) +{ + uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf; + write32(nvme->config + 0x24, NVME_QUEUE_SIZE << 16 | NVME_QUEUE_SIZE); + + void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + if (!sq_buffer) { + printf("NVMe ERROR: faild to allocated memory for admin submission queue\n"); + return -1; + } + memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + write64(nvme->config + 0x28, virt_to_phys(sq_buffer)); + + nvme->queue[ads].base = sq_buffer; + nvme->queue[ads].bell = nvme->config + 0x1000 + (ads * (4 << cap_dstrd)); + nvme->queue[ads].idx = 0; + + void *cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + if (!cq_buffer) { + printf("NVMe ERROR: Faild to allocate memory for admin completion queue\n"); + free(cq_buffer); + return -1; + } + memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE); + write64(nvme->config + 0x30, virt_to_phys(cq_buffer)); + + nvme->queue[adc].base = cq_buffer; + nvme->queue[adc].bell = nvme->config + 0x1000 + (adc * (4 << cap_dstrd)); + nvme->queue[adc].idx = 0; + nvme->queue[adc].round = 0; + + return 0; +} + +static void nvme_init(pcidev_t dev) +{ + printf("NVMe init (Device %02x:%02x.%02x)\n", PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev)); + + void *pci_bar0 = phys_to_virt(pci_read_config32(dev, 0x10) & ~0x3ff); + + if ( !(((read64(pci_bar0) >> 37 ) & 0xff) == 0x01)) { + printf("NVMe ERROR: PCIe device does not support the NVMe command set\n"); + return; + } + + struct nvme_dev *nvme = malloc(sizeof(*nvme)); + if (!nvme) { + printf("NVMe ERROR: Faild to allocate buffer for nvme driver struct\n"); + return; + } + nvme->storage_dev.port_type = PORT_TYPE_NVME; + nvme->storage_dev.poll = nvme_poll; + nvme->storage_dev.read_blocks512 = nvme_read_blocks512; + nvme->storage_dev.write_blocks512 = NULL; // not implemented + nvme->storage_dev.detach_device = nvme_detach_device; + nvme->config = pci_bar0; + + uint32_t cc = 0; + write32(nvme->config + 0x1c, 0); + + int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500; + do { + status = read32(nvme->config + 0x1c) & 0x3; + if (status == 0x2) { + printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n"); + goto abort; + } + if (timeout < 0) { + printf("NVMe ERROR: Faild to disable controller. Timeout.\n"); + goto abort; + } + timeout -= 10; + mdelay(10); + } while (status != 0x0); + + if (create_admin_queues(nvme)) + goto abort; + + cc = NVME_CC_EN | NVME_CC_CSS | NVME_CC_MPS | NVME_CC_AMS |NVME_CC_SHN + | NVME_CC_IOSQES | NVME_CC_IOCQES; + write32(nvme->config + 0x14, cc); + + timeout = (read64(nvme->config) >> 24 & 0xff) * 500; + do { + status = read32(nvme->config + 0x1c) & 0x3; + if (status == 0x2) { + printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n"); + goto abort; + } + if (timeout < 0) { + printf("NVMe ERROR: Faild to disable controller. Timeout.\n"); + goto abort; + } + timeout -= 10; + mdelay(10); + } while (status != 0x1); + + uint16_t command = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); + + if (create_io_completion_queue(nvme)) + goto abort; + if (create_io_submission_queue(nvme)) + goto abort; + + storage_attach_device((storage_dev_t*)nvme); + printf("NVMe init done.\n"); + return; + +abort: + delete_io_submission_queue(nvme); + delete_io_completion_queue(nvme); + delete_admin_queues(nvme); + free(nvme); + printf("failed\n"); + return; +} + +void nvme_initialize(void) +{ + int bus, dev, func; + uint16_t class; + + for (bus = 0; bus < 256; ++bus) { + for (dev = 0; dev < 32; ++dev) { + for (func = 0; func < 8; ++func) { + class = pci_read_config16(PCI_DEV(bus, dev, func), 0xa); + if (class == PCI_CLASS_CODE_NVME) + nvme_init(PCI_DEV(bus, dev, func)); + } + } + } +} diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index a7141ee..55cb60d 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -31,6 +31,9 @@ #if CONFIG(LP_STORAGE_AHCI) # include <storage/ahci.h> #endif +#if CONFIG(LP_STORAGE_NVME) +#include <storage/nvme.h> +#endif #include <storage/storage.h> @@ -113,4 +116,7 @@ #if CONFIG(LP_STORAGE_AHCI) ahci_initialize(); #endif +#if CONFIG(LP_STORAGE_NVME) + nvme_initialize(); +#endif } diff --git a/payloads/libpayload/include/storage/nvme.h b/payloads/libpayload/include/storage/nvme.h new file mode 100644 index 0000000..090c6d0 --- /dev/null +++ b/payloads/libpayload/include/storage/nvme.h @@ -0,0 +1,22 @@ +#ifndef _STORAGE_NVME_H +#define _STORAGE_NVME_H + +#include <stdint.h> +#include "storage.h" + +struct nvme_dev { + storage_dev_t storage_dev; + + void *config; + void *admin_s_queue; + struct { + void *base; + uint32_t *bell; + uint16_t idx; // bool pos 0 or 1 + uint16_t round; // bool round 0 or 1+0xd + } queue[4]; +}; + +void nvme_initialize(void); + +#endif /* _STORAGE_NVME_H */ diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h index 2dc70b0..d1f998e 100644 --- a/payloads/libpayload/include/storage/storage.h +++ b/payloads/libpayload/include/storage/storage.h @@ -45,6 +45,7 @@ PORT_TYPE_IDE = (1 << 0), PORT_TYPE_SATA = (1 << 1), PORT_TYPE_USB = (1 << 2), + PORT_TYPE_NVME = (1 << 3), } storage_port_t; typedef enum { diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index c417ce0..46836d9 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -64,6 +64,11 @@ return *((volatile uint32_t *)(addr)); } +static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr) +{ + return *((volatile uint64_t *)(addr)); +} + static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; @@ -79,6 +84,11 @@ *((volatile uint32_t *)(addr)) = value; } +static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value) +{ + *((volatile uint64_t *)(addr)) = value; +} + static inline unsigned int inl(int port) { unsigned long val; diff --git a/payloads/libpayload/sample/nvme_test.c b/payloads/libpayload/sample/nvme_test.c new file mode 100644 index 0000000..d2bdf10 --- /dev/null +++ b/payloads/libpayload/sample/nvme_test.c @@ -0,0 +1,51 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Example file for libpayload. */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <storage/storage.h> + +#define STORAGE_ID 0 + +int main(void) +{ + printf("---------- TEST PROGRAM BEGIN ----------\n"); + storage_initialize(); + + void *buffer = memalign(0x1000, 0x2000); + storage_read_blocks512(STORAGE_ID, 0, 15, buffer); + printf("\nbuffer content:\n"); + //hexdump(buffer,0x2000); + + printf("----------- TEST PROGRAM END -----------\n"); + halt(); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c Gerrit-Change-Number: 33582 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

7 28

Change in coreboot[master]: nb/intel/i440bx: Enable bootblock console
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41461 ) Change subject: nb/intel/i440bx: Enable bootblock console ...................................................................... nb/intel/i440bx: Enable bootblock console Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41461/1 diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 8a6783e..d51cc0c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -4,7 +4,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select NO_BOOTBLOCK_CONSOLE config SDRAMPWR_4DIMM bool -- To view, visit https://review.coreboot.org/c/coreboot/+/41461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18 Gerrit-Change-Number: 41461 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/asus/p2b: Add option table support
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41560 ) Change subject: mb/asus/p2b: Add option table support ...................................................................... mb/asus/p2b: Add option table support Just do it already. The two SCSI-specific options for p2b-{ls,ds} will be wired up in a followup. They will be ignored by other boards without the hardware. Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Kconfig A src/mainboard/asus/p2b/cmos.default A src/mainboard/asus/p2b/cmos.layout 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41560/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f21de71..762207c 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -17,6 +17,7 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 + select HAVE_OPTION_TABLE select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS diff --git a/src/mainboard/asus/p2b/cmos.default b/src/mainboard/asus/p2b/cmos.default new file mode 100644 index 0000000..447726f --- /dev/null +++ b/src/mainboard/asus/p2b/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +nmi=Enable +udma_enable=Enable +scsi_lvd_term=Enable +scsi_se_term=Enable diff --git a/src/mainboard/asus/p2b/cmos.layout b/src/mainboard/asus/p2b/cmos.layout new file mode 100644 index 0000000..5fd379f --- /dev/null +++ b/src/mainboard/asus/p2b/cmos.layout @@ -0,0 +1,74 @@ +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +#409 2 e 5 power_on_after_fail +411 1 e 1 udma_enable + +# ----------------------------------------------------------------- +# p2b-[ld]s config options: onboard SCSI termination +# Controls PIIX4 GPO22 (Ultra2-68) and GPO23 (SCSI-50) +412 1 e 1 scsi_se_term +413 1 e 2 scsi_lvd_term + +# ----------------------------------------------------------------- +# TODO: raminit config options +#415 1 e 6 ram_timing +#416 1 e 5 srp_timing +#417 1 e 5 srcd_timing +#418 1 e 5 cas_latency + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable +# Inverted on/off enum +2 0 Enable +2 1 Disable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +#5 0 3 +#5 1 2 + +#6 0 Auto +#6 1 Manual + +checksums + +checksum 592 975 976 + + -- To view, visit https://review.coreboot.org/c/coreboot/+/41560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4 Gerrit-Change-Number: 41560 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: sb/intel/i82371eb: Claim less I/O ports in ACPI
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41093 ) Change subject: sb/intel/i82371eb: Claim less I/O ports in ACPI ...................................................................... sb/intel/i82371eb: Claim less I/O ports in ACPI To avoid resource conflicts, this change leaves unclaimed: - PM and SMBus ports (claimed by MBRS device written in SSDT) - Ports 0x2e-0x2f (After reviewing Asus P3B-F OEM firmware) Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 1 file changed, 4 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41093/1 diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 8b60edb..45e7a5e 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -31,15 +31,13 @@ { Name (BUF1, ResourceTemplate () { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) /* PIIX4E ports */ /* Aliased DMA ports */ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, ) + IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, ) /* Aliased timer ports */ IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) @@ -49,18 +47,10 @@ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + /* W83977TF/EF Super I/O config ports */ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) Return (BUF1) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/41093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Gerrit-Change-Number: 41093 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 18

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020