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Change in coreboot[master]: mb/google/volteer: Add support for USB Type-C ports
by John Zhao (Code Review) 15 Jun '21

15 Jun '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40425 ) Change subject: mb/google/volteer: Add support for USB Type-C ports ...................................................................... mb/google/volteer: Add support for USB Type-C ports Two usb type-c ports under the actual Mux device. Each port has its own ACPI device entry (node). These nodes are the ones that the USB Type-C port/connnector devices will refer to in order to configure the mux. BUG=b:151646486 BRANCH=None TEST=Verify USB Type-C alternate mode (DP or TBT) along wth PMC control. Change-Id: I4b443a1ca1c5361652a69586b340b1c95e9c3f06 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- A src/mainboard/google/volteer/acpi/usbc.asl M src/mainboard/google/volteer/dsdt.asl 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40425/1 diff --git a/src/mainboard/google/volteer/acpi/usbc.asl b/src/mainboard/google/volteer/acpi/usbc.asl new file mode 100644 index 0000000..b185b2f --- /dev/null +++ b/src/mainboard/google/volteer/acpi/usbc.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0.PMC.MUX) { + /* + * Mux driver looks for usb type-C devices underneath it through + * _DSD and _ADR, where _ADR specifies the device address on the + * parent bus. CON0 is representing the first type-C port and CON1 + * is representing the second. + */ + Device (CON0) + { + Name (_ADR, 0) + /* + * These properties should have the values that the driver needs + * to supply to the PMC via IPC when the muxes are being + * configured. + */ + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb2-port", 6 }, + Package () { "usb3-port", 3 }, + Package () { "sbu-orientation", "normal" }, + Package () { "hsl-orientation", "normal" }, + }, + }) + } + + Device (CON1) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb2-port", 5 }, + Package () { "usb3-port", 2 }, + Package () { "sbu-orientation", "normal" }, + Package () { "hsl-orientation", "normal" }, + }, + }) + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 640f7cd..1888267 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -50,4 +50,7 @@ /* Camera */ #include <soc/intel/tigerlake/acpi/ipu.asl> #include "acpi/mipi_camera.asl" + + /* usbc */ + #include "acpi/usbc.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/40425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b443a1ca1c5361652a69586b340b1c95e9c3f06 Gerrit-Change-Number: 40425 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: nb/intel/sandybridge: x86_64 support
by Patrick Rudolph (Code Review) 15 Jun '21

15 Jun '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44677 ) Change subject: nb/intel/sandybridge: x86_64 support ...................................................................... nb/intel/sandybridge: x86_64 support Add experimental x86_64 support. Tested on HP Z220: * Still boots on x86_32. * Boots to payload with CB:37395 applied on x86_64. Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smihandler.c 7 files changed, 51 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..97c8234 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_206AX +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select MMX select SSE2 select UDELAY_TSC diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..892b3e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1957,9 +1957,12 @@ { unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; + uintptr_t addr; - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + 4 * j; + write32((void *)addr, j & 2 ? b : a); + } sfence(); } @@ -1977,13 +1980,16 @@ unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); + uintptr_t addr; - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); - - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); - + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + j * 4; + write32((void *)addr, 0xffffffff); + } + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + channel_step + j * 4; + write32((void *)addr, 0); + } sfence(); } @@ -2925,14 +2931,14 @@ if (invert[patno - 1][i] & (1 << (j / 2))) val = ~val; - write32((void *)((1 << 26) + offset + i * step + j * 4), val); + write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); } } } else { for (i = 0; i < ARRAY_SIZE(pattern); i++) { for (j = 0; j < 16; j++) { const u32 val = pattern[i][j]; - write32((void *)((1 << 26) + offset + i * step + j * 4), val); + write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); } } sfence(); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15be4ab..39d3b66 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -212,7 +212,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2407d92..a108b42 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -265,18 +265,18 @@ { printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(CIR5, ~0U, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0U, (1 << 14)); RCBA32(DMC) = 0xc0388400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x050f0000; RCBA32(CIR8) = 0x04000000; - RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)); + RCBA32_AND_OR(CIR10, ~0U, 0xfffff); + RCBA32_AND_OR(CIR11, ~0U, (1 << 1)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -378,10 +378,10 @@ reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEB007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEB004000, ~0U, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEC004000, ~0U, (1 << 7)); reg32 = RCBA32(CG); reg32 |= (1 << 31); @@ -672,7 +672,7 @@ /* Add it to DSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1c56e5e..7337eae 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -438,7 +438,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 484f0f1..c350186 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -142,7 +142,7 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 7211da3..26b9074 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -96,23 +96,23 @@ case ACPI_S4: /* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */ reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 &= ~0x03UL; + reg16 &= ~0x03U; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFU; /* FIXME: This looks broken (conditions are always false) */ if ((xhci_bar + 0x4C0) & 1) - pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000082, ~0U, (3 << 2)); if ((xhci_bar + 0x4D0) & 1) - pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000182, ~0U, (3 << 2)); if ((xhci_bar + 0x4E0) & 1) - pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000282, ~0U, (3 << 2)); if ((xhci_bar + 0x4F0) & 1) - pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000382, ~0U, (3 << 2)); pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); @@ -192,7 +192,7 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; if (smm_region_overlaps_handler(&r)) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/44677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Gerrit-Change-Number: 44677 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: [WIP, HACK] broadwell: make uart support build again
by Angel Pons (Code Review) 14 Jun '21

14 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37553 ) Change subject: [WIP, HACK] broadwell: make uart support build again ...................................................................... [WIP, HACK] broadwell: make uart support build again @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ @ @ DO NOT MERGE AS-IS! @ @ @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ I am fully aware this is an atrociously hideous kludge. Moreover, this change won't be properly build-tested by Mr. Jenkins, and it has not been tested on real hardware either. It only exists for backup purposes. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/serialio.c 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37553/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..61b62c8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += romstage/uart.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c @@ -16,6 +17,9 @@ bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S +postcar-y += romstage/uart.c +ramstage-y += romstage/uart.c + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a1a29b6..43c62a9 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -14,13 +14,15 @@ */ #include <device/pci_def.h> +#include <console/uart.h> #include <reg_script.h> #include <stdint.h> -#include <uart8250.h> #include <soc/iobp.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> #include <soc/serialio.h> -const struct reg_script uart_init[] = { +const struct reg_script uart_init_script[] = { /* Set MMIO BAR */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), /* Enable Memory access and Bus Master */ @@ -41,6 +43,11 @@ REG_SCRIPT_END }; +uintptr_t uart_platform_base(int idx) +{ + return CONFIG_TTYS0_BASE; +} + void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ @@ -72,11 +79,11 @@ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); /* Initialize chipset uart interface */ - reg_script_run_on_dev(dev, uart_init); + reg_script_run_on_dev(dev, uart_init_script); /* * Perform standard UART initialization * Divisor 1 is 115200 BAUD */ - uart8250_mem_init(CONFIG_TTYS0_BASE, 1); + uart_init(0); } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 161c875..50daa3f 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -282,7 +282,8 @@ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - uartmem_setbaseaddr(res->base); + printk(BIOS_ERR, "UART base address changed\n"); + //uartmem_setbaseaddr(res->base); } #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/37553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Gerrit-Change-Number: 37553 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: [UNTESTED]cpu/x86/mp_init.c: Print out the SMM save state revision wh...
by Arthur Heymans (Code Review) 14 Jun '21

14 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45478 ) Change subject: [UNTESTED]cpu/x86/mp_init.c: Print out the SMM save state revision when relocating ...................................................................... [UNTESTED]cpu/x86/mp_init.c: Print out the SMM save state revision when relocating This can be used to determine the save state revision of a CPU. Change-Id: I751d226a9de60f5dd03fd2bcb8c473bdbd5923a0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45478/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4..3a48f1a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -721,6 +721,8 @@ return; } + printk(BIOS_DEBUG, "SMM save state revision: 0x%x\n", smm_revision()); + /* * The permanent handler runs with all cpus concurrently. Precalculate * the location of the new SMBASE. If using SMM modules then this -- To view, visit https://review.coreboot.org/c/coreboot/+/45478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751d226a9de60f5dd03fd2bcb8c473bdbd5923a0 Gerrit-Change-Number: 45478 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/common/smihandler.c: Add common gnvs update mechanism
by Arthur Heymans (Code Review) 14 Jun '21

14 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45476 ) Change subject: sb/intel/common/smihandler.c: Add common gnvs update mechanism ...................................................................... sb/intel/common/smihandler.c: Add common gnvs update mechanism With common save state handling there is no need for per southbridge handling. Change-Id: I9dc0258f1335c678f992e8ad83f96b73fc474ec8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 8 files changed, 12 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45476/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 8af1428..e24a53e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -184,18 +184,6 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 52b83dd..c71ff0b 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -130,7 +130,6 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index ff61c6f..cb42832 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -8,7 +8,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <elog.h> #include <halt.h> #include <option.h> @@ -268,7 +268,13 @@ "SMI#: SMM structures already initialized!\n"); return; } - southbridge_update_gnvs(reg8, &smm_initialized); + int node = get_apmc_node(reg8); + + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } break; case APM_CNT_FINALIZE: if (mainboard_finalized) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 562dae3..fa91c37 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,10 +21,6 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f..3ca507f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,10 +14,6 @@ struct global_nvs *gnvs; #endif -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 16ec025..f5e9b75 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -15,10 +15,6 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 2bc31cf..5bf18c9 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -145,18 +145,6 @@ #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index a033d68..007b383 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -221,7 +221,7 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; + int node; static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -269,10 +269,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { + node = get_apmc_node(reg8); + if (node >= 0) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc0258f1335c678f992e8ad83f96b73fc474ec8 Gerrit-Change-Number: 45476 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: mb/lenovo/x220/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Jun '21

09 Jun '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37297 ) Change subject: mb/lenovo/x220/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x220/devicetree: Use subsystemid inheritance Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x220/devicetree.cb 1 file changed, 15 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37297/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 26fa1a4..5ae1427 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21db - end # host bridge + subsystemid 0x17aa 0x21db inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21db - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -80,49 +78,29 @@ device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21db - end # High Definition Audio - device pci 1c.0 on - subsystemid 0x17aa 0x21db - end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21db - end # PCIe Port #2 (wlan) - device pci 1c.2 on - subsystemid 0x17aa 0x21db - end # PCIe Port #3 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21db smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21db chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21db - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21db chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,11 +150,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21db - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21db # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -190,9 +165,7 @@ end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21db - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Gerrit-Change-Number: 37297 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/bd82x6x: Add missing ID for PCI bridge
by James (Code Review) 07 Jun '21

07 Jun '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41015 ) Change subject: sb/intel/bd82x6x: Add missing ID for PCI bridge ...................................................................... sb/intel/bd82x6x: Add missing ID for PCI bridge The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge" was missing. Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41015/1 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..757bdeb 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -58,8 +58,14 @@ .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x244e, /* Desktop */ + 0x2448, /* Mobile */ + 0 +}; + static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Gerrit-Change-Number: 41015 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR
by Arthur Heymans (Code Review) 07 Jun '21

07 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46503 ) Change subject: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR ...................................................................... soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR In MADT loop over each stack and compare it against the same IO APIC ID table as during the DMAR table generation. This fixes Linux (5.8) warning: "DMAR-IR: [Firmware Bug]: ioapic 12 has no mapping iommu, interrupt remapping will be disabled" Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 42 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46503/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4a..c7172b2 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -78,49 +78,56 @@ unsigned long acpi_fill_madt(unsigned long current) { - int cur_index; - struct iiostack_resource stack_info = {0}; + int cur_index = 0; + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ - int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; + const int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + assert(hob != NULL && hob_size != 0); /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); - cur_index = 0; - get_iiostack_info(&stack_info); + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * Add entry for PCH IOAPIC. + */ + { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[0].StackRes[0]; + const int gsi_base = gsi_bases[cur_index]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for PCH: ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + PCH_IOAPIC_ID, ri->IoApicBase, gsi_base); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, PCH_IOAPIC_ID, + ri->IoApicBase, gsi_base); + cur_index++; + } - for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ri->IoApicBase, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase, gsi_base); - ++cur_index; - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. - */ - if (stack == 0) { /* PCH IOAPIC */ - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + // DRHD + for (int iio = 0; iio < hob->PlatformData.numofIIO; ++iio) { + for (int stack = 0; stack < MAX_IIO_STACK; stack++) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[iio].StackRes[stack]; + if (ri->Personality != TYPE_UBOX_IIO) + continue; + const int ioapic_id = IoApicID[(iio * MAX_IIO_STACK) + stack]; + const int gsi_base = gsi_bases[cur_index]; + uint32_t apic_base = ri->IoApicBase; + if (iio == 0 && stack == 0) + apic_base += 0x1000; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + ioapic_id, apic_base, gsi_base); ++cur_index; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Gerrit-Change-Number: 46503 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: [TEST] Enable link time optimization
by Jacob Garber (Code Review) 05 Jun '21

05 Jun '21

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40815 ) Change subject: [TEST] Enable link time optimization ...................................................................... [TEST] Enable link time optimization Enable LTO to shake out the bugs. Current problems: - GCC does not track symbol origins when using LTO, so it must be disabled for AGESA so it can be excluded from the illegal_globals check. - GCC segfaults when compiling ARMV7 - Most of the Google boards do not compile because of a missing reference to _watchdog_tombstone Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/Kconfig M src/vendorcode/amd/agesa/Makefile.inc 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40815/1 diff --git a/src/Kconfig b/src/Kconfig index e4821e8..375bca2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,7 +116,7 @@ config LTO bool "Use link time optimization (LTO)" - default n + default y depends on COMPILER_GCC help Compile with link time optimization. This can often decrease the diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..3e4a53c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -14,6 +14,12 @@ AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing +# GCC currently does not track symbol origins when using LTO, so +# AGESA gets caught in the illegal_globals check. Disable for now. +ifeq ($(CONFIG_LTO),y) +AGESA_CFLAGS += -fno-lto +endif + CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/40815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Gerrit-Change-Number: 40815 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44014 ) Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ...................................................................... src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE This patch ensures that the TSEG region is only mapped as cacheable so that one can perform SMRAM relocation faster. Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) and other ranges as reserve alone. TEST=Able to build and boot ICL, TGL RVP. Without this CL: PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL: PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e12e07c..b15ca01 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -173,8 +173,13 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TSEG */ base_k = top_of_ram; + size_k = sa_map_values[SA_TSEG_REG] - base_k; + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + + /* TSEG -> BGSM */ + base_k = sa_map_values[SA_TSEG_REG]; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/44014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Gerrit-Change-Number: 44014 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020