coreboot-gerrit November 2020

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Change in coreboot[master]: Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer...
by Michael Niewöhner (Code Review) 25 Sep '21

25 Sep '21

Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Subrata Banik, Aamir Bohra, Aaron Durbin, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45000 to review the following change. Change subject: Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled" ...................................................................... Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled" This reverts commit e5269a8fd975fa0cba0655cd41f7f8cc99a1feb8. Reason for revert: BIOS spec says, emulation shall be always enabled. Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681 --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45000/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6682cdc..b0eaa5d 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -384,14 +384,8 @@ */ static void enable_pm_timer_emulation(void) { - const struct soc_intel_cannonlake_config *config; + /* ACPI PM timer emulation */ msr_t msr; - - config = config_of_path(SA_DEVFN_ROOT); - - /* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) - return; /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. -- To view, visit https://review.coreboot.org/c/coreboot/+/45000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681 Gerrit-Change-Number: 45000 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: util/abuild: Run `make .xcompile` only once
by Nico Huber (Code Review) 24 Sep '21

24 Sep '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42640 ) Change subject: util/abuild: Run `make .xcompile` only once ...................................................................... util/abuild: Run `make .xcompile` only once If abuild called itself recursively, the file already exists and we can spare us one evaluation of all the makefiles per recursive abuild run. Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42640/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 022567d..d41fcd1 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -769,8 +769,6 @@ exit 1 fi -$MAKE -C"${ROOT}" .xcompile || exit 1 - customizing=$(echo "$customizing" | cut -c3-) if [ "$customizing" = "" ]; then customizing="default configuration" @@ -780,6 +778,7 @@ PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)" if [ "$recursive" = "false" ]; then + $MAKE -C"${ROOT}" .xcompile || exit 1 rm -f "$FAILED_BOARDS" "$PASSED_BOARDS" fi -- To view, visit https://review.coreboot.org/c/coreboot/+/42640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Gerrit-Change-Number: 42640 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: soc/amd/common: Refactor program_gpios() for overrides
by Kyösti Mälkki (Code Review) 22 Sep '21

22 Sep '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43050 ) Change subject: soc/amd/common: Refactor program_gpios() for overrides ...................................................................... soc/amd/common: Refactor program_gpios() for overrides Some GPIO listed in override_cfg may not be programmed. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 20 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/43050/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index b52d7f1..1019d79 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -189,7 +189,16 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - size_t i; + return gpio_configure_pads_with_override(gpio_list_ptr, size, NULL, 0); +} + +void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, + size_t base_num_pads, + const struct soc_amd_gpio *override_cfg, + size_t override_num_pads) +{ + const struct soc_amd_gpio *c; + size_t i, j; /* * Disable blocking wake/interrupt status generation while updating @@ -203,8 +212,16 @@ */ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); - for (i = 0; i < size; i++) - set_single_gpio(&gpio_list_ptr[i]); + for (i = 0; i < base_num_pads; i++) { + c = &base_cfg[i]; + for (j = 0; override_cfg && j < override_num_pads; j++) { + if (c->gpio == override_cfg[j].gpio) { + c = &override_cfg[j]; + break; + } + } + set_single_gpio(c); + } /* * Re-enable interrupt status generation. @@ -229,36 +246,3 @@ return 0; } - -/* - * This function checks to see if there is an override config present for the - * provided pad_config. If no override config is present, then the input config - * is returned. Else, it returns the override config. - */ -static const struct soc_amd_gpio *gpio_get_config(const struct soc_amd_gpio *c, - const struct soc_amd_gpio *override_cfg_table, - size_t num) -{ - size_t i; - if (override_cfg_table == NULL) - return c; - for (i = 0; i < num; i++) { - if (c->gpio == override_cfg_table[i].gpio) - return override_cfg_table + i; - } - return c; -} -void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, - size_t base_num_pads, - const struct soc_amd_gpio *override_cfg, - size_t override_num_pads) -{ - size_t i; - const struct soc_amd_gpio *c; - - for (i = 0; i < base_num_pads; i++) { - c = gpio_get_config(base_cfg + i, override_cfg, - override_num_pads); - program_gpios(c, 1); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Gerrit-Change-Number: 43050 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: [WIP]arch/arm: Allow program loading of Linux kernels
by Arthur Heymans (Code Review) 17 Sep '21

17 Sep '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35409 ) Change subject: [WIP]arch/arm: Allow program loading of Linux kernels ...................................................................... [WIP]arch/arm: Allow program loading of Linux kernels On ARM the linux kernel takes 3 arguments: r0 = 0 r1 = machine_type (0xffffffff if using FDT) r2 = &fdt To allow this, a function with a different signature needs to be used when using a FIT payload. Change-Id: Ie0dcc26d647941de71669345911ba288341b834b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/boot.c 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35409/1 diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 9d1e4cd..fd7ba68 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -11,15 +11,29 @@ * GNU General Public License for more details. */ +#include <cbfs.h> #include <arch/cache.h> #include <program_loading.h> void arch_prog_run(struct prog *prog) { void (*doit)(void *); + void (*doit_3)(void *, void *, void *); + char *program_arg = prog_entry_arg(prog); cache_sync_instructions(); - doit = prog_entry(prog); - doit(prog_entry_arg(prog)); + /* The Linux kernel takes 3 dword's as argument */ + switch (prog_cbfs_type(prog)) { + case CBFS_TYPE_FIT: /* Flattened image tree */ + if (CONFIG(PAYLOAD_FIT_SUPPORT)) { + doit_3 = prog_entry(prog); + doit_3((void *)program_arg, (void *)(program_arg + sizeof(void *)), + (void *)(program_arg + 2 * sizeof(void *))); + break; + } /* else fall-through */ + default: + doit = prog_entry(prog); + doit((void *)program_arg); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dcc26d647941de71669345911ba288341b834b Gerrit-Change-Number: 35409 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: mb/up/squared: set primary GPU in the devicetree
by Maxim Polyakov (Code Review) 14 Sep '21

14 Sep '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39375 ) Change subject: mb/up/squared: set primary GPU in the devicetree ...................................................................... mb/up/squared: set primary GPU in the devicetree Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/up/squared/devicetree.cb M src/mainboard/up/squared/romstage.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/39375/1 diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index d7281a6..6ba3bf4 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/apollolake + # Set IGD as the primary graphics device + register "primary_gpu" = "PRIMARY_IGD" + # Override USB port configuration register "usb_config_override" = "1" # USB 2.0 diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 55235a8..fd06559 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -169,7 +169,6 @@ config->RmtCheckRun = 0x3; // 0x0 config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 config->EnhancePort8xhDecoding = 0x0; // 0x1 - config->PrimaryVideoAdaptor = 0x2; // 0x0 config->Ch0_DeviceWidth = 0x1; // 0x0 config->Ch0_Option = 0x3; // 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Gerrit-Change-Number: 39375 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: autoport: search for the HDA device on PCH
by Iru Cai (vimacs) (Code Review) 06 Sep '21

06 Sep '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34357 to review the following change. Change subject: autoport: search for the HDA device on PCH ...................................................................... autoport: search for the HDA device on PCH Haswell has its Mini-HD device and is at card0, so we need to search for the PCH HD Audio device instead of using card0. Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/log_maker.go 1 file changed, 53 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34357/1 diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go index 08b35d2..2a524d3 100644 --- a/util/autoport/log_maker.go +++ b/util/autoport/log_maker.go @@ -9,6 +9,7 @@ "os" "os/exec" "strings" + "bytes" ) func TryRunAndSave(output string, name string, arg []string) error { @@ -74,6 +75,44 @@ return } +func MakeHDALogs(outDir string, cardName string) { + SysDir := "/sys/class/sound/" + cardName + "/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/" + cardName + "/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } +} + func MakeLogs(outDir string) { os.MkdirAll(outDir, 0700) RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") @@ -97,40 +136,23 @@ RunAndSave(outDir+"/ectool.log", "../ectool/ectool", "-pd") RunAndSave(outDir+"/superiotool.log", "../superiotool/superiotool", "-ade") - SysDir := "/sys/class/sound/card0/" - files, _ := ioutil.ReadDir(SysDir) - for _, f := range files { - if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { - in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") - defer in.Close() - if err != nil { - log.Fatal(err) + SysSound := "/sys/class/sound/" + card := "" + cards, _ := ioutil.ReadDir(SysSound) + for _, f := range cards { + if strings.HasPrefix(f.Name(), "card") { + cid, err := ioutil.ReadFile(SysSound + f.Name() + "/id") + if err == nil && bytes.Equal(cid, []byte("PCH\n")) { + fmt.Fprintln(os.Stderr, "PCH sound card is", f.Name()) + card = f.Name() } - out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) - if err != nil { - log.Fatal(err) - } - defer out.Close() - io.Copy(out, in) } } - ProcDir := "/proc/asound/card0/" - files, _ = ioutil.ReadDir(ProcDir) - for _, f := range files { - if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { - in, err := os.Open(ProcDir + f.Name()) - defer in.Close() - if err != nil { - log.Fatal(err) - } - out, err := os.Create(outDir + "/" + f.Name()) - if err != nil { - log.Fatal(err) - } - defer out.Close() - io.Copy(out, in) - } + if card != "" { + MakeHDALogs(outDir, card) + } else { + fmt.Fprintln(os.Stderr, "HDAudio not found on PCH.") } for _, fname := range []string{"cpuinfo", "ioports"} { @@ -154,7 +176,7 @@ defer out.Close() ClassInputDir := "/sys/class/input/" - files, _ = ioutil.ReadDir(ClassInputDir) + files, _ := ioutil.ReadDir(ClassInputDir) for _, f := range files { if strings.HasPrefix(f.Name(), "input") && !f.Mode().IsRegular() { /* Allow both dirs and symlinks. */ in, err := os.Open(ClassInputDir + f.Name() + "/id/bustype") -- To view, visit https://review.coreboot.org/c/coreboot/+/34357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4 Gerrit-Change-Number: 34357 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: inteltool: Support dumping IOBP register values
by Iru Cai (vimacs) (Code Review) 06 Sep '21

06 Sep '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41473 to review the following change. Change subject: inteltool: Support dumping IOBP register values ...................................................................... inteltool: Support dumping IOBP register values Currently only LynxPoint IOBP registers are added. The SATA IOBP registers are found in coreboot sb/intel/lynxpoint, and the USB IOBP registers are found in mrc.bin. Tested with Dell Latitude E7240, which fails to read SATA_IOBP_SP*G3IR (does LynxPoint really use them?) and reads other IOBP registers successfully. Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/inteltool/Makefile M util/inteltool/inteltool.h A util/inteltool/iobp.c M util/inteltool/rootcmplx.c 4 files changed, 153 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41473/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 1ae04d4..3b692fd 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -16,7 +16,7 @@ OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o lpc.o + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o lpc.o iobp.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index b314fe4..6c361b4 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -386,6 +386,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_lpc(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); +void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, size_t* community_count, diff --git a/util/inteltool/iobp.c b/util/inteltool/iobp.c new file mode 100644 index 0000000..dafcb00 --- /dev/null +++ b/util/inteltool/iobp.c @@ -0,0 +1,149 @@ +/* inteltool - dump all registers on an Intel CPU + chipset based system */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdio.h> +#include <stdlib.h> +#include "inteltool.h" + +#define RCBA8(x) (*((volatile u8 *)(rcba + x))) +#define RCBA16(x) (*((volatile u16 *)(rcba + x))) +#define RCBA32(x) (*((volatile u32 *)(rcba + x))) +#define RCBA64(x) (*((volatile u64 *)(rcba + x))) +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 +#define IOBPU 0x233a +#define IOBPU_MAGIC 0xf000 + +#define IOBP_RETRY 1000 +static inline int iobp_poll(volatile uint8_t *rcba) +{ + for (int try = IOBP_RETRY; try > 0; try --) { + u16 status = RCBA16(IOBPS); + if ((status & IOBPS_READY) == 0) + return 1; + // udelay(10); + } + + printf("IOBP: timeout waiting for transaction to complete\n"); + return 0; +} + +static u32 pch_iobp_read(volatile uint8_t *rcba, u32 address) +{ + u16 status; + + if (!iobp_poll(rcba)) + return 0; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_READ; + RCBA16(IOBPS) = status; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll(rcba)) + return 0; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printf("IOBP: read 0x%08x failed\n", address); + return 0; + } + + /* Read IOBP data */ + return RCBA32(IOBPD); +} + +typedef struct { + u32 addr; + char *name; +} iobp_register_t; + +static const iobp_register_t lynxpoint_iobp_registers[] = { + /* SATA IOBP */ + {0xea000151, "SATA_IOBP_SP0G3IR"}, + {0xea000051, "SATA_IOBP_SP1G3IR"}, + {0xea002550, "SATA_IOBP_SP0DTLE_DATA"}, + {0xea002554, "SATA_IOBP_SP0DTLE_EDGE"}, + {0xea002750, "SATA_IOBP_SP1DTLE_DATA"}, + {0xea002754, "SATA_IOBP_SP1DTLE_EDGE"}, + /* USB port IOBP */ + {0xe5004100, "USBP01"}, + {0xe5004200, "USBP02"}, + {0xe5004300, "USBP03"}, + {0xe5004400, "USBP04"}, + {0xe5004500, "USBP05"}, + {0xe5004600, "USBP06"}, + {0xe5004700, "USBP07"}, + {0xe5004800, "USBP08"}, + /* LynxPoint-LP doesn't have port 9-14, the IOBP values are zero */ + {0xe5004900, "USBP09"}, + {0xe5004a00, "USBP10"}, + {0xe5004b00, "USBP11"}, + {0xe5004c00, "USBP12"}, + {0xe5004d00, "USBP13"}, + {0xe5004e00, "USBP14"}, +}; + +void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba) +{ + const iobp_register_t *iobp_registers = NULL; + size_t iobp_size = 0; + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_C8_MOBILE: + case PCI_DEVICE_ID_INTEL_C8_DESKTOP: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: + iobp_registers = lynxpoint_iobp_registers; + iobp_size = ARRAY_SIZE(lynxpoint_iobp_registers); + break; + default: + break; + } + + if (iobp_size == 0) + return; + + printf("\n============= IOBP ==============\n\n"); + + for (size_t i = 0; i < iobp_size; i++) { + u32 address = iobp_registers[i].addr; + const char *name = iobp_registers[i].name; + u32 v = pch_iobp_read(rcba, address); + printf("0x%08x: 0x%08x (%s)\n", address, v, name); + } +} diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 490897f..9819af5 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -138,6 +138,8 @@ printf("0x%04x: 0x%08x\n", i, read32(rcba + i)); } + print_iobp(sb, rcba); + unmap_physical((void *)rcba, size); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9 Gerrit-Change-Number: 41473 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 22

Change in coreboot[master]: mb/google/volteer/var/elemi: Disable Pcie setting for non-emmc sku
by Chen Wisley (Code Review) 30 Aug '21

30 Aug '21

Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47355 to review the following change. Change subject: mb/google/volteer/var/elemi: Disable Pcie setting for non-emmc sku ...................................................................... mb/google/volteer/var/elemi: Disable Pcie setting for non-emmc sku BUG=none BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I5fbdb9de81066100d28040bdbc044b8cec10188f --- M src/mainboard/google/volteer/variants/elemi/Makefile.inc A src/mainboard/google/volteer/variants/elemi/variant.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47355/1 diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc index b0bfc56..e34a40b 100644 --- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/elemi/variant.c b/src/mainboard/google/volteer/variants/elemi/variant.c new file mode 100644 index 0000000..4e14e1a --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/variant.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> + +void variant_devtree_update(void) +{ + config_t *cfg = config_of_soc(); + if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_PRESENT))){ + if (cfg) { + cfg->PcieRpEnable[4] = 0; + cfg->PcieRpLtrEnable[4] = 0; + cfg->PcieRpHotPlug[4] = 0; + cfg->PcieClkSrcUsage[5] = 0xff; + cfg->PcieClkSrcClkReq[5] = 0xff; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fbdb9de81066100d28040bdbc044b8cec10188f Gerrit-Change-Number: 47355 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Documentation: Add documentation for resource allocator
by Furquan Shaikh (Code Review) 25 Aug '21

25 Aug '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43603 ) Change subject: Documentation: Add documentation for resource allocator ...................................................................... Documentation: Add documentation for resource allocator This change adds documentation for resource allocator in coreboot which captures the expectations from device and platform drivers and details about resource allocator v3 and v4. Change-Id: I887284b44df2bf871f45c3a93fbef9cfc37e42a0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A Documentation/device/index.md A Documentation/device/resource_allocation.md M Documentation/index.md 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43603/1 diff --git a/Documentation/device/index.md b/Documentation/device/index.md new file mode 100644 index 0000000..9b703d6 --- /dev/null +++ b/Documentation/device/index.md @@ -0,0 +1,6 @@ +# Device management specific documentation + +This section contains documentation about device management in +coreboot. + +- [Resource allocation](resource_allocation.md) diff --git a/Documentation/device/resource_allocation.md b/Documentation/device/resource_allocation.md new file mode 100644 index 0000000..e82b1c1 --- /dev/null +++ b/Documentation/device/resource_allocation.md @@ -0,0 +1,88 @@ +# Resource allocation in coreboot + +## Introduction + +Resource allocator in coreboot is responsible for assigning parts of the address space to devices. It handles two types of resource requests from devices viz. IO (IORESOURCE_IO) and MMIO (IORESOURCE_MEM). It is typically used for PCI devices, but it also keeps track of other assignments to ensure that there are no conflicts + +## Principles followed by the resource allocator + +Resource allocator follows these basic principles: + +* Allocate address space for every device resource as long as its requirement can be satisfied. +* Don’t overlap with resources in fixed locations. +* Don’t overlap with other resource allocations and follow the rules of bridges i.e. downstream devices of bridges should use parts of the address space allocated to the bridge. + +## Pre-allocation and post-allocation requirements + +The main function that is responsible for allocating resources is `allocate_resources()` and gets called in the `BS_DEV_RESOURCES` boot state. The resource allocator depends upon the device and platform drivers to perform pre-allocation and post-allocation operations. Pre-allocation step requires that the device and platform drivers provide a complete map of fixed resources (resources not changed by the allocator) owned by the device/platform and a list of resource requests that need to be satisfied by the allocator. This is done as part of the `read_resources()` device operation. This step is critical to ensure that the resource allocator can perform its operation correctly as per the principles outlined above. In the post-allocation step, the device and platform drivers are expected to assign the address space allocated by the allocator to the resources requested by the device. This is done as part of the `set_resources()` device operation. This allows the resource allocator to perform its operation independent of platform and device type. + +## Input and output rules for the resource allocator + +As mentioned above, the entrypoint into the resource allocator is `allocate_resources()`. One of the important goals of the allocator is to perform its operation independent of platform and device type. In order to accomplish this, it is important to clearly define what goes into the allocator and what comes out of it. This determines the expected behavior from the device and platform drivers. + +The allocator processes all devices in each domain sub-tree and performs allocation for resources of the following types: +* IORESOURCE_IO +* IORESOURCE_MEM + +On the other hand, it does not change resources marked with IORESOURCE_FIXED flag. These are referred to as “fixed resources”. Resources that have the IORESOURCE_BRIDGE flag set are referred to as “bridge resources”. + + +### Input Rules + +1. IORESOURCE_IO and IORESOURCE_MEM are mutually exclusive. Both the flags must never be set for the same resource. +1. Resources that should not be changed by the allocator must be marked with IORESOURCE_FIXED flag. These resources must be pre-assigned a valid `base` address. It is used by the allocator to ensure there are no conflicts during the allocation step. +1. A fixed resource must not overlap with any other fixed resource within the same address space (IO / MEM), unless either of them is a bridge resource. +1. A fixed bridge resource must not overlap with any other fixed resource within the same address space and on the same bus (i.e. same device or its siblings), unless exactly one of them has IORESOURCE_SUBTRACTIVE set. + +### Output Rules + +1. All device attributes (members of `struct device` structure) beside non-fixed resources are left unaltered. +1. The structure of resource lists (`next` pointers) is left unaltered. +1. The `index` and `gran` attributes of all resources are left unaltered. +1. The `size`, `limit` and `align` attributes of all non-bridge resources are left unaltered. +1. All non-fixed assigned resources downstream of a bridge are covered by an assigned bridge resource of that bridge. +1. IORESOURCE_ASSIGNED flag is set for a non-fixed resource only if it is assigned address space by the allocator. If allocation for a non-fixed resource fails for any reason, all the attributes of that resource are left untouched including resource flags. It is the responsibility of the device and platform driver to check the IORESOURCE_ASSIGNED flag before using the values stored in the `base` field of the resource. + +## Resource allocator implementations + +Currently, there are two flavors of resource allocators implemented in coreboot - v3 and v4. + +### Resource Allocator v3 + +This is the older resource allocator which is used only on the following platforms: + +* northbridge/amd/pi/00630F01 +* northbridge/amd/pi/00730F01 +* northbridge/amd/pi/00660F01 +* northbridge/amd/agesa/family14 +* northbridge/amd/agesa/family15tn +* northbridge/amd/agesa/family16kb + +Resource allocator v3 is still retained and used for the above platforms because these platforms do not conform to the requirements of the allocator i.e. not all the fixed resources of the platform are provided during the `read_resources()` operation. This results in the resource allocator not getting a complete view of the address space. These platforms still work okay with the older resource allocator because of the way it performs allocation in a single window of the address space. No platform other than the ones listed above must use resource allocator v3 as it will be deprecated once the above platforms are fixed. It can be enabled by selecting the `RESOURCE_ALLOCATOR_V3` Kconfig option. + +#### Highlights + +* Contains two phases - resource computation phase and resource allocation phase. +* Finds a single window for resource allocation towards the top of addressable memory under 4G boundary. + +#### Limitations + +* Finds a single window for resource allocation towards the top of addressable memory under 4G boundary. +* Does not support allocation above 4G boundary. Thus, it might not be able to allocate resources for devices that request large allocations (e.g. USB4, discrete graphics, etc.). + + +### Resource Allocator v4 + +This is the latest resource allocator that uses multiple ranges for allocating resources. Unlike resource allocator v3, it does not use the topmost available window for allocation. Instead, it uses the first available window within the address space that is available and satisfies the resource request. This allows utilization of the entire available address space and also allows allocation above the 4G boundary. + +#### Highlights + +* Contains two phases - resource computation phase and resource allocation phase. +* In phase 1, the allocator walks in a DFS fashion gathering the requirements from leaf devices and propagates them back up to their upstream bridges until the requirements for all the downstream devices of the domain are gathered. +* Every domain is considered to have a fixed set of resources. These ranges cannot be relaxed based on the requirements of the downstream devices. They represent the available windows from which resources can be allocated to the different devices under the domain. +* In the second phase, the allocator walks down the tree allocating resources to downstream devices as per the resource requirements gathered in the first phase. +* In order to accomplish best fit for the resources, a list of ranges is maintained by each resource type (IO and MEM). +* Domain does not distinguish between mem and prefmem resources. Thus, the resource allocation at domain level considers mem and prefmem together when finding the best fit based on the biggest resource requirement. +* Allocation at bridge level works the same as at the domain level. One major difference at the bridge level is that it considers prefmem resources separately from mem resources. +* Device and platform drivers can request the allocator to perform allocation for a particular resource above 4G boundary by using the flag `IORESOURCE_ABOVE_4G`. + diff --git a/Documentation/index.md b/Documentation/index.md index a7c4869..ec26b4e 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -188,3 +188,4 @@ * [Utilities](util.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) +* [Device Management](device/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/43603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I887284b44df2bf871f45c3a93fbef9cfc37e42a0 Gerrit-Change-Number: 43603 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: [WIP] util/inteltool: add opt to override cores number
by Maxim Polyakov (Code Review) 17 Aug '21

17 Aug '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35919 ) Change subject: [WIP] util/inteltool: add opt to override cores number ...................................................................... [WIP] util/inteltool: add opt to override cores number In some cases, it is necessary to increase (if the server contains several processors) or decrease (dump should be more compact) the number of CPU cores for dump MSRs. Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 3 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35919/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index f100851..9ae46c9 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -219,7 +219,7 @@ return error; } -int print_intel_core_msrs(void) +int print_intel_core_msrs(unsigned int cores_num) { unsigned int i, core, id; msr_t msr; @@ -2256,8 +2256,10 @@ close(fd_msr); - unsigned int max_core_limit = cpu->max_core_limit ? 8 : cpu->max_core_limit; - for (core = 0; core < max_core_limit; core++) { + if (!cores_num) + cores_num = cpu->max_core_limit; + + for (core = 0; core < cores_num; core++) { #ifndef __DARWIN__ char msrfilename[64]; memset(msrfilename, 0, 64); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..bc9af2b 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -476,7 +476,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrpmedPMcaAsfSRx]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -493,6 +493,7 @@ " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" + " -c <num> | --cores <num>: override CPU cores number for MSR dump\n\n" " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" " -a | --all: dump all known (safe) registers\n" @@ -508,6 +509,7 @@ struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev; const char *dump_spd_file = NULL; int opt, option_index = 0; + unsigned int cores = 0; unsigned int id, i; char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown"; @@ -532,6 +534,7 @@ {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, + {"cores", required_argument, 0, 'c'}, {"ambs", 0, 0, 'A'}, {"spi", 0, 0, 's'}, {"spd", 0, 0, 'S'}, @@ -543,7 +546,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMc:aAsfRS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -587,6 +590,9 @@ case 'M': dump_coremsrs = 1; break; + case 'c': + cores = strtoul(optarg, NULL, 0); + break; case 'a': dump_gpios = 1; show_gpio_diffs = 1; @@ -813,7 +819,7 @@ } if (dump_coremsrs) { - print_intel_core_msrs(); + print_intel_core_msrs(cores); printf("\n\n"); } diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..7708d70 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -385,7 +385,7 @@ void unmap_physical(void *virt_addr, size_t len); unsigned int cpuid(unsigned int op); -int print_intel_core_msrs(void); +int print_intel_core_msrs(unsigned int cores_num); int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); -- To view, visit https://review.coreboot.org/c/coreboot/+/35919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Gerrit-Change-Number: 35919 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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