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Change in coreboot[master]: WIP: lib: Add murmur3 algorithm for RAM hash
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43301 ) Change subject: WIP: lib: Add murmur3 algorithm for RAM hash ...................................................................... WIP: lib: Add murmur3 algorithm for RAM hash This is the murmur3 algorithm from https://github.com/PeterScott/murmur3. I'm not sure we can even include this since it's public domain. We might need to use another hash algorithm. I picked it because it's supposed to be fast. I didn't cleanup the code at all. This is why -Wno-implicit-fallthrough was added to the CFLAGS. BUG=b:159081993 TEST=Suspend trembyle and see hashes being generated. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9dfd371c67966bf7a342fdb5562445e63afce664 --- M Makefile.inc A src/include/murmur3.h M src/lib/Kconfig M src/lib/Makefile.inc A src/lib/murmur3.c A src/lib/ram_hash_murmur.c 6 files changed, 362 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/43301/1 diff --git a/Makefile.inc b/Makefile.inc index 89bb3e4..9b39b39 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -421,7 +421,7 @@ CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -Wno-implicit-fallthrough ifeq ($(CONFIG_COMPILER_GCC),y) # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) diff --git a/src/include/murmur3.h b/src/include/murmur3.h new file mode 100644 index 0000000..138f87f --- /dev/null +++ b/src/include/murmur3.h @@ -0,0 +1,29 @@ +//----------------------------------------------------------------------------- +// MurmurHash3 was written by Austin Appleby, and is placed in the +// public domain. The author hereby disclaims copyright to this source +// code. + +#ifndef _MURMURHASH3_H_ +#define _MURMURHASH3_H_ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_32 (const void *key, int len, uint32_t seed, uint32_t *out); + +void MurmurHash3_x86_128(const void *key, int len, uint32_t seed, void *out); + +void MurmurHash3_x64_128(const void *key, int len, uint32_t seed, void *out); + +//----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // _MURMURHASH3_H_ diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 8eeceec..0e4fa88 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -111,6 +111,8 @@ depends on ENABLE_RAM_HASH help The hash algorithm to use for RAM hash. -# TODO: Add algorithms + +config RAM_HASH_ALGO_MURMUR3 + bool "murmur3" endchoice diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 05df3c6..54b23e2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -148,6 +148,9 @@ ramstage-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c smm-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c +ramstage-$(CONFIG_RAM_HASH_ALGO_MURMUR3) += ram_hash_murmur.c murmur3.c +smm-$(CONFIG_RAM_HASH_ALGO_MURMUR3) += ram_hash_murmur.c murmur3.c + postcar-$(CONFIG_VENDOR_EMULATION) += ramdetect.c postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/murmur3.c b/src/lib/murmur3.c new file mode 100644 index 0000000..f2b6b18 --- /dev/null +++ b/src/lib/murmur3.c @@ -0,0 +1,314 @@ +//----------------------------------------------------------------------------- +// MurmurHash3 was written by Austin Appleby, and is placed in the public +// domain. The author hereby disclaims copyright to this source code. + +// Note - The x86 and x64 versions do _not_ produce the same results, as the +// algorithms are optimized for their respective platforms. You can still +// compile and run any of them on any platform, but your performance with the +// non-native version will be less than optimal. + +#include "murmur3.h" + +//----------------------------------------------------------------------------- +// Platform-specific functions and macros + +#ifdef __GNUC__ +#define FORCE_INLINE __attribute__((always_inline)) inline +#else +#define FORCE_INLINE inline +#endif + +static FORCE_INLINE uint32_t rotl32 ( uint32_t x, int8_t r ) +{ + return (x << r) | (x >> (32 - r)); +} + +static FORCE_INLINE uint64_t rotl64 ( uint64_t x, int8_t r ) +{ + return (x << r) | (x >> (64 - r)); +} + +#define ROTL32(x,y) rotl32(x,y) +#define ROTL64(x,y) rotl64(x,y) + +#define BIG_CONSTANT(x) (x##LLU) + +//----------------------------------------------------------------------------- +// Block read - if your platform needs to do endian-swapping or can only +// handle aligned reads, do the conversion here + +#define getblock(p, i) (p[i]) + +//----------------------------------------------------------------------------- +// Finalization mix - force all bits of a hash block to avalanche + +static FORCE_INLINE uint32_t fmix32 ( uint32_t h ) +{ + h ^= h >> 16; + h *= 0x85ebca6b; + h ^= h >> 13; + h *= 0xc2b2ae35; + h ^= h >> 16; + + return h; +} + +//---------- + +static FORCE_INLINE uint64_t fmix64 ( uint64_t k ) +{ + k ^= k >> 33; + k *= BIG_CONSTANT(0xff51afd7ed558ccd); + k ^= k >> 33; + k *= BIG_CONSTANT(0xc4ceb9fe1a85ec53); + k ^= k >> 33; + + return k; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_32 ( const void * key, int len, + uint32_t seed, uint32_t * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 4; + int i; + + uint32_t h1 = seed; + + uint32_t c1 = 0xcc9e2d51; + uint32_t c2 = 0x1b873593; + + //---------- + // body + + const uint32_t * blocks = (const uint32_t *)(data + nblocks*4); + + for(i = -nblocks; i; i++) + { + uint32_t k1 = getblock(blocks,i); + + k1 *= c1; + k1 = ROTL32(k1,15); + k1 *= c2; + + h1 ^= k1; + h1 = ROTL32(h1,13); + h1 = h1*5+0xe6546b64; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*4); + + uint32_t k1 = 0; + + switch(len & 3) + { + case 3: k1 ^= tail[2] << 16; + case 2: k1 ^= tail[1] << 8; + case 1: k1 ^= tail[0]; + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; + + h1 = fmix32(h1); + + *(uint32_t*)out = h1; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_128 ( const void * key, const int len, + uint32_t seed, void * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 16; + int i; + + uint32_t h1 = seed; + uint32_t h2 = seed; + uint32_t h3 = seed; + uint32_t h4 = seed; + + uint32_t c1 = 0x239b961b; + uint32_t c2 = 0xab0e9789; + uint32_t c3 = 0x38b34ae5; + uint32_t c4 = 0xa1e38b93; + + //---------- + // body + + const uint32_t * blocks = (const uint32_t *)(data + nblocks*16); + + for(i = -nblocks; i; i++) + { + uint32_t k1 = getblock(blocks,i*4+0); + uint32_t k2 = getblock(blocks,i*4+1); + uint32_t k3 = getblock(blocks,i*4+2); + uint32_t k4 = getblock(blocks,i*4+3); + + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + + h1 = ROTL32(h1,19); h1 += h2; h1 = h1*5+0x561ccd1b; + + k2 *= c2; k2 = ROTL32(k2,16); k2 *= c3; h2 ^= k2; + + h2 = ROTL32(h2,17); h2 += h3; h2 = h2*5+0x0bcaa747; + + k3 *= c3; k3 = ROTL32(k3,17); k3 *= c4; h3 ^= k3; + + h3 = ROTL32(h3,15); h3 += h4; h3 = h3*5+0x96cd1c35; + + k4 *= c4; k4 = ROTL32(k4,18); k4 *= c1; h4 ^= k4; + + h4 = ROTL32(h4,13); h4 += h1; h4 = h4*5+0x32ac3b17; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*16); + + uint32_t k1 = 0; + uint32_t k2 = 0; + uint32_t k3 = 0; + uint32_t k4 = 0; + + switch(len & 15) + { + case 15: k4 ^= tail[14] << 16; + case 14: k4 ^= tail[13] << 8; + case 13: k4 ^= tail[12] << 0; + k4 *= c4; k4 = ROTL32(k4,18); k4 *= c1; h4 ^= k4; + + case 12: k3 ^= tail[11] << 24; + case 11: k3 ^= tail[10] << 16; + case 10: k3 ^= tail[ 9] << 8; + case 9: k3 ^= tail[ 8] << 0; + k3 *= c3; k3 = ROTL32(k3,17); k3 *= c4; h3 ^= k3; + + case 8: k2 ^= tail[ 7] << 24; + case 7: k2 ^= tail[ 6] << 16; + case 6: k2 ^= tail[ 5] << 8; + case 5: k2 ^= tail[ 4] << 0; + k2 *= c2; k2 = ROTL32(k2,16); k2 *= c3; h2 ^= k2; + + case 4: k1 ^= tail[ 3] << 24; + case 3: k1 ^= tail[ 2] << 16; + case 2: k1 ^= tail[ 1] << 8; + case 1: k1 ^= tail[ 0] << 0; + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; h2 ^= len; h3 ^= len; h4 ^= len; + + h1 += h2; h1 += h3; h1 += h4; + h2 += h1; h3 += h1; h4 += h1; + + h1 = fmix32(h1); + h2 = fmix32(h2); + h3 = fmix32(h3); + h4 = fmix32(h4); + + h1 += h2; h1 += h3; h1 += h4; + h2 += h1; h3 += h1; h4 += h1; + + ((uint32_t*)out)[0] = h1; + ((uint32_t*)out)[1] = h2; + ((uint32_t*)out)[2] = h3; + ((uint32_t*)out)[3] = h4; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x64_128 ( const void * key, const int len, + const uint32_t seed, void * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 16; + int i; + + uint64_t h1 = seed; + uint64_t h2 = seed; + + uint64_t c1 = BIG_CONSTANT(0x87c37b91114253d5); + uint64_t c2 = BIG_CONSTANT(0x4cf5ad432745937f); + + //---------- + // body + + const uint64_t * blocks = (const uint64_t *)(data); + + for(i = 0; i < nblocks; i++) + { + uint64_t k1 = getblock(blocks,i*2+0); + uint64_t k2 = getblock(blocks,i*2+1); + + k1 *= c1; k1 = ROTL64(k1,31); k1 *= c2; h1 ^= k1; + + h1 = ROTL64(h1,27); h1 += h2; h1 = h1*5+0x52dce729; + + k2 *= c2; k2 = ROTL64(k2,33); k2 *= c1; h2 ^= k2; + + h2 = ROTL64(h2,31); h2 += h1; h2 = h2*5+0x38495ab5; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*16); + + uint64_t k1 = 0; + uint64_t k2 = 0; + + switch(len & 15) + { + case 15: k2 ^= (uint64_t)(tail[14]) << 48; + case 14: k2 ^= (uint64_t)(tail[13]) << 40; + case 13: k2 ^= (uint64_t)(tail[12]) << 32; + case 12: k2 ^= (uint64_t)(tail[11]) << 24; + case 11: k2 ^= (uint64_t)(tail[10]) << 16; + case 10: k2 ^= (uint64_t)(tail[ 9]) << 8; + case 9: k2 ^= (uint64_t)(tail[ 8]) << 0; + k2 *= c2; k2 = ROTL64(k2,33); k2 *= c1; h2 ^= k2; + + case 8: k1 ^= (uint64_t)(tail[ 7]) << 56; + case 7: k1 ^= (uint64_t)(tail[ 6]) << 48; + case 6: k1 ^= (uint64_t)(tail[ 5]) << 40; + case 5: k1 ^= (uint64_t)(tail[ 4]) << 32; + case 4: k1 ^= (uint64_t)(tail[ 3]) << 24; + case 3: k1 ^= (uint64_t)(tail[ 2]) << 16; + case 2: k1 ^= (uint64_t)(tail[ 1]) << 8; + case 1: k1 ^= (uint64_t)(tail[ 0]) << 0; + k1 *= c1; k1 = ROTL64(k1,31); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; h2 ^= len; + + h1 += h2; + h2 += h1; + + h1 = fmix64(h1); + h2 = fmix64(h2); + + h1 += h2; + h2 += h1; + + ((uint64_t*)out)[0] = h1; + ((uint64_t*)out)[1] = h2; +} + +//----------------------------------------------------------------------------- diff --git a/src/lib/ram_hash_murmur.c b/src/lib/ram_hash_murmur.c new file mode 100644 index 0000000..4f6ac9b --- /dev/null +++ b/src/lib/ram_hash_murmur.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <murmur3.h> +#include <ram_hash.h> + +uint32_t generate_hash(const void *buffer, unsigned int size) +{ + uint32_t hash; + MurmurHash3_x86_32(buffer, size, 0xDEADBEEF, &hash); + return hash; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfd371c67966bf7a342fdb5562445e63afce664 Gerrit-Change-Number: 43301 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add support for RAM hash
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43302 ) Change subject: soc/amd/picasso: Add support for RAM hash ...................................................................... soc/amd/picasso: Add support for RAM hash This CL allocates a region in EARLY_DRAM to store the RAM hashes. It also introduces a hard coded memory map based on the current e820 map. In the future we could maybe automate the generate of the hash_ranges. Until now we will need to keep it updated. To enable, add the following to your .config: CONFIG_ENABLE_RAM_HASH=y Hashing RAM from the SMM handler is pretty slow compared to trying it in bootblock. Not sure if the OS has reset the MTRRs. Example of entering S3: coreboot-4.12-1163-gd9cc83a4ce58-dirty Tue Jul 7 21:34:13 UTC 2020 smm starting (log level: 8)... SMI# #0 SMI#: SLP = 0x0c01 hash_ram: Start for_each_range: Processing range 0x1000 -> 0xa0000 Processed block 128: crc: 0x7f00c996. Remaining: 0 MiB Processed block 256: crc: 0x7f00c996. Remaining: 0 MiB Processed block 384: crc: 0x7f00c996. Remaining: 0 MiB Processed block 512: crc: 0x7f00c996. Remaining: 0 MiB for_each_range: Processing range 0x100000 -> 0x2000000 for_each_range: Processing range 0x22cd000 -> 0xcc50c000 Processed block 128: crc: 0x9a22c19c. Remaining: 3107 MiB Processed block 256: crc: 0x9a22c19c. Remaining: 2979 MiB Processed block 384: crc: 0x9a22c19c. Remaining: 2851 MiB ... Example of exiting S3: Timestamp - ACPI wake jump: 36887335255 verify_ram: Start for_each_range: Processing range 0x1000 -> 0xa0000 Processed block 128: crc: 0x7f00c996. Remaining: 0 MiB Processed block 256: crc: 0x7f00c996. Remaining: 0 MiB Processed block 384: crc: 0x7f00c996. Remaining: 0 MiB Processed block 512: crc: 0x7f00c996. Remaining: 0 MiB for_each_range: Processing range 0x100000 -> 0x2000000 for_each_range: Processing range 0x22cd000 -> 0xcc50c000 Processed block 128: crc: 0x9a22c19c. Remaining: 3107 MiB Processed block 256: crc: 0x9a22c19c. Remaining: 2979 MiB Processed block 384: crc: 0x9a22c19c. Remaining: 2851 MiB Processed block 512: crc: 0x9a22c19c. Remaining: 2723 MiB Processed block 640: crc: 0x9a22c19c. Remaining: 2595 MiB Processed block 768: crc: 0x9a22c19c. Remaining: 2467 MiB Processed block 896: crc: 0x9a22c19c. Remaining: 2339 MiB Processed block 1024: crc: 0x9a22c19c. Remaining: 2211 MiB Processed block 1152: crc: 0x9a22c19c. Remaining: 2083 MiB Processed block 1280: crc: 0x9a22c19c. Remaining: 1955 MiB Processed block 1408: crc: 0x9a22c19c. Remaining: 1827 MiB Processed block 1536: crc: 0x9a22c19c. Remaining: 1699 MiB Processed block 1664: crc: 0x9a22c19c. Remaining: 1571 MiB Processed block 1792: crc: 0x9a22c19c. Remaining: 1443 MiB Processed block 1920: crc: 0x9a22c19c. Remaining: 1315 MiB Processed block 2048: crc: 0x9a22c19c. Remaining: 1187 MiB Processed block 2176: crc: 0x9a22c19c. Remaining: 1059 MiB Processed block 2304: crc: 0x9a22c19c. Remaining: 931 MiB Processed block 2432: crc: 0x9a22c19c. Remaining: 803 MiB Processed block 2560: crc: 0x9a22c19c. Remaining: 675 MiB Processed block 2688: crc: 0x9a22c19c. Remaining: 547 MiB Processed block 2816: crc: 0x9a22c19c. Remaining: 419 MiB Processed block 2944: crc: 0x9a22c19c. Remaining: 291 MiB Processed block 3072: crc: 0x9a22c19c. Remaining: 163 MiB Processed block 3200: crc: 0x9a22c19c. Remaining: 35 MiB verify_ram: Done BUG=b:159081993 TEST=S3 suspend and resume on trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia9b80044dd794ddfb0b661d517367259917cd944 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/ram_hash.c M src/soc/amd/picasso/smihandler.c 5 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/43302/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fd2a205..2e7ce89 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -57,6 +57,7 @@ select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS + select HAS_RAM_HASH config MEMLAYOUT_LD_FILE string @@ -174,6 +175,20 @@ Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. +config RAM_HASH_ADDR + hex + depends on ENABLE_RAM_HASH + default 0x21CD000 + help + Where in memory to store the hashes. + +config RAM_HASH_SIZE + hex + depends on ENABLE_RAM_HASH + default 0x100000 + help + Size of the RAM_HASH buffer. + config RAMBASE hex default 0x10000000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..679ee98 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -89,6 +89,9 @@ smm-y += smu.c smm-y += config.c +ramstage-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c +smm-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c + CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 6f43ba1..bb15263 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -89,6 +89,10 @@ VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif +#if CONFIG(ENABLE_RAM_HASH) + REGION(hash_buffer, 0x21CD000, 1M, 4) +#endif + EARLY_RESERVED_DRAM_END(.) RAMSTAGE(CONFIG_RAMBASE, 8M) diff --git a/src/soc/amd/picasso/ram_hash.c b/src/soc/amd/picasso/ram_hash.c new file mode 100644 index 0000000..c7f0be4 --- /dev/null +++ b/src/soc/amd/picasso/ram_hash.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <ram_hash.h> +#include <commonlib/bsd/helpers.h> + +struct hash_range mem_layout[] = { + { + .start = 0x1000, + .end = 0xa0000, + .block_size = 1 * KiB, + .diff = 1 + }, + { + .start = 0x100000, + .end = 0x2000000, + .block_size = 1 * MiB, + .diff = 0 + }, + { + .start = 0x22cd000, + .end = 0xcc50c000, + .block_size = 1 * MiB, + .diff = 0 + }, +}; + +void soc_hash_ram(void) +{ + hash_ram(mem_layout, ARRAY_SIZE(mem_layout)); +} +void soc_verify_ram(void) +{ + verify_ram(mem_layout, ARRAY_SIZE(mem_layout)); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 7e762a9..6832526 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <ram_hash.h> #include <cpu/x86/cache.h> #include <cpu/amd/amd64_save_state.h> #include <acpi/acpi.h> @@ -144,6 +145,13 @@ printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); slp_typ = acpi_sleep_from_pm1(pm1cnt); + /* + * Hash RAM as soon as we know we are entering S3 to catch any problems + * caused by the SMM handler, PSP, or SMU. + */ + if (slp_typ == ACPI_S3) + soc_hash_ram(); + /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -- To view, visit https://review.coreboot.org/c/coreboot/+/43302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9b80044dd794ddfb0b661d517367259917cd944 Gerrit-Change-Number: 43302 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: mb/gigabyte: add GA-P67A-UD3R
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31363 Change subject: mb/gigabyte: add GA-P67A-UD3R ...................................................................... mb/gigabyte: add GA-P67A-UD3R This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support. This board has redundant 4MB SOIC-8 flash chips, and flashrom is usable with the vendor BIOS. This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected. The function of PCIe ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports. Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) - Booting Linux (SeaBIOS) - Native RAM init - PCIe graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port Not tested: - SATA 2 - PS/2 keyboard/mouse - Digital audio Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye <jye836(a)gmail.com> --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c A src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c 16 files changed, 781 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/1 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig new file mode 100644 index 0000000..c1efe12 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig @@ -0,0 +1,40 @@ +if BOARD_GIGABYTE_GA_P67A_UD3R + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "gigabyte/ga-p67a-ud3r" + +config MAINBOARD_PART_NUMBER + string + default "GA-P67A-UD3R" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x5001 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_GIGABYTE_GA_P67A_UD3R diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name new file mode 100644 index 0000000..15f0655 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_P67A_UD3R + bool "GA-P67A-UD3R" diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl new file mode 100644 index 0000000..34de86f --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl new file mode 100644 index 0000000..2b20c77 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c new file mode 100644 index 0000000..a2f383b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt new file mode 100644 index 0000000..c6f16ae --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-P67A-UD3R-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default new file mode 100644 index 0000000..60de212 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout new file mode 100644 index 0000000..4e5c0a8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +#400 1 e 0 unused +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +#432 3 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb new file mode 100644 index 0000000..4ed458d --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 James Ye <jye836(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + device lapic 0x0 on end + + # Magic APIC ID to locate this chip + device lapic 0xacac off end + + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + end + end + + device domain 0x0 on + subsystemid 0x1458 0x5001 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on # PCIe bridge (PCIEX16) + subsystemid 0x1458 0x5000 + end + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x000c0801" + register "gen2_dec" = "0x000c0291" + + register "pcie_port_coalesce" = "0" + register "c2_latency" = "0x0065" + register "p_cnt_throttling_supported" = "1" + + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio controller + subsystemid 0x1458 0xa102 + end + device pci 1c.0 on end # Unrouted, to disable coalescing + device pci 1c.1 on # PCIe Port #2 + device pci 00.0 on # USB 3.0 controller + subsystemid 0x1458 0x5007 + end + end + device pci 1c.2 on # PCIe Port #3 + device pci 00.0 on # Ethernet controller + subsystemid 0x1458 0xe000 + end + end + device pci 1c.3 on # PCIe Port #4 + device pci 00.0 on # PCI bridge + subsystemid 0x1458 0x5000 + end + end + device pci 1c.4 on end # PCIe Port #5 (PCIEX4) + device pci 1c.5 off end # PCIe Port #6 (PCIEX1_1) + device pci 1c.6 off end # PCIe Port #7 (PCIEX1_2) + device pci 1c.7 off end # PCIe Port #8 (PCIEX1_3) + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy, not routed + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2, not routed + device pnp 2e.3 off end # Parallel port, not rounted + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0290 + io 0x62 = 0x0 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR, not routed + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl new file mode 100644 index 0000000..365a0fa --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // Chipset specific sleep states + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c new file mode 100644 index 0000000..c65f432 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c new file mode 100644 index 0000000..a843a2b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1458a022, /* Subsystem ID */ + + 15, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a022), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x593301f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x014b6130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c new file mode 100644 index 0000000..3037b73 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SUPERIO_BASE 0x2e +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | + CNF2_LPC_EN | COMA_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 6, 2 }, + { 1, 6, 2 }, + { 1, 6, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, + { 1, 5, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO WDT which kicks in DualBIOS */ + ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Gerrit-Change-Number: 31363 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 22

Change in ...coreboot[master]: nb/intel/sandybridge: Introduce soc/iomap.h
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32075 Change subject: nb/intel/sandybridge: Introduce soc/iomap.h ...................................................................... nb/intel/sandybridge: Introduce soc/iomap.h Defines the memory ranges used by the northbridge in a separate header. Include the new header and rename the defines to match the one found in soc/intel/common. Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/early_init.c A src/northbridge/intel/sandybridge/include/soc/iomap.h M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 8 files changed, 92 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32075/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 54a4057..c3d9079 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +CFLAGS_common += -Isrc/northbridge/intel/sandybridge/include + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += pcie.c diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb546..af2f37b 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -92,7 +92,8 @@ unsigned long tmp; tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd(current, 0, 0, + GFXVT_BASE_ADDRESS); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -107,8 +108,8 @@ } const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, + VTVC0_BASE_ADDRESS); current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 5307a2c..2e0f087 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -35,20 +35,20 @@ return; /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + MCHBAR32(0x5404) = GFXVT_BASE_ADDRESS >> 32; + MCHBAR32(0x5400) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(0x5414) = VTVC0_BASE_ADDRESS >> 32; + MCHBAR32(0x5410) = VTVC0_BASE_ADDRESS | 1; /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + write32((void *)(GFXVT_BASE_ADDRESS + 0xff0), 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x20000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0xa0000000); } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x80000000); } } @@ -67,12 +67,12 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, EP_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, MCH_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, DMI_BASE_ADDRESS >> 32); printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/include/soc/iomap.h b/src/northbridge/intel/sandybridge/include/soc/iomap.h new file mode 100644 index 0000000..75fd9d9 --- /dev/null +++ b/src/northbridge/intel/sandybridge/include/soc/iomap.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SANDYBRIDGE_IOMAP_H_ +#define _SOC_SANDYBRIDGE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +/* Intel Enhanced Debug region must be 4MB */ + +#define IED_SIZE CONFIG_IED_REGION_SIZE + +#define ILB_BASE_ADDRESS 0xfed08000ULL +#define ILB_BASE_SIZE 0x400 + +#define DMI_BASE_ADDRESS 0xfed18000ULL +#define DMI_BASE_SIZE 0x1000 + +#define MCH_BASE_ADDRESS 0xfed10000ULL +#define MCH_BASE_SIZE 0x4000 + +#define EP_BASE_ADDRESS 0xfed19000ULL +#define EP_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + +#define TPM_BASE_ADDRESS 0xfed40000ULL +#define TPM_BASE_SIZE 0x5000 + + +#endif diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..71dea62 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -112,8 +112,8 @@ /* Reserve IOMMU BARs */ const u32 capid0_a = pci_read_config32(dev, 0xe4); if (!(capid0_a & (1 << 23))) { - mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); - mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, 4); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, 4); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 55df03b..72ae5b0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -41,23 +41,23 @@ * Channel X = [0, 1] * Command queue index Y = [0, 1, 2, 3] * - * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register + * MCH_BASE_ADDRESS + 0x4220 + 0x400 * X + 4 * Y: command io register * Controls the DRAM command signals * Bit 0: !RAS * Bit 1: !CAS * Bit 2: !WE * - * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register + * MCH_BASE_ADDRESS + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register * Controls the address, bank address and slotrank signals * Bit 0-15 : Address * Bit 20-22: Bank Address * Bit 24-25: slotrank * - * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register + * MCH_BASE_ADDRESS + 0x4230 + 0x400 * X + 4 * Y: idle register * Controls the idle time after issuing this DRAM command * Bit 16-32: number of clock-cylces to idle * - * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue + * MCH_BASE_ADDRESS + 0x4284 + 0x400 * channel: execute command queue * Starts to execute all queued commands * Bit 0 : start DRAM command execution * Bit 18-19 : number of queued commands - 1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index c544a74..2382084 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -277,10 +277,10 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->mchbar = MCH_BASE_ADDRESS; + pei_data->dmibar = DMI_BASE_ADDRESS; + pei_data->epbar = EP_BASE_ADDRESS; + pei_data->pciexbar = MCFG_BASE_ADDRESS; pei_data->smbusbar = SMBUS_IO_BASE; pei_data->wdbbar = 0x4000000; pei_data->wdbsize = 0x1000; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d7de843..dc9f889 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -17,6 +17,8 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ +#include <northbridge/intel/sandybridge/include/soc/iomap.h> + /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 #define BASE_REV_IVB 0x50 @@ -34,24 +36,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#define IOMMU_BASE1 0xfed90000ULL -#define IOMMU_BASE2 0xfed91000ULL - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> @@ -118,9 +102,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) #define MCHBAR32_AND_OR(x, and, or) \ @@ -133,9 +117,9 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR16(x) (*((volatile u16 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR32(x) (*((volatile u32 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -164,9 +148,9 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Gerrit-Change-Number: 32075 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: console,boot_state: Denote unit in beginning in log message
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38136 ) Change subject: console,boot_state: Denote unit in beginning in log message ...................................................................... console,boot_state: Denote unit in beginning in log message Looking at the board status repository logs, lines similar to BS: postcar times (exec / console): total (unknown) / 0 ms BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms are not obvious right away, as the unit visually only applies to the value after the slash. So, add the unit after `times`. BS: BS_DEV_ENUMERATE run times [ms] (exec / console): 6 / 0 Change-Id: If01a5d43a54aeefc0a6d49d4b600436c2a8328cd Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/console/printk.c M src/lib/hardwaremain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38136/1 diff --git a/src/console/printk.c b/src/console/printk.c index 3ef28f3..be7c98b 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -49,7 +49,7 @@ if (!TRACK_CONSOLE_TIME) return; - printk(BIOS_DEBUG, "BS: " ENV_STRING " times (exec / console): total (unknown) / %ld ms\n", + printk(BIOS_DEBUG, "BS: " ENV_STRING " times [ms] (exec / console): total (unknown) / %ld\n", DIV_ROUND_CLOSEST(console_usecs, USECS_PER_MSEC)); } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index eba5f12..cf1e1b7 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -250,7 +250,7 @@ execution = DIV_ROUND_CLOSEST(execution, USECS_PER_MSEC); console = DIV_ROUND_CLOSEST(console, USECS_PER_MSEC); if (execution) { - printk(BIOS_DEBUG, "BS: %s %s times (exec / console): %ld / %ld ms\n", + printk(BIOS_DEBUG, "BS: %s %s times [ms] (exec / console): %ld / %ld\n", state->name, sample_id[i], execution - console, console); /* Reset again to ignore printk() time above. */ console_time_get_and_reset(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If01a5d43a54aeefc0a6d49d4b600436c2a8328cd Gerrit-Change-Number: 38136 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: util/lint/checkpatch: Update to 96 char line length limit
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38677 ) Change subject: util/lint/checkpatch: Update to 96 char line length limit ...................................................................... util/lint/checkpatch: Update to 96 char line length limit Follow up on commit bcbf2deb42 (Documentation/coding_style.md: Update line length limit) and update the script `checkpatch.pl`. Change-Id: I2b5c5d4cf9f0534298d00e76173cd448e8e13281 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/lint/checkpatch.pl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38677/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 1affdb7..c6cbe69 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -51,7 +51,7 @@ my @exclude = (); #coreboot my $help = 0; my $configuration_file = ".checkpatch.conf"; -my $max_line_length = 80; +my $max_line_length = 96; my $ignore_perl_version = 0; my $minimum_perl_version = 5.10.0; my $min_conf_desc_length = 4; -- To view, visit https://review.coreboot.org/c/coreboot/+/38677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5c5d4cf9f0534298d00e76173cd448e8e13281 Gerrit-Change-Number: 38677 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/poppy: Create sylas variant
by Danomi Lin (Code Review) 07 Aug '23

07 Aug '23

Danomi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41648 ) Change subject: mb/google/poppy: Create sylas variant ...................................................................... mb/google/poppy: Create sylas variant Create new variant and build for sylas. BUG=b:155315878 TEST=FW_NAME="sylas" emerge-nami coreboot chromeos-bootimage Change-Id: Ifa43b72d4e1f61a50ab624ad8bd2938c3a1ef809 Signed-off-by: Danomi Lin <lin.danomi(a)inventec.corp-partner.google.com> --- A src/mainboard/google/poppy/variants/sylas/Makefile.inc A src/mainboard/google/poppy/variants/sylas/bard-data.vbt A src/mainboard/google/poppy/variants/sylas/devicetree.cb A src/mainboard/google/poppy/variants/sylas/gpio.c A src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl A src/mainboard/google/poppy/variants/sylas/include/variant/ec.h A src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h A src/mainboard/google/poppy/variants/sylas/include/variant/sku.h A src/mainboard/google/poppy/variants/sylas/mainboard.c A src/mainboard/google/poppy/variants/sylas/memory.c A src/mainboard/google/poppy/variants/sylas/nhlt.c A src/mainboard/google/poppy/variants/sylas/smihandler.c 12 files changed, 1,860 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41648/1 diff --git a/src/mainboard/google/poppy/variants/sylas/Makefile.inc b/src/mainboard/google/poppy/variants/sylas/Makefile.inc new file mode 100644 index 0000000..dc80357 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/Makefile.inc @@ -0,0 +1,45 @@ + +# IMPORTANT!! When a new memory SPD is added here, please ensure that ddp_bitmap +# is correctly updated in memory.c to indicate if memory id is using DDP. +SPD_SOURCES = empty_ddr4 # 0b0000 +SPD_SOURCES += micron_dimm_MT40A256M16GE-083E # 0b0001 +SPD_SOURCES += samsung_dimm_K4A8G165WB-BCRC # 0b0010 +SPD_SOURCES += hynix_dimm_H5AN4G6NBJR-UHC # 0b0011 +SPD_SOURCES += hynix_dimm_H5ANAG6NAMR-UHC # 0b0100 +SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b0101 +SPD_SOURCES += hynix_dimm_H5AN8G6NAFR-UHC # 0b0110 +SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111 +SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000 +SPD_SOURCES += samsung_dimm_K4AAG165WB-MCRC # 0b1001 +SPD_SOURCES += hynix_dimm_H5AN4G6NAFR-UHC # 0b1010 +SPD_SOURCES += micron_dimm_MT40A256M16LY-075F # 0b1011 +SPD_SOURCES += micron_dimm_MT40A512M16TB-062EJ # 0b1100 +SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101 +SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b1110 +SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b1111 + +# Used when PCH_MEM_CONFIG4 = 1 (LPDDR3) +SEC_SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0000 +SEC_SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0001 +SEC_SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0010 +SEC_SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0011 +SEC_SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b0100 +SEC_SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0101 +SEC_SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b0110 + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += nhlt.c +ramstage-y += mainboard.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +# Add OEM ID table +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw + +$(call add_vbt_to_cbfs, vbt-bard.bin, bard-data.vbt) diff --git a/src/mainboard/google/poppy/variants/sylas/bard-data.vbt b/src/mainboard/google/poppy/variants/sylas/bard-data.vbt new file mode 100644 index 0000000..cdaca6a --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/bard-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/sylas/devicetree.cb b/src/mainboard/google/poppy/variants/sylas/devicetree.cb new file mode 100644 index 0000000..8325261 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/devicetree.cb @@ -0,0 +1,493 @@ +chip soc/intel/skylake + + # Deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable S0ix + register "s0ix_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "SaImguEnable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" + + # Intersil VR c-state issue workaround + # send VR mailbox command for IA/GT/SA rails + register "IslVrCmd" = "2" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 11 | 2.4 | 3.1 | 3.1 | + #| DcLoadline | 10 | 2.46 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 1100, + .dc_loadline = 1000, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 246, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Root port 4 (x1) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ1# + # PcieRpClkSrcNumber: Uses 1 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + + # Root port 5 (x4) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ3# + # PcieRpClkSrcNumber: Uses 3 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + + # Root port 9 (x2) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ2# + # PcieRpClkSrcNumber: Uses 2 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader + + # Touchscreen + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + + # Trackpad + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + + # Pen + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + + # Audio + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Touchscreen | + #| I2C1 | Trackpad | + #| I2C2 | Pen | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 90, + .sda_hold = 36, + }, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 90, + .sda_hold = 36, + }, + .early_init = 1, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 195, + .scl_hcnt = 90, + .sda_hold = 36, + }, + }, + }" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + + register "tcc_offset" = "3" # TCC of 97C + register "psys_pmax" = "101" + + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "enable_delay_ms" = "5" + register "enable_off_delay_ms" = "100" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" + register "stop_off_delay_ms" = "2" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" + register "stop_delay_ms" = "20" + register "stop_off_delay_ms" = "2" + device i2c 39 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "generic.enable_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "wake" = "GPE0_DW2_16" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "generic.wake" = "GPE0_DW2_16" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C #1 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM005C"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "generic.wake" = "GPE0_DW2_01" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_E8)" + register "key.dev_name" = ""INST"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_insert"" + device generic 0 on end + end + end # I2C #2 + device pci 15.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1A on end + end + end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 + device pci 00.0 on end + end + end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)" + register "wake" = "GPE0_DW0_01" # GPP_B1 + device spi 0 on end + end # FPMCU + end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/poppy/variants/sylas/gpio.c b/src/mainboard/google/poppy/variants/sylas/gpio.c new file mode 100644 index 0000000..42f84f5 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/gpio.c @@ -0,0 +1,490 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <variant/sku.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 : RCIN# ==> NC(TP22) */ + PAD_CFG_NC(GPP_A0), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SERIRQ ==> NC(TP24) */ + PAD_CFG_NC(GPP_A6), + /* A7 : PIRQA# ==> NC(TP15) */ + PAD_CFG_NC(GPP_A7), + /* A8 : CLKRUN# ==> NC(TP23) */ + PAD_CFG_NC(GPP_A8), + /* A9 : ESPI_CLK */ + /* A10 : CLKOUT_LPC1 ==> NC */ + PAD_CFG_NC(GPP_A10), + /* A11 : PME# ==> NC(TP46) */ + PAD_CFG_NC(GPP_A11), + /* A12 : BM_BUSY# ==> NC */ + PAD_CFG_NC(GPP_A12), + /* A13 : SUSWARN# ==> SUSWARN#_R */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RESET# */ + /* A15 : SUSACK# ==> SUSACK# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL ==> NC */ + PAD_CFG_NC(GPP_A16), + /* A17 : SD_PWR_EN# ==> NC */ + PAD_CFG_NC(GPP_A17), + /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC (unstuffed) */ + PAD_CFG_NC(GPP_A18), + /* A19 : ISH_GP1 ==> NC */ + PAD_CFG_NC(GPP_A19), + /* A20 : ISH_GP2 ==> NC */ + PAD_CFG_NC(GPP_A20), + /* A21 : ISH_GP3 ==> NC */ + PAD_CFG_NC(GPP_A21), + /* A22 : ISH_GP4 ==> NC */ + PAD_CFG_NC(GPP_A22), + /* A23 : ISH_GP5 ==> PCH_SPK_EN */ + PAD_CFG_GPO(GPP_A23, 1, DEEP), + + /* B0 : CORE_VID0 ==> NC(T3) */ + PAD_CFG_NC(GPP_B0), + /* B1 : CORE_VID1 ==> NC(T4) */ + PAD_CFG_NC(GPP_B1), + /* B2 : VRALERT# ==> NC */ + PAD_CFG_NC(GPP_B2), + /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), + /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B5 : SRCCLKREQ0# ==> NC */ + PAD_CFG_NC(GPP_B5), + /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : SRCCLKREQ2# ==> CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : SRCCLKREQ3# ==> CLKREQ_PCIE#3 */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : SRCCLKREQ4# ==> WLAN_PE_RST_AP */ + PAD_CFG_GPO(GPP_B9, 0, RSMRST), + /* B10 : SRCCLKREQ5# ==> NC */ + PAD_CFG_NC(GPP_B10), + /* B11 : EXT_PWR_GATE# ==> NC */ + PAD_CFG_NC(GPP_B11), + /* B12 : SLP_S0# ==> PM_SLP_R_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST#_PCH */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> EC_GPP_B14 (rsvd for later) */ + PAD_CFG_NC(GPP_B14), + /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS# ==> NC(TP26) */ + PAD_CFG_NC(GPP_B19), + /* B20 : GSPI1_CLK ==> NC(TP27) */ + PAD_CFG_NC(GPP_B20), + /* B21 : GSPI1_MISO ==> NC(TP28) */ + PAD_CFG_NC(GPP_B21), + /* B22 : GSPI1_MOSI ==> NC(TP30) */ + PAD_CFG_NC(GPP_B22), + /* B23 : SM1ALERT# ==> SOC_SML1ALERT# (unstuffed) */ + PAD_CFG_NC(GPP_B23), + + /* C0 : SMBCLK ==> SOC_SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA ==> SOC_SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : SMBALERT# ==> NC(TP917) */ + PAD_CFG_NC(GPP_C2), + /* C4 : SML0DATA ==> NC */ + PAD_CFG_NC(GPP_C4), + /* C5 : SML0ALERT# ==> SOC_SML0ALERT# (unstuffed) */ + PAD_CFG_NC(GPP_C5), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> NC(TP31) */ + PAD_CFG_NC(GPP_C8), + /* C9 : UART0_TXD ==> NC(TP32) */ + PAD_CFG_NC(GPP_C9), + /* C10 : UART0_RTS# ==> EN_PP3300_DX_CAM1 */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM2 */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C12 : UART1_RXD ==> PCH_MEM_CONFIG0 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> PCH_MEM_CONFIG1 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), + /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG2 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG3 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> I2C_0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> I2C_0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> I2C_1_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> I2C_1_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> NC(TP926) */ + PAD_CFG_NC(GPP_C22), + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* D0 : SPI1_CS# ==> DDR_CHB_EN (for debugging) */ + PAD_CFG_NC(GPP_D0), + /* D1 : SPI1_CLK ==> PEN_IRQ# */ + PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + /* D2 : SPI1_MISO ==> PEN_PDCT# */ + PAD_CFG_GPI_APIC(GPP_D2, NONE, PLTRST), + /* D3 : SPI1_MOSI ==> PEN_RST# */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + /* D4 : FASHTRIG ==> NC */ + PAD_CFG_NC(GPP_D4), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_CFG_NC(GPP_D5), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_CFG_NC(GPP_D6), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_CFG_NC(GPP_D7), + /* D8 : ISH_I2C1_SCL ==> NC */ + PAD_CFG_NC(GPP_D8), + /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ + PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), + /* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */ + PAD_CFG_NC(GPP_D11), + /* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */ + PAD_CFG_NC(GPP_D12), + /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX (unstuffed) */ + PAD_CFG_NC(GPP_D13), + /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX (unstuffed) */ + PAD_CFG_NC(GPP_D14), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_D15), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_CFG_NC(GPP_D16), + /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21 : SPI1_IO2 ==> DDR_CHA_EN (debugging) */ + PAD_CFG_NC(GPP_D21), + /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ + PAD_CFG_GPO(GPP_D22, 1, DEEP), + /* D23 : I2S_MCLK ==> I2S_1_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + /* E1 : SATAXPCIE1 ==> EMR_GARAGE_DET# - for wake event */ + PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + /* E2 : SATAXPCIE2 ==> WLAN_OFF# */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E3 : CPU_GP0 ==> TRACKPAD_INT# */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST), + /* E4 : SATA_DEVSLP0 ==> BT_OFF# */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> NC(TP928) */ + PAD_CFG_NC(GPP_E5), + /* E6 : SATA_DEVSLP2 ==> NC(TP915) */ + PAD_CFG_NC(GPP_E6), + /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + /* E8 : SATALED# ==> EMR_GARAGE_DET# - for notification */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E8, NONE, DEEP), + /* E9 : USB2_OCO# ==> USB_C0_OC# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB2_OC1# ==> USB_C1_OC# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : USB2_OC2# ==> USB_A0_OC# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : USB2_OC3# ==> NC */ + PAD_CFG_NC(GPP_E12), + /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + /* E15 : DDPD_HPD2 ==> DDR_SEL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), + /* E17 : EDP_HPD ==> EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* E19 : DDPB_CTRLDATA ==> SOC_DP1_CTRL_DATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + /* E20 : DDPC_CTRLCLK ==> SOC_DP2_CTRL_CLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), + /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/ + PAD_CFG_NC(GPP_E23), + + /* The next 4 pads are for bit banging the amplifiers, default to I2S */ + /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), + /* F1 : I2S2_SFRM ==> I2S2_2_FS_LRC */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), + /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), + /* F3 : I2S2_RXD ==> NC */ + PAD_CFG_NC(GPP_F3), + /* F4 : I2C2_SDA ==> I2C_2_SDA */ + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + /* F5 : I2C2_SCL ==> I2C_2_SCL */ + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + /* F6 : I2C3_SDA ==> I2C_3_SDA */ + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + /* F7 : I2C3_SCL ==> I2C_3_SCL */ + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ + PAD_CFG_NC(GPP_F8), + /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ + PAD_CFG_NC(GPP_F9), + /* F10 : I2C5_SDA ==> NC */ + PAD_CFG_NC(GPP_F10), + /* F11 : I2C5_SCL ==> NC */ + PAD_CFG_NC(GPP_F11), + /* F12 : EMMC_CMD ==> EMMC_1_CMD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA1 ==> EMMC_1_D1 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA2 ==> EMMC_1_D2 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA3 ==> EMMC_1_D3 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA4 ==> EMMC_1_D4 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA5 ==> EMMC_1_D5 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA6 ==> EMMC_1_D6 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_DATA7 ==> EMMC_1_D7 */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_RCLK ==> EMMC_1_RCLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_CLK ==> EMMC_1_CLK */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : RSVD ==> NC */ + PAD_CFG_NC(GPP_F23), + + /* G0 : SD_CMD ==> NC */ + PAD_CFG_NC(GPP_G0), + /* G1 : SD_DATA0 ==> NC */ + PAD_CFG_NC(GPP_G1), + /* G2 : SD_DATA1 ==> NC */ + PAD_CFG_NC(GPP_G2), + /* G3 : SD_DATA2 ==> NC */ + PAD_CFG_NC(GPP_G3), + /* G4 : SD_DATA3 ==> NC */ + PAD_CFG_NC(GPP_G4), + /* G5 : SD_CD# ==> NC */ + PAD_CFG_NC(GPP_G5), + /* G6 : SD_CLK ==> NC */ + PAD_CFG_NC(GPP_G6), + /* G7 : SD_WP ==> SD_WP (not needed) */ + PAD_CFG_NC(GPP_G7), + + /* GPD0: BATLOW# ==> PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R# */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_R_BTN# */ + PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> NC(TP44) */ + PAD_CFG_NC(GPD6), + /* GPD7: RSVD ==> NC */ + PAD_CFG_NC(GPD7), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> NC(TP41) */ + PAD_CFG_NC(GPD9), + /* GPD10: SLP_S5# ==> NC(TP38) */ + PAD_CFG_NC(GPD10), + /* GPD11: LANPHYC ==> NC */ + PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* Ensure UART pins are in native mode for H1. */ + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + + /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct pad_config nami_default_sku_gpio_table[] = { + /* D17 : DMIC_CLK1 ==> SOC_DMIC_CLK1 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), +}; + +static const struct pad_config no_dmic1_sku_gpio_table[] = { + /* D17 : DMIC_CLK1 ==> NC */ + PAD_CFG_NC(GPP_D17), + /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), +}; + +static const struct pad_config pantheon_gpio_table[] = { + /* D17 : DMIC_CLK1 ==> NC */ + PAD_CFG_NC(GPP_D17), + /* C3 : SML0CLK ==> NC */ + PAD_CFG_NC(GPP_C3), +}; + +static const struct pad_config fpmcu_gpio_table[] = { + /* B0 : CORE_VID0 ==> FPMCU_INT_L */ + PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), + /* B1 : CORE_VID1 ==> FPMCU_INT_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), + /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_SPI_FP_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_SPI_FP_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), + /* C9 : UART0_TXD ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C9, 1, DEEP), + /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), + /* D17 : DMIC_CLK1 ==> NC */ + PAD_CFG_NC(GPP_D17), +}; + +const struct pad_config *variant_sku_gpio_table(size_t *num) +{ + uint32_t sku_id = variant_board_sku(); + const struct pad_config *board_gpio_tables; + switch (sku_id) { + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + case SKU_0_SONA: + case SKU_1_SONA: + case SKU_0_SYNDRA: + case SKU_1_SYNDRA: + case SKU_2_SYNDRA: + case SKU_3_SYNDRA: + case SKU_4_SYNDRA: + case SKU_5_SYNDRA: + case SKU_6_SYNDRA: + case SKU_7_SYNDRA: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: + *num = ARRAY_SIZE(no_dmic1_sku_gpio_table); + board_gpio_tables = no_dmic1_sku_gpio_table; + break; + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + *num = ARRAY_SIZE(pantheon_gpio_table); + board_gpio_tables = pantheon_gpio_table; + break; + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + *num = ARRAY_SIZE(fpmcu_gpio_table); + board_gpio_tables = fpmcu_gpio_table; + break; + default: + *num = ARRAY_SIZE(nami_default_sku_gpio_table); + board_gpio_tables = nami_default_sku_gpio_table; + break; + } + return board_gpio_tables; +} diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2b3bd25 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal_Sensor_Remote_CPU" +#define DPTF_TSR0_PASSIVE 75 +#define DPTF_TSR0_CRITICAL 125 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal_Sensor_Remote_PMIC" +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 125 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal_Sensor_Remote_CPU" +#define DPTF_TSR2_PASSIVE 75 +#define DPTF_TSR2_CRITICAL 125 +#define DPTF_TSR2_ACTIVE_AC0 50 +#define DPTF_TSR2_ACTIVE_AC1 47 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) +#endif + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 1, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 1, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 1, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/ec.h b/src/mainboard/google/poppy/variants/sylas/include/variant/ec.h new file mode 100644 index 0000000..a5a0196 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TABLET_EVENT +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h new file mode 100644 index 0000000..98450f6 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 +#define GPIO_MEM_CONFIG_4 GPP_E15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/sku.h b/src/mainboard/google/poppy/variants/sylas/include/variant/sku.h new file mode 100644 index 0000000..d6786dc --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/sku.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_0_NAMI 0x3A7B +#define SKU_0_VAYNE 0x3A67 +#define SKU_1_VAYNE 0x3A63 +#define SKU_2_VAYNE 0x3A7F +#define SKU_0_PANTHEON 0x3F63 +#define SKU_1_PANTHEON 0x3F67 +#define SKU_2_PANTHEON 0x3F62 +#define SKU_3_PANTHEON 0xBF63 +#define SKU_4_PANTHEON 0xBF62 +#define SKU_0_SONA 0x3AE2 +#define SKU_1_SONA 0x3AE3 +#define SKU_0_SYLAS 0x39E2 +#define SKU_1_SYLAS 0x39E3 +#define SKU_0_AKALI 0x29E1 +#define SKU_1_AKALI 0x2861 +#define SKU_0_AKALI360 0x2BE7 +#define SKU_1_AKALI360 0x2A67 +#define SKU_0_SYNDRA 0x2BC63 +#define SKU_1_SYNDRA 0x2BC62 +#define SKU_2_SYNDRA 0x2BC61 +#define SKU_3_SYNDRA 0X2BC60 +#define SKU_4_SYNDRA 0X6BC63 +#define SKU_5_SYNDRA 0X6BC62 +#define SKU_6_SYNDRA 0X6BC61 +#define SKU_7_SYNDRA 0X6BC60 +#define SKU_0_EKKO 0x10118E3 +#define SKU_1_EKKO 0x10018E3 +#define SKU_2_EKKO 0x10118E1 +#define SKU_3_EKKO 0X10018E1 +#define SKU_4_EKKO 0x10118E2 +#define SKU_5_EKKO 0x10018E2 +#define SKU_6_EKKO 0x10118E0 +#define SKU_7_EKKO 0x10018E0 +#define SKU_0_BARD 0x1019CE3 +#define SKU_1_BARD 0x1009CE3 +#define SKU_2_BARD 0x1019CE1 +#define SKU_3_BARD 0X1009CE1 +#define SKU_4_BARD 0X1009CE0 +#define SKU_5_BARD 0X1009CE2 +#define SKU_6_BARD 0x1019CE0 +#define SKU_7_BARD 0x1019CE2 + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/sylas/mainboard.c b/src/mainboard/google/poppy/variants/sylas/mainboard.c new file mode 100644 index 0000000..dde74c7 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/mainboard.c @@ -0,0 +1,310 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <assert.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include <chip.h> +#include <commonlib/cbfs_serialized.h> +#include <compiler.h> +#include <device/device.h> +#include <drivers/intel/gma/opregion.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/mp_init.h> +#include <smbios.h> +#include <soc/ramstage.h> +#include <string.h> +#include <variant/sku.h> + +#define PL2_I7_SKU 44 +#define PL2_DEFAULT 29 +#define PL2_KBL_U 25 + +/* PL2 ID define*/ +#define PL2_ID_DEFAULT 0 +#define PL2_ID_SONA_SYNDRA 1 +#define PL2_ID_BARD_EKKO 2 + +static const struct pl2_config { + uint32_t cpuid_y0_pl2; + uint32_t cpuid_non_y0_pl2; +} pl2_config_table[] = { + [PL2_ID_DEFAULT] = { PL2_I7_SKU, PL2_DEFAULT }, + [PL2_ID_SONA_SYNDRA] = { PL2_DEFAULT, PL2_KBL_U }, + [PL2_ID_BARD_EKKO] = { PL2_DEFAULT, PL2_KBL_U }, +}; + +/* Variant for AKALI */ +#define AKALI_SA_AC_LOADLINE 1100 +#define AKALI_SA_DC_LOADLINE 1028 +#define AKALI_IA_AC_LOADLINE 272 +#define AKALI_IA_DC_LOADLINE 247 +#define AKALI_GT_AC_LOADLINE 314 +#define AKALI_GT_DC_LOADLINE 321 + +/* We only have Akali and Nami default settings so far */ +enum project_sku { + PRJ_AKALI = 1, +}; + +static const struct { + enum project_sku sku; + int ac_loadline[NUM_VR_DOMAINS]; + int dc_loadline[NUM_VR_DOMAINS]; +} sku_overwrite_mapping[] = { + { + .sku = PRJ_AKALI, + .ac_loadline = { + AKALI_SA_AC_LOADLINE, + AKALI_IA_AC_LOADLINE, + AKALI_GT_AC_LOADLINE, + AKALI_GT_AC_LOADLINE + }, + .dc_loadline = { + AKALI_SA_DC_LOADLINE, + AKALI_IA_DC_LOADLINE, + AKALI_GT_DC_LOADLINE, + AKALI_GT_DC_LOADLINE + } + }, +}; + +static uint32_t get_pl2(int pl2_id) +{ + assert(pl2_id < ARRAY_SIZE(pl2_config_table)); + if (cpuid_eax(1) == CPUID_KABYLAKE_Y0) + return pl2_config_table[pl2_id].cpuid_y0_pl2; + + return pl2_config_table[pl2_id].cpuid_non_y0_pl2; +} + +uint32_t variant_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + uint32_t id; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + if (google_chromeec_cbi_get_sku_id(&id)) + return SKU_UNKNOWN; + sku_id = id; + + return sku_id; +} + +const char *smbios_mainboard_sku(void) +{ + static char sku_str[14]; /* sku{0..4294967295} */ + + snprintf(sku_str, sizeof(sku_str), "sku%u", variant_board_sku()); + + return sku_str; +} + +#define OEM_UNKNOWN 0xff + +/* + * Read OEM ID from EC using cbi commands. + * Return value: + * Success = OEM ID read from EC + * Failure = OEM_UNKNOWN (0xff) + */ +static uint8_t read_oem_id(void) +{ + static uint8_t oem_id = OEM_UNKNOWN; + uint32_t id; + + if (oem_id != OEM_UNKNOWN) + return oem_id; + + if (google_chromeec_cbi_get_oem_id(&id)) + return OEM_UNKNOWN; + + if (id > OEM_UNKNOWN) { + printk(BIOS_ERR, "%s: OEM ID too big %u!\n", __func__, id); + return OEM_UNKNOWN; + } + + oem_id = id; + printk(BIOS_DEBUG, "%s: OEM ID=%d\n", __func__, oem_id); + + return oem_id; +} + +/* "oem.bin" in cbfs contains array of records using the following structure. */ +struct oem_mapping { + uint8_t oem_id; + char oem_name[10]; +} __packed; + +/* Local buffer to read "oem.bin" */ +static char oem_bin_data[200]; + +const char *smbios_mainboard_manufacturer(void) +{ + uint8_t oem_id = read_oem_id(); + const struct oem_mapping *oem_entry = (void *)&oem_bin_data; + size_t oem_data_size; + size_t curr = 0; + static const char *manuf; + + if (manuf) + return manuf; + + /* If OEM ID cannot be determined, return default manuf string. */ + if (oem_id == OEM_UNKNOWN) + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, + sizeof(oem_bin_data), + CBFS_TYPE_RAW); + + while ((curr < oem_data_size) && + ((oem_data_size - curr) >= sizeof(*oem_entry))) { + if (oem_id == oem_entry->oem_id) { + manuf = oem_entry->oem_name; + break; + } + curr += sizeof(*oem_entry); + oem_entry++; + } + + if (manuf == NULL) + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + return manuf; +} + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id = variant_board_sku(); + + switch (sku_id) { + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + return "vbt-pantheon.bin"; + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + return "vbt-vayne.bin"; + case SKU_0_AKALI: + case SKU_1_AKALI: + case SKU_0_AKALI360: + case SKU_1_AKALI360: + return "vbt-akali.bin"; + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + return "vbt-bard.bin"; + default: + return "vbt.bin"; + break; + } +} + +static int find_sku_mapping(const uint8_t oem_id) +{ + /* Check if this OEM ID has a mapping table entry. */ + for (int i = 0; i < ARRAY_SIZE(sku_overwrite_mapping); i++) + if (oem_id == sku_overwrite_mapping[i].sku) + return i; + + return -1; +} + +/* Override dev tree settings per board */ +void variant_devtree_update(void) +{ + uint32_t sku_id = variant_board_sku(); + uint32_t i; + int oem_index; + struct device *root = SA_DEV_ROOT; + config_t *cfg = root->chip_info; + uint8_t pl2_id = PL2_ID_DEFAULT; + struct device *spi_fpmcu = PCH_DEV_GSPI1; + + switch (sku_id) { + case SKU_0_SONA: + case SKU_1_SONA: + case SKU_0_SYNDRA: + case SKU_1_SYNDRA: + case SKU_2_SYNDRA: + case SKU_3_SYNDRA: + case SKU_4_SYNDRA: + case SKU_5_SYNDRA: + case SKU_6_SYNDRA: + case SKU_7_SYNDRA: + pl2_id = PL2_ID_SONA_SYNDRA; + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: + cfg->usb2_ports[5].enable = 0; + spi_fpmcu->enabled = 0; + break; + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: + pl2_id = PL2_ID_BARD_EKKO; + cfg->usb2_ports[5].enable = 0; + cfg->usb2_ports[7].enable = 0; + cfg->usb2_ports[8].enable = 0; + cfg->usb2_ports[9].enable = 0; + break; + default: + break; + } + + /* Update PL2 based on SKU. */ + cfg->tdp_pl2_override = get_pl2(pl2_id); + + /* Overwrite settings for different projects based on OEM ID*/ + oem_index = find_sku_mapping(read_oem_id()); + + /* Return if the OEM ID is not supported or no changes are required */ + if (oem_index < 0) + return; + + for (i = 0; i < ARRAY_SIZE(cfg->domain_vr_config); i++) { + cfg->domain_vr_config[i].ac_loadline = + sku_overwrite_mapping[oem_index].ac_loadline[i]; + cfg->domain_vr_config[i].dc_loadline = + sku_overwrite_mapping[oem_index].dc_loadline[i]; + } +} diff --git a/src/mainboard/google/poppy/variants/sylas/memory.c b/src/mainboard/google/poppy/variants/sylas/memory.c new file mode 100644 index 0000000..b7f5185 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/memory.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <variant/gpio.h> +#include <string.h> + +/* Rcomp resistor */ +static const u16 rcomp_resistor_ddp[] = { 121, 81, 100 }; +static const u16 rcomp_resistor_sdp[] = { 200, 81, 100 }; +static const u16 rcomp_resistor_lpddr3[] = { 200, 81, 162 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 20, 20, 26 }; +static const u16 rcomp_target_lpddr3[] = { 100, 40, 40, 23, 40 }; + +/* DQ byte map */ +static const u8 dq_map_lpddr3[][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } +}; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map_lpddr3[][8] = { + { 1, 0, 3, 2, 6, 5, 4, 7 }, + { 0, 3, 2, 1, 6, 4, 7, 5 }, +}; + +/* Memory ids are 1-indexed, so subtract 1 to use 0-indexed values in bitmap. */ +#define MEM_ID(x) (1 << ((x) - 1)) + +/* Bitmap to indicate which memory ids are using DDP. */ +static const uint16_t ddp_bitmap = MEM_ID(4); + +static void fill_lpddr3_memory_params(struct memory_params *p) +{ + p->type = MEMORY_LPDDR3; + p->use_sec_spd = 1; + p->dq_map = dq_map_lpddr3; + p->dq_map_size = sizeof(dq_map_lpddr3); + p->dqs_map = dqs_map_lpddr3; + p->dqs_map_size = sizeof(dqs_map_lpddr3); + p->rcomp_resistor = rcomp_resistor_lpddr3; + p->rcomp_resistor_size = sizeof(rcomp_resistor_lpddr3); + p->rcomp_target = rcomp_target_lpddr3; + p->rcomp_target_size = sizeof(rcomp_target_lpddr3); +} + +static void fill_ddr4_memory_params(struct memory_params *p) +{ + p->type = MEMORY_DDR4; + p->use_sec_spd = 0; + + /* Rcomp resistor values are different for SDP and DDP. */ + if (ddp_bitmap & MEM_ID(variant_memory_sku())) { + p->rcomp_resistor = rcomp_resistor_ddp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_ddp); + } else { + p->rcomp_resistor = rcomp_resistor_sdp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_sdp); + } + + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} + +void variant_memory_params(struct memory_params *p) +{ + memset(p, 0, sizeof(*p)); + gpio_input_pulldown(GPIO_MEM_CONFIG_4); + if (gpio_get(GPIO_MEM_CONFIG_4)) + /* set to LPDDR3 */ + fill_lpddr3_memory_params(p); + else + /* default to DDR4 */ + fill_ddr4_memory_params(p); + + /* GPP_D10 set to 0 for dual channel and 1 for single channel */ + if (gpio_get(GPP_D10)) + p->single_channel = 1; +} diff --git a/src/mainboard/google/poppy/variants/sylas/nhlt.c b/src/mainboard/google/poppy/variants/sylas/nhlt.c new file mode 100644 index 0000000..c3096d4 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/nhlt.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void variant_nhlt_init(struct nhlt *nhlt) +{ + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + + /* Dialog DA7219 Headset codec. */ + if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); + +} + +void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "NAMIMAX"; + *oem_revision = 0; +} diff --git a/src/mainboard/google/poppy/variants/sylas/smihandler.c b/src/mainboard/google/poppy/variants/sylas/smihandler.c new file mode 100644 index 0000000..6816508 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/smihandler.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <delay.h> +#include "gpio.h" + +#define TOUCH_DISABLE GPP_C3 +#define TOUCH_RESET GPP_B3 +#define TOUCH_ENABLE GPP_B4 +#define FP_PWR_ENABLE GPP_B11 + +/* + * Elan touchscreen has higher delay requirements than the other + * devices, so using that. + */ +#define ELAN_STOP_OFF_DELAY 2 +#define ELAN_RESET_OFF_DELAY 2 +#define ELAN_ENABLE_OFF_DELAY 100 + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* TOUCHSCREEN_DIS# */ + gpio_set(TOUCH_DISABLE, 0); + mdelay(ELAN_STOP_OFF_DELAY); + /* TOUCHSCREEN_RST# */ + gpio_set(TOUCH_RESET, 0); + mdelay(ELAN_RESET_OFF_DELAY); + /* EN_PP3300_DX_TOUCHSCREEN */ + gpio_set(TOUCH_ENABLE, 0); + mdelay(ELAN_ENABLE_OFF_DELAY); + /* PCH_FP_PWR_EN */ + gpio_set(FP_PWR_ENABLE, 0); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa43b72d4e1f61a50ab624ad8bd2938c3a1ef809 Gerrit-Change-Number: 41648 Gerrit-PatchSet: 1 Gerrit-Owner: Danomi Lin <lin.danomi(a)inventec.corp-partner.google.com> Gerrit-MessageType: newchange

8 17

Change in ...coreboot[master]: [WIP]x86: Introduce the blobolator
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32020 Change subject: [WIP]x86: Introduce the blobolator ...................................................................... [WIP]x86: Introduce the blobolator This is a PoC to run arbitrary code and blobs inside an emulated virtual machine using libx86emu, thus the name blobolator. The libx86emu has been patched to the following: * redirect IO to the host machine it's running on * trace IO * start in protected mode * add mechanism to drop IO access * add Kconfig to debug code it is running Implemented features: * Run ramstage in libx86emu * Run postcar in libx86emu TODO: * Add support to trace only blobs, not stages. * Improve translation of known IO to human readable format ** COM ** PCI ** APIC ** PIT ** POST Tested on qemu. Sucessfully run ramstage in blobolator. Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/Kconfig M src/arch/x86/boot.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/vendorcode/Makefile.inc A src/vendorcode/libx86emu/Makefile.inc A src/vendorcode/libx86emu/blobolator.c A src/vendorcode/libx86emu/decode.c A src/vendorcode/libx86emu/include/decode.h A src/vendorcode/libx86emu/include/mem.h A src/vendorcode/libx86emu/include/ops.h A src/vendorcode/libx86emu/include/prim_ops.h A src/vendorcode/libx86emu/include/x86emu.h A src/vendorcode/libx86emu/include/x86emu_int.h A src/vendorcode/libx86emu/mem.c A src/vendorcode/libx86emu/ops.c A src/vendorcode/libx86emu/ops2.c A src/vendorcode/libx86emu/prim_ops.c 18 files changed, 14,512 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32020/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Gerrit-Change-Number: 32020 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

10 31

Change in coreboot[master]: Documentation: Add guidelines for new mainboard ports
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34632 ) Change subject: Documentation: Add guidelines for new mainboard ports ...................................................................... Documentation: Add guidelines for new mainboard ports This is WIP and partly copied from https://www.coreboot.org/Motherboard_Porting_Guide It also list what should be documented for new mainboard ports. Change-Id: I134dbf2341696ba0dd33c3d52bf787b8eaabbdab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/getting_started/index.md A Documentation/getting_started/new_mainboard_ports.md M Documentation/getting_started/writing_documentation.md 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34632/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..7821ee1 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [Adding new mainboards](new_mainboard_ports.md) diff --git a/Documentation/getting_started/new_mainboard_ports.md b/Documentation/getting_started/new_mainboard_ports.md new file mode 100644 index 0000000..cb7cd9b --- /dev/null +++ b/Documentation/getting_started/new_mainboard_ports.md @@ -0,0 +1,91 @@ +# Adding new mainboards + +Mainboard code is placed under `src/mainboards`. It glues the HW components +together by selecting appropiate northbridge, southbridge, on-board HW and +drivers. + +It provides the devicetree.cb, configures GPIOs, audio codecs, a static ACPI +board desciption and allows the romstage code to retrieve the SPD for +DRAM training. + +## Starting a new port from scratch + +1. Identify your platform + Try to find out as much as possible about the current hardware. + Dump information with existing tools: + * lspci + * lsusb + * superiotool + * inteltool + * ectool + * dmidecode + * acpidump + + Have a look at the mainboard schematics to see how those components are + connected. +2. Find a similar existing board + It a good idea to find a similar board and use it as reference. You should + then provide a proper GPIO configuration and devicetree.cb. +3. Find a similar SuperIo or BMC + To debug coreboot you should get the serial console working first. If your + board has a SuperIO or BMC try to find a compatible one. + Some boards have UART hardware on the SoC, makeing external components + obsolete. +4. Start with a minimal bootable configuration. That is: + * serial is working + * SPD reading/DRAM is working + * A payload that is able to boot an operating system +5. Be able to recover from a bad flash. You should use external flashing as + it's likely that you will brick your platform on the first attempts. + Make sure to backup the original firmware (if any). + +## Code submission + +Here's a checklist for new mainboard ports: + +1. Try to not duplicate code, use variants scheme instead. +2. Split changes logical into top level directories: + `src/mainboard` , `src/northbridge`, `src/ec`, ... +3. Provide good documentation, see point 4 +4. In the commit message describe as much as possible or point to the + documentation, satisfying the following questions: + * Where's the flash IC located? + * Can you flash incircuit? + * Are there pinheaders for flashing? + * Is the flash hardware write-protected? + * Which flash IC is usually equipped? + * If the board features an BMC, can it be used for developing and + debugging? + * What was tested and is working? + * What was tested and isn't working? + * What wasn't tested (due to lack of testing equipment)? + * Are blobs necessary? + * How can the board be debugged? + * Are there serial, EHCI debug, xHCI debug or BMC connections? + * Does it have a SuperIO? + + In addition please descibe: + * How to retrieve blobs, like dumping them from vendor firmware + + See [Writing Documentation] for more details. + +5. What you should **not** document: + * Steps or instructions how to flash the board + * Steps or instructions how to use a specific application for flashing + * Please do not provide pictures of the whole board or it's backplate + connectors +6. Recommand a flashing method as descibed in [Flashing tutorial] +7. If you are working at/for a hardware vendor, please provide free board + schematics as well. +8. Provide a picture of the flash IC or flash connector. + * The picture should be less than 800pc in width and compressed with + 70% compression to reduce size. + * You must own the Copyright + * Try to cut of uninteresting parts of the image, like tables, cables, ... + +Once done submit your board to Gerrit. Please follow the [Gerrit Guidelines] as +well. + +[Writing Documentation]: writing_documentation.md +[Flashing tutorial]: ../flash_tutorial/index.md +[Gerrit Guidelines]: gerrit_guidelines.md diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index fb942a4..0b820fc 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -49,6 +49,8 @@ the current theme doesn't allow bigger images. 12. Shouldn't cover implementation details; for details, the code is the reference. +13. New mainboard ports should also add documentation. See + [Adding new mainboards] for more details. ## Referencing markdown documents @@ -122,3 +124,4 @@ [Markdown Guide]: https://www.markdownguide.org/ [Gerrit Guidelines]: gerrit_guidelines.md [review.coreboot.org]: https://review.coreboot.org +[Adding new mainboards]: new_mainboard_ports.md -- To view, visit https://review.coreboot.org/c/coreboot/+/34632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I134dbf2341696ba0dd33c3d52bf787b8eaabbdab Gerrit-Change-Number: 34632 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 19

Change in coreboot[master]: mb/kontron/986lcd-m: Select FIXED_UART_FOR_CONSOLE
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39124 ) Change subject: mb/kontron/986lcd-m: Select FIXED_UART_FOR_CONSOLE ...................................................................... mb/kontron/986lcd-m: Select FIXED_UART_FOR_CONSOLE The serial port base address is hardcoded for this mainboard, so deactivate the Kconfig dialog for `TTYS0_BASE`. Change-Id: Ic989e4c4fde8ce03c6941c44f71dc72840fc77c3 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/kontron/986lcd-m/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/39124/1 diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index dfc7c3c..204d404 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -9,6 +9,7 @@ select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off + select FIXED_UART_FOR_CONSOLE select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/39124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic989e4c4fde8ce03c6941c44f71dc72840fc77c3 Gerrit-Change-Number: 39124 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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