coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: cpu/x86: Select proper SMM save Kconfig option
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45473 ) Change subject: cpu/x86: Select proper SMM save Kconfig option ...................................................................... cpu/x86: Select proper SMM save Kconfig option Note: Qemu always uses AMD64 save states but messes up the revision if the CPU is set to be a 32bit-only one the save state revision is 0 but still uses the AMD64 one. This is currently not handled by coreboot. Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 30 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45473/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b..538fb6c 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 533507e..0aa3183 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE if CPU_AMD_PI diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 18fc392..1242dd7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -21,6 +21,7 @@ select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 0a29d69..b29d426 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,3 +12,4 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 095fee5..44d9805 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -14,6 +14,8 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..de3e835 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..abb8eba 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 0c92479..50c64b9 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -8,3 +8,5 @@ select SMM_ASEG select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index fbb00fa..60eeac7 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -7,3 +7,5 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 9398d18..91adff9 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -5,3 +5,4 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 2b6deb6..720ce11 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -17,6 +17,7 @@ select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE select SETUP_XIP_CACHE + select X86_LEGACY_SAVE_STATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index af43f72..9c5f292 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -9,6 +9,7 @@ select MMX select SSE select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 638653c..b903fdf 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -3,6 +3,7 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE + select X86_EM64T101_SAVE_STATE if CPU_INTEL_SOCKET_BGA956 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8db932c..2c2141c 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -14,6 +14,7 @@ select MMX select SSE select SIPI_VECTOR_IN_ROM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 8b1f5ed..0ca7c99 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -9,6 +9,8 @@ select CPU_INTEL_MODEL_6FX select MMX select SSE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 176ae9e..8911a8d 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -13,6 +13,7 @@ select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 06ac685..6aa081b 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -13,6 +13,7 @@ select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select X86_AMD64_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c..19fb1d3 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_CHROMEOS + select X86_AMD64_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..7e28e27 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -58,6 +58,7 @@ select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd99..59f6a66 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -48,6 +48,7 @@ select SSE2 select RTC select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f837a2e..817c3e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -105,6 +105,7 @@ select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select X86_EM64T100_SAVE_STATE config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b23f56d..a74f243 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select X86_EM64T100_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index bf067da..2e7d32e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -44,6 +44,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + select X86_EM64T100_SAVE_STATE config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..7b0a0bd 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -43,6 +43,7 @@ select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select X86_EM64T101_SAVE_STATE config PCIEXP_ASPM bool diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..981ac69 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -113,6 +113,7 @@ select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE + select X86_EM64T101_SAVE_STATE config MAX_CPUS int diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3fce223..202704a8 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -40,6 +40,7 @@ select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS + select X86_EM64T100_SAVE_STATE config MMCONF_BASE_ADDRESS hex diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1230675..bc4c44c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -61,6 +61,7 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index f2922f5..2f23c5f 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -62,6 +62,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..338a5be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -79,6 +79,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select X86_EM64T101_SAVE_STATE config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2659357..beb87ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -62,6 +62,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/45473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Gerrit-Change-Number: 45473 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: device/pci: Don't enabled unassigned resources
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Furquan Shaikh, Arthur Heymans, Kyösti Mälkki, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41553 to review the following change. Change subject: device/pci: Don't enabled unassigned resources ...................................................................... device/pci: Don't enabled unassigned resources We only have a single bit in the PCI_COMMAND register to enable or disable resources of one type. If any resource of a type is unassigned, we have to disable all of them. Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/pci_device.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/41553/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5afbfa9..8df44df 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -506,7 +506,8 @@ } } -static void pci_set_resource(struct device *dev, struct resource *resource) +static void pci_set_resource(struct device *const dev, struct resource *const resource, + uint16_t *const command_mask) { /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { @@ -518,6 +519,11 @@ printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " "assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); + /* We'll have to disable all resources of this type. */ + if (resource->flags & IORESOURCE_MEM) + *command_mask &= ~PCI_COMMAND_MEMORY; + if (resource->flags & IORESOURCE_IO) + *command_mask &= ~PCI_COMMAND_IO; return; } } @@ -561,12 +567,16 @@ void pci_dev_set_resources(struct device *dev) { + uint16_t command_mask = 0xffff; struct resource *res; struct bus *bus; u8 line; for (res = dev->resource_list; res; res = res->next) - pci_set_resource(dev, res); + pci_set_resource(dev, res, &command_mask); + /* If there are unassigned resources, we might + have to disable others of the same type. */ + dev->command &= command_mask; for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) -- To view, visit https://review.coreboot.org/c/coreboot/+/41553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e Gerrit-Change-Number: 41553 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: cpu/x86/smm: Add a function for the amount of support CPUs
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47016 ) Change subject: cpu/x86/smm: Add a function for the amount of support CPUs ...................................................................... cpu/x86/smm: Add a function for the amount of support CPUs CONFIG_MAX_CPUS might be larger than the amount for which an SMI handler is installed. So when looping over CONFIG_MAX_CPUS to fetch a SMM save state one might access memory that does not belong to a CPU node save state and get invalid results. Change-Id: Ibc17602aa2817d910292c37d0a0095d3d9dc0aae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/amd64_save_state.c M src/cpu/intel/smm/em64t100_save_state.c M src/cpu/intel/smm/em64t101_save_state.c M src/cpu/x86/smm/legacy_save_state.c M src/cpu/x86/smm/save_state.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 8 files changed, 20 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47016/1 diff --git a/src/cpu/amd/smm/amd64_save_state.c b/src/cpu/amd/smm/amd64_save_state.c index db329c0..a274fd1 100644 --- a/src/cpu/amd/smm/amd64_save_state.c +++ b/src/cpu/amd/smm/amd64_save_state.c @@ -84,7 +84,7 @@ int node; u8 reg_al; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); smm_io_trap = state->smm_io_trap_offset; diff --git a/src/cpu/intel/smm/em64t100_save_state.c b/src/cpu/intel/smm/em64t100_save_state.c index 4fd7d76..fe5f65e 100644 --- a/src/cpu/intel/smm/em64t100_save_state.c +++ b/src/cpu/intel/smm/em64t100_save_state.c @@ -72,7 +72,7 @@ em64t100_smm_state_save_area_t *state; int node; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); /* Check for Synchronous IO (bit0 == 1) */ diff --git a/src/cpu/intel/smm/em64t101_save_state.c b/src/cpu/intel/smm/em64t101_save_state.c index c6aa397..70112df 100644 --- a/src/cpu/intel/smm/em64t101_save_state.c +++ b/src/cpu/intel/smm/em64t101_save_state.c @@ -72,7 +72,7 @@ em64t101_smm_state_save_area_t *state; int node; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); /* Check for Synchronous IO (bit0 == 1) */ diff --git a/src/cpu/x86/smm/legacy_save_state.c b/src/cpu/x86/smm/legacy_save_state.c index 8e996ee..0b07155 100644 --- a/src/cpu/x86/smm/legacy_save_state.c +++ b/src/cpu/x86/smm/legacy_save_state.c @@ -71,7 +71,7 @@ legacy_smm_state_save_area_t *state; int node; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); /* Check AL against the requested command */ diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c index bb08f86..c860b03 100644 --- a/src/cpu/x86/smm/save_state.c +++ b/src/cpu/x86/smm/save_state.c @@ -59,7 +59,7 @@ if (init_save_state()) return -1; - if (node > CONFIG_MAX_CPUS) + if (node > smm_max_cpus()) return -1; return save_state->get_reg(reg, node, out, length); @@ -70,7 +70,7 @@ if (init_save_state()) return -1; - if (node > CONFIG_MAX_CPUS) + if (node > smm_max_cpus()) return -1; return save_state->set_reg(reg, node, in, length); diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 0d9131e..21b2b5e 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -136,6 +136,11 @@ return region_overlap(&r_smm, r); } +uint32_t smm_max_cpus(void) +{ + return CONFIG_MAX_CPUS; +} + /** * @brief Interrupt handler for SMI# * diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684..89864c4 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -119,6 +119,11 @@ return region_overlap(&r_smm, r) || region_overlap(&r_aseg, r); } +uint32_t smm_max_cpus(void) +{ + return MIN(smm_runtime->num_cpus, CONFIG_MAX_CPUS); +} + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; @@ -137,7 +142,7 @@ if (smm_runtime == NULL) smm_runtime = runtime; - if (cpu >= CONFIG_MAX_CPUS) { + if (cpu >= smm_max_cpus()) { console_init(); printk(BIOS_CRIT, "Invalid CPU number assigned in SMM stub: %d\n", cpu); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6cf6f82..8bdd695 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -98,6 +98,9 @@ * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); +/* Return the amount of CPUs the smihandler is set up to handle. */ +uint32_t smm_max_cpus(void); + /* Returns true if the region overlaps with the SMM */ bool smm_region_overlaps_handler(const struct region *r); -- To view, visit https://review.coreboot.org/c/coreboot/+/47016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc17602aa2817d910292c37d0a0095d3d9dc0aae Gerrit-Change-Number: 47016 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [RFC] libpayload/keyboard: Dynamically toggle controller translation
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46730 ) Change subject: [RFC] libpayload/keyboard: Dynamically toggle controller translation ...................................................................... [RFC] libpayload/keyboard: Dynamically toggle controller translation This is what would be necessary to detect cases where we have to toggle the keyboard controller's scancode translation. After setting the matching scancode set for the current translation setting, we read it back and try to adapt the translation setting of necessary. It adds a lot complexity, so we'd probably want to avoid it? Chances that we find a keyboard that can't switch scancode sets and isn't integrated (where we could set the correct translation setting in coreboot) seem rather low. Change-Id: I938184875e1c4c40cdb2762e1c5b6ed9c8f82b90 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/drivers/i8042/i8042.c M payloads/libpayload/drivers/i8042/i8042.h M payloads/libpayload/drivers/i8042/keyboard.c 3 files changed, 102 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46730/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 317d04b..487863e 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -317,6 +317,24 @@ } /** + * Send command & data to keyboard controller. + * + * @param cmd: The command to be send. + * @param data: The data to be send. + * Returns 0 on success, -1 on failure. + */ +int i8042_cmd_with_data(const u8 cmd, const u8 data) +{ + const int ret = i8042_cmd(cmd); + if (ret != 0) + return ret; + + i8042_write_data(data); + + return ret; +} + +/** * Probe for keyboard controller data and queue it. */ static void i8042_data_poll(void) diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 68fd149..f2dc0d0 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -29,6 +29,8 @@ #ifndef __DRIVERS_I8042_I8042_H__ #define __DRIVERS_I8042_I8042_H__ +#include <stdint.h> + /* Port 0x64 commands */ #define I8042_CMD_RD_CMD_BYTE 0x20 #define I8042_CMD_WR_CMD_BYTE 0x60 @@ -67,5 +69,6 @@ #define I8042_KBCMD_RESET 0xff int i8042_cmd_with_response(u8 cmd); +int i8042_cmd_with_data(u8 cmd, u8 data); #endif /* __DRIVERS_I8042_I8042_H__ */ diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index aa21b9d..c3cba9b 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <assert.h> #include <stdbool.h> #include <keycodes.h> @@ -326,27 +327,90 @@ return ctrl_cfg < 0 || (ctrl_cfg & I8042_CMD_BYTE_XLATE); } -/* Set scancode set 1 */ -static bool set_scancode_set(const unsigned char set) +static bool send_scancode_set(const unsigned char set) { - bool ret; + assert(set <= 3); - if (set < 1 || set > 3) + if (!keyboard_cmd(I8042_KBCMD_SET_SCANCODE) || + !keyboard_cmd(set)) { + printf("ERROR: Keyboard send scancode set#%u failed!\n", set); + return false; + } + return true; +} + +static unsigned char select_scancode_set(const bool xlate) +{ + /* + * We only support scancode set 1. The controller translation + * would translate from set 2 to 1 for us, so we try to configure: + * + * o set 1 if the controller doesn't translate, and + * o set 2 if the controller does. + */ + const unsigned char set = xlate ? 2 : 1; + + if (!send_scancode_set(set)) + return 2; + + /* + * Now try to confirm the current scancode set selection. + */ + if (!send_scancode_set(0)) /* retrieve current scancode set # */ + return 2; + + int actual_set = i8042_wait_read_ps2(); + if (xlate) { + /* controllers translate even this answer */ + switch (actual_set) { + case 0x43: actual_set = 1; break; + case 0x41: actual_set = 2; break; + case 0x3f: actual_set = 3; break; + } + } + + if (actual_set < 1) /* assume success on unexpected data */ + return set; + + return actual_set; +} + +static bool prepare_scancode_set(void) +{ + const bool xlate = controller_translates(); + + const unsigned char set = select_scancode_set(xlate); + + if (set > 2) /* We can't do anything with scancode set #3. */ return false; - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret) { - printf("ERROR: Keyboard set scancode failed!\n"); - return ret; + if ((set != 2 && !xlate) || (set == 2 && xlate)) + return true; + + /* + * In case we failed to set the correct scancode set, fall back + * and try to change the controller's translation setting. + */ + printf("WARNING: Keyboard failed to select correct scancode set.\n"); + + int ctrl_cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE); + if (ctrl_cfg < 0) { + printf("ERROR: i8042_cmd RD_CMD failed!\n"); + return false; } - ret = keyboard_cmd(set); - if (!ret) { - printf("ERROR: Keyboard scancode set#%u failed!\n", set); - return ret; + if (xlate) + ctrl_cfg &= ~I8042_CMD_BYTE_XLATE; + else + ctrl_cfg |= I8042_CMD_BYTE_XLATE; + + const int ret = i8042_cmd_with_data(I8042_CMD_WR_CMD_BYTE, ctrl_cfg); + if (ret < 0) { + printf("ERROR: i8042_cmd WR_CMD failed!\n"); + return false; } - return ret; + return true; } void keyboard_init(void) @@ -364,14 +428,10 @@ /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - /* - * We only support scancode set 1. The controller translation - * would translate from set 2 to 1 for us, so we try to configure - * - * o set 1 if the controller doesn't translate, and - * o set 2 if the controller does. - */ - (void)set_scancode_set(controller_translates() ? 2 : 1); + if (!prepare_scancode_set()) { + printf("ERROR: Keyboard failed to configure scancode set, giving up.\n"); + return; + } /* Enable scanning */ const bool ret = keyboard_cmd(I8042_KBCMD_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/46730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I938184875e1c4c40cdb2762e1c5b6ed9c8f82b90 Gerrit-Change-Number: 46730 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH
by Iru Cai (vimacs) (Code Review) 10 Jun '23

10 Jun '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41485 to review the following change. Change subject: sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH ...................................................................... sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH GPI_ROUT is in LynxPoint-H PCH [1], and not in LynxPoint-LP [2]. So call pch_gpi_routing() when PCH is not -LP. Also add GPI_ROUT2 register according to the datasheet. Need testing on real hardware. [1] Intel 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, Document Number 328904-003 [2] Mobile 4th Generation Intel Core Processor Family I/O Datasheet, Document Number: 329003-003 Change-Id: Id9999ea9cb44565832d44a57423e89ede1c6b238 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41485/1 diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ed362a2..ce38faa 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -44,6 +44,14 @@ uint8_t gpi13_routing; uint8_t gpi14_routing; uint8_t gpi15_routing; + uint8_t gpi17_routing; + uint8_t gpi19_routing; + uint8_t gpi21_routing; + uint8_t gpi22_routing; + uint8_t gpi43_routing; + uint8_t gpi56_routing; + uint8_t gpi57_routing; + uint8_t gpi60_routing; uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3535312..e15452e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -161,6 +161,18 @@ reg32 |= (config->gpi15_routing & 0x03) << 30; pci_write_config32(dev, GPIO_ROUT, reg32); + + reg32 = 0; + reg32 |= (config->gpi17_routing & 0x03) << 0; + reg32 |= (config->gpi19_routing & 0x03) << 2; + reg32 |= (config->gpi21_routing & 0x03) << 4; + reg32 |= (config->gpi22_routing & 0x03) << 6; + reg32 |= (config->gpi43_routing & 0x03) << 8; + reg32 |= (config->gpi56_routing & 0x03) << 10; + reg32 |= (config->gpi57_routing & 0x03) << 12; + reg32 |= (config->gpi60_routing & 0x03) << 14; + + pci_write_config32(dev, GPIO_ROUT2, reg32); } static void pch_power_options(struct device *dev) @@ -243,7 +255,7 @@ * Set the board's GPI routing on LynxPoint-H. * This is done as part of GPIO configuration on LynxPoint-LP. */ - if (pch_is_lp()) + if (!pch_is_lp()) pch_gpi_routing(dev); /* GPE setup based on device tree configuration */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 19f8637..8e1f9f1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -214,6 +214,7 @@ #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 +#define GPIO_ROUT2 0xbc #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 -- To view, visit https://review.coreboot.org/c/coreboot/+/41485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9999ea9cb44565832d44a57423e89ede1c6b238 Gerrit-Change-Number: 41485 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
by David Jimenez (Code Review) 10 Jun '23

10 Jun '23

David Jimenez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38947 ) Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ...................................................................... mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration Signed-off-by: David Jimenez <dvjimenez(a)chromium.org> Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38947/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f7cf3cd..f360c10 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -50,6 +50,8 @@ register "PchUnlockGpioPads" = "1" # SD card WP pin confguration register "ScsSdCardWpPinEnabled" = "0" + # Auto-switch between X4 NVMe and X2 NVMe for hybrid storage support + register "TetonGlacierMode" = "1" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of @@ -163,7 +165,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" - # Enable Root port 9(x4) for NVMe. + # Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -171,6 +173,10 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + # Enable Root port 11(x2) for NVMe hybrid storage devices. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" @@ -324,9 +330,9 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on end # PCI Express Port 9 (X2 NVME) device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.2 on end # PCI Express Port 11 (x2 NVME) device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..16265d2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + // Enables support for Teton Glacier hybrid storage device + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..e8ad62f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ #endif params->Device4Enable = config->Device4Enable; + /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df Gerrit-Change-Number: 38947 Gerrit-PatchSet: 1 Gerrit-Owner: David Jimenez <dvjimenez(a)chromium.org> Gerrit-MessageType: newchange

7 8

Change in coreboot[master]: mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46558 ) Change subject: mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation ...................................................................... mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation Use the more readable size notation, which also unifies it with Mandolin’s FMD. Change-Id: I95c22d8d775104dc046601418bd402317dd8e676 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/cereme/board.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46558/1 diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd index b55b8b5..31a0b2a 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/board.fmd +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -1,7 +1,7 @@ FLASH@0xFF000000 16M { BIOS { EC 0x20000 - RW_MRC_CACHE 0x10000 + RW_MRC_CACHE 64K FMAP 0x1000 COREBOOT(CBFS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95c22d8d775104dc046601418bd402317dd8e676 Gerrit-Change-Number: 46558 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/intel: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37314 ) Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb/intel: Add unaligned flag (%) sections that don't need alignment Sections that won't be updated independently and don't need to be aligned. Note: glkrvp/chromeos.fmd had unaligned RW_SECTION_{A,B} and is fixed now. leafhill/leafhill.8192.fmd had unaligned UNIFIED_MRC_CACHE and is fixed. Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/intel/baskingridge/chromeos.fmd M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/glkrvp/chromeos.fmd M src/mainboard/intel/icelake_rvp/chromeos.fmd M src/mainboard/intel/kblrvp/chromeos.fmd M src/mainboard/intel/kunimitsu/chromeos.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/intel/strago/chromeos.fmd M src/mainboard/intel/wtm2/chromeos.fmd 14 files changed, 88 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37314/1 diff --git a/src/mainboard/intel/baskingridge/chromeos.fmd b/src/mainboard/intel/baskingridge/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/baskingridge/chromeos.fmd +++ b/src/mainboard/intel/baskingridge/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..0a7be5f 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..d4f9021 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -20,13 +20,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -40,11 +40,11 @@ RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 + RO_UNUSED@0x4000% 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46..fbaca9b 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -4,9 +4,9 @@ IFWI@0x1000 0x1ff000 RO_VPD(PRESERVE)@0x200000 0x4000 RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 COREBOOT(CBFS)@0x1000 0x1ab000 GBB@0x1ac000 0x40000 RO_UNUSED@0x1ec000 0x10000 @@ -27,17 +27,17 @@ FPF_STATUS@0x3B000 0x1000 TMP_UNUSED_HOLE@0x3C000 0xE000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x44a000 0x478000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x467fc0 + RW_FWID_A@0x477fc0% 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8c2000 0x478000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x467fc0 + RW_FWID_B@0x477fc0% 0x40 } - RW_NVRAM(PRESERVE)@0xd39000 0x6000 + RW_NVRAM(PRESERVE)@0xd3a000 0x6000 SMMSTORE(PRESERVE)@0xd40000 0x40000 RW_LEGACY(CBFS)@0xd80000 0x1b0000 BIOS_UNUSABLE@0xf3f000 0x40000 diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd index f4db8b4..037de53 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kblrvp/chromeos.fmd +++ b/src/mainboard/intel/kblrvp/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.fmd +++ b/src/mainboard/intel/kunimitsu/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..a7a6b26 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xc1d800 + FMAP@0x300000% 0x800 + COREBOOT(CBFS)@0x300800% 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..3fe71e0 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,9 +1,9 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 - COREBOOT(CBFS)@0x321800 0x300000 - UNIFIED_MRC_CACHE@0x621800 0x21000 { + FMAP@0x321000% 0x800 + COREBOOT(CBFS)@0x321800% 0x300800 + UNIFIED_MRC_CACHE@0x622000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..9733567 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 - COREBOOT(CBFS)@0x301800 0x3dc800 + FMAP@0x301000% 0x800 + COREBOOT(CBFS)@0x301800% 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd index 923c8ee..5dec9ec 100644 --- a/src/mainboard/intel/strago/chromeos.fmd +++ b/src/mainboard/intel/strago/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x6f000 COREBOOT(CBFS)@0x70000 0x180000 } diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/wtm2/chromeos.fmd +++ b/src/mainboard/intel/wtm2/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Gerrit-Change-Number: 37314 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43483 ) Change subject: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ...................................................................... Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ELTAN verified boot seems to be using vboot 2.1 key format not vboot 1.0. Generating vboot 1.0 keys results in public key of incorrect size (according to the verified boot implementation in vendorcode) which results in errors during booting. Fix the cbfstool extraction command to take account for stage file which may have certain sections removed. Add note about endianess of digest generated by openssl. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 --- M Documentation/vendorcode/eltan/security.md 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43483/1 diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md index 9dd47c0..1c05cd5 100644 --- a/Documentation/vendorcode/eltan/security.md +++ b/Documentation/vendorcode/eltan/security.md @@ -42,7 +42,7 @@ Create private key in RSA2048 format: `openssl genrsa -F4 -out <private_key_file> 2048` Create public key using private key: -`futility --vb1 create <private_key_file> <public_key_file_without_extension>` +`futility --vb21 create <private_key_file> <public_key_file_without_extension>` The public key will be included into coreboot and used for verified boot only. @@ -79,9 +79,15 @@ The total number of items must match `VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS`. For every part the SHA (SHA-256) must be calculated. First extract the binary from the coreboot -image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name>` +image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name> -m x86 -U` +Note the `-m x86 -U` flags are required for correct extraction of stages. Certain stages are +put in CBFS without certain program sections so extraction process must also remove these sections. + followed by: `openssl dgst -sha256 -binary -out <hash_file_name> <item_binary_file_name>` +The SHA256 digest will be in big endian so it must be converted to little endian with: +`< <hash_file_name> xxd -p -c1 | tac | xxd -p -r > <hash_file_name_le>` + Replace -sha256 with -sha512 when `VENDORCODE_ELTAN_VBOOT_USE_SHA512` is enabled. All the hashes must be combined to a hash binary. The hashes need to be placed in the same order as -- To view, visit https://review.coreboot.org/c/coreboot/+/43483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 Gerrit-Change-Number: 43483 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37317 ) Change subject: mb: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb: Add unaligned flag (%) sections that don't need alignment Fix all FMD files with unaligned sections. Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd M src/mainboard/lenovo/t400/vboot-rwa.fmd M src/mainboard/lenovo/t410/vboot-rwa.fmd M src/mainboard/lenovo/t420/vboot-rwa.fmd M src/mainboard/lenovo/t420s/vboot-rwa.fmd M src/mainboard/lenovo/t520/vboot-rwa.fmd M src/mainboard/lenovo/x200/vboot-rwa.fmd M src/mainboard/lenovo/x201/vboot-rwa.fmd M src/mainboard/lenovo/x220/vboot-rwa.fmd M src/mainboard/opencellular/elgon/vboot.fmd M src/mainboard/samsung/lumpy/chromeos.fmd M src/mainboard/samsung/stumpy/chromeos.fmd M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd M src/mainboard/up/squared/vboot-ro.fmd M src/mainboard/up/squared/vboot-roa.fmd M src/mainboard/up/squared/vboot-roab.fmd 19 files changed, 104 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37317/1 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/t400/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd index 8f50d33..885aa0d 100644 --- a/src/mainboard/lenovo/t410/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -20,9 +20,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION 0x11e000 { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t520/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/x200/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd index 0d1aa5d..dc035e9 100644 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -19,9 +19,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd index 0d6af2d..dbb31cb 100644 --- a/src/mainboard/opencellular/elgon/vboot.fmd +++ b/src/mainboard/opencellular/elgon/vboot.fmd @@ -4,8 +4,8 @@ RO_SECTION@0x0 0x3fc000 { # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 - FMAP@0x0 0x1000 - RO_FRID@0x1000 0x100 + FMAP@0x0% 0x1000 + RO_FRID@0x1000% 0x100 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. @@ -17,13 +17,13 @@ } RW_SECTION_A@0x400000 0x5fa000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x5f7f00 - RW_FWID_A@0x5f9f00 0x100 + FW_MAIN_A(CBFS)@0x2000% 0x5f7f00 + RW_FWID_A@0x5f9f00% 0x100 } RW_SECTION_B@0x9fa000 0x5fa000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x5f7f00 - RW_FWID_B@0x5f9f00 0x100 + FW_MAIN_B(CBFS)@0x2000% 0x5f7f00 + RW_FWID_B@0x5f9f00% 0x100 } RW_ELOG(PRESERVE)@0xff4000 0x4000 RW_VPD(PRESERVE)@0xff8000 0x8000 diff --git a/src/mainboard/samsung/lumpy/chromeos.fmd b/src/mainboard/samsung/lumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/lumpy/chromeos.fmd +++ b/src/mainboard/samsung/lumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/samsung/stumpy/chromeos.fmd b/src/mainboard/samsung/stumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/stumpy/chromeos.fmd +++ b/src/mainboard/samsung/stumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 36772d6..2dd2173 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI 0x2ff000 - FMAP 0x800 - COREBOOT(CBFS) 0xb9d800 + FMAP% 0x800 + COREBOOT(CBFS)% 0xb9d800 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 RW_MRC_CACHE 0x10000 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index 8af2e9a..c9d1c148 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -4,9 +4,9 @@ IFWI 0x2ff000 RO_VPD 0x4000 RO_SECTION 0xb8f000 { - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_FRID_PAD% 0x7c0 COREBOOT(CBFS) 0xb4e000 GBB 0x40000 } diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd index a295680..96f359e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x500000 0xb00000 { RW_SECTION_A@0x0 0x33e000 { VBLOCK_A@0x0 0x20000 - FW_MAIN_A(CBFS)@0x20000 0x31dfc0 - RW_FWID_A@0x33dfc0 0x40 + FW_MAIN_A(CBFS)@0x20000% 0x31dfc0 + RW_FWID_A@0x33dfc0% 0x40 } RW_SECTION_B@0x33e000 0x33e000 { VBLOCK_B@0x0 0x20000 - FW_MAIN_B(CBFS)@0x20000 0x31dfc0 - RW_FWID_B@0x33dfc0 0x40 + FW_MAIN_B(CBFS)@0x20000% 0x31dfc0 + RW_FWID_B@0x33dfc0% 0x40 } MISC_RW@0x67d000 0x62000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -25,9 +25,9 @@ WP_RO@0x6df000 0x421000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x41d000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x32d000 } diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd index 72f92fe..afebc8c 100644 --- a/src/mainboard/up/squared/vboot-ro.fmd +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0xe91000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0xb8d800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0xb8d800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0xb4d000 } diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd index 330ce03..b23e69f 100644 --- a/src/mainboard/up/squared/vboot-roa.fmd +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x502000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1fe800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1fe800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1be000 } @@ -28,8 +28,8 @@ } RW_SECTION_A@0x52f000 0x98f000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x97efc0 - RW_FWID_A@0x98efc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x97efc0 + RW_FWID_A@0x98efc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd index 4ddcbc0..90e8e37 100644 --- a/src/mainboard/up/squared/vboot-roab.fmd +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -3,12 +3,12 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x503000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1ff800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 - GBB@0x800 0x40000 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1ff800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 + GBB@0x800% 0x40000 COREBOOT(CBFS)@0x40800 0x1bf000 } } @@ -28,13 +28,13 @@ } RW_SECTION_A@0x530000 0x4c7000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4b6fc0 - RW_FWID_A@0x4c6fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_A@0x4c6fc0% 0x40 } RW_SECTION_B@0x9f7000 0x4c7000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4b6fc0 - RW_FWID_B@0x4c6fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_B@0x4c6fc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Gerrit-Change-Number: 37317 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

6 8

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020