coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Nico Huber (Code Review) 27 Oct '20

27 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 22: Code-Review+1 I've confirmed that the spare bits are writable on APL. The emulated PM timer still runs at the nominal rate with them set to a random value. Will have a final look later. -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 22 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Oct 2020 17:25:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Correct sequence for gpio pad group
by Karthik Ramasubramanian (Code Review) 27 Oct '20

27 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct sequence for gpio pad group ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46842/2/src/soc/intel/jasperlake/g… File src/soc/intel/jasperlake/gpio.c: https://review.coreboot.org/c/coreboot/+/46842/2/src/soc/intel/jasperlake/g… PS2, Line 50: INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), I am still not sure how moving the reserved GPIOs help here. The GPIO Pad number defined in gpio_soc_defs.h has not changed. Hence the pad offset within the community or group is not going to change. Going through gpio_group_index function, it is just going to return the index to the gpio group within the community. This change will just return a different index to the same group. The pad offset within the group or the ACPI pad base will remain the same. -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 27 Oct 2020 16:48:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus: Disable XHCI LFPS power management by sku for garg
by Kevin Chiu (Code Review) 27 Oct '20

27 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46701 ) Change subject: mb/google/octopus: Disable XHCI LFPS power management by sku for garg ...................................................................... mb/google/octopus: Disable XHCI LFPS power management by sku for garg LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:171478764 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/octopus/variants/garg/overridetree.cb M src/mainboard/google/octopus/variants/garg/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46701/1 diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index f3c580d..971d0d8 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -192,4 +192,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 7c84f26..0a6574d 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <variant/sku.h> +#include <soc/intel/apollolake/chip.h> const char *mainboard_vbt_filename(void) { @@ -42,3 +43,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { + switch (google_chromeec_get_board_sku()) { + case SKU_17_LTE: + case SKU_18_LTE_TS: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e Gerrit-Change-Number: 46701 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/garg: fix LTE power sequence while DUT war...
by Kevin Chiu (Code Review) 27 Oct '20

27 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46022 ) Change subject: mb/google/octopus/variants/garg: fix LTE power sequence while DUT warmboot ...................................................................... mb/google/octopus/variants/garg: fix LTE power sequence while DUT warmboot related LTE GPIOs: GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L For DUT power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:167565015 BRANCH=master TEST=build and verify on the DUT with LTE Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/octopus/variants/garg/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46022/1 diff --git a/src/mainboard/google/octopus/variants/garg/Makefile.inc b/src/mainboard/google/octopus/variants/garg/Makefile.inc index ba865e9..7ee7e70 100644 --- a/src/mainboard/google/octopus/variants/garg/Makefile.inc +++ b/src/mainboard/google/octopus/variants/garg/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978 Gerrit-Change-Number: 46022 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Karthik Ramasubramanian (Code Review) 27 Oct '20

27 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45901 ) Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 13 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Oct 2020 16:13:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Allow configuring bus mastering for PCI bridges conditionally
by Felix Singer (Code Review) 27 Oct '20

27 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45150 ) Change subject: device: Allow configuring bus mastering for PCI bridges conditionally ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45150/4/src/device/Kconfig File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/45150/4/src/device/Kconfig@541 PS4, Line 541: Let coreboot configure bus mastering for PCI bridges. > Maybe extend with: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Gerrit-Change-Number: 45150 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Oct 2020 15:39:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Allow configuring bus mastering for PCI bridges conditionally
by Felix Singer (Code Review) 27 Oct '20

27 Oct '20

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45150 to look at the new patch set (#5). Change subject: device: Allow configuring bus mastering for PCI bridges conditionally ...................................................................... device: Allow configuring bus mastering for PCI bridges conditionally Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/device/Kconfig M src/device/pci_device.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45150/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Gerrit-Change-Number: 45150 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device: Rephrase bus master Kconfig option
by Nico Huber (Code Review) 27 Oct '20

27 Oct '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46341 ) Change subject: device: Rephrase bus master Kconfig option ...................................................................... device: Rephrase bus master Kconfig option Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index b69a254..cbe970f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -520,7 +520,7 @@ default y config PCI_ALLOW_BUS_MASTER - bool "Allow PCI bus master bit to be enabled by coreboot" + bool "Allow coreboot to set optional PCI bus master bits" default y help For security reasons, bus mastering should be enabled as late as -- To view, visit https://review.coreboot.org/c/coreboot/+/46341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40 Gerrit-Change-Number: 46341 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device: Allow configuring bus mastering for PCI bridges conditionally
by Nico Huber (Code Review) 27 Oct '20

27 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45150 ) Change subject: device: Allow configuring bus mastering for PCI bridges conditionally ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45150/4/src/device/Kconfig File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/45150/4/src/device/Kconfig@541 PS4, Line 541: Let coreboot configure bus mastering for PCI bridges. Maybe extend with: Enabling bus mastering for a PCI bridge also allows it to forward requests from downstream devices. Currently, payloads ignore this and only enable bus mastering for the downstream device. Hence, this option is needed for compatibility until payloads are fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/45150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Gerrit-Change-Number: 45150 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 27 Oct 2020 15:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device: Rework bus master option
by Nico Huber (Code Review) 27 Oct '20

27 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45149 ) Change subject: device: Rework bus master option ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33b37a79022007a16e97350db61575b63fa8256b Gerrit-Change-Number: 45149 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Oct 2020 15:31:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020