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Change in ...coreboot[master]: Include required files to compile in postcar to skip ramstage
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32675 Change subject: Include required files to compile in postcar to skip ramstage ...................................................................... Include required files to compile in postcar to skip ramstage Change-Id: I5269d562baf8f216e17794ffceb8f97061483515 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc A src/arch/x86/c_postcar_start.S M src/arch/x86/exit_car.S M src/commonlib/Makefile.inc M src/cpu/intel/microcode/Makefile.inc M src/cpu/intel/turbo/Makefile.inc M src/cpu/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/name/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/device/Makefile.inc M src/drivers/elog/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/ppi/Makefile.inc M src/drivers/intel/gma/Makefile.inc M src/drivers/mrc_cache/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/ec/google/chromeec/Makefile.inc M src/lib/Makefile.inc M src/security/vboot/Makefile.inc M src/soc/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Makefile.inc 23 files changed, 378 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32675/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6e4ee76..63e84ca 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -283,6 +283,20 @@ postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c +postcar-y += c_postcar_start.S +postcar-y += cpu.c +postcar-$(CONFIG_IOAPIC) += ioapic.c +postcar-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +postcar-y += tables.c +postcar-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S +endif + LDFLAGS_postcar += -Map $(objcbfs)/postcar.map $(objcbfs)/postcar.debug: $$(postcar-objs) diff --git a/src/arch/x86/c_postcar_start.S b/src/arch/x86/c_postcar_start.S new file mode 100644 index 0000000..70c38b5 --- /dev/null +++ b/src/arch/x86/c_postcar_start.S @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/post_code.h> + +/* Place the stack in the bss section. It's not necessary to define it in the + * the linker script. */ + .section .bss, "aw", @nobits +.global _stack +.global _estack + +/* Stack alignment is not enforced with rmodule loader, reserve one + * extra CPU such that alignment can be enforced on entry. */ +.align CONFIG_STACK_SIZE +_stack: +.space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE +_estack: +#if CONFIG(COOP_MULTITASKING) +.global thread_stacks +thread_stacks: +.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS +#endif + + .section ".text._start", "ax", @progbits +#ifdef __x86_64__ + .code64 +#else + .code32 +#endif + .globl cstart +cstart: + cli + lgdt %cs:gdtaddr +#ifndef __x86_64__ + ljmp $0x10, $1f +#endif +1: movl $0x18, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs +#ifdef __x86_64__ + mov $0x48, %ecx + call SetCodeSelector +#endif + + post_code(POST_ENTRY_C_START) /* post 13 */ + + cld + + /** poison the stack. Code should not count on the + * stack being full of zeros. This stack poisoning + * recently uncovered a bug in the broadcast SIPI + * code. + */ + leal _stack, %edi + movl $_estack, %ecx + subl %edi, %ecx + shrl $2, %ecx /* it is 32 bit aligned, right? */ + movl $0xDEADBEEF, %eax + rep + stosl + + /* Set new stack with enforced alignment. */ + movl $_estack, %esp + andl $(~(CONFIG_STACK_SIZE-1)), %esp + +#if CONFIG(COOP_MULTITASKING) + /* Push the thread pointer. */ + push $0 +#endif + /* Push the CPU index and struct CPU */ + push $0 + push $0 + + /* + * Now we are finished. Memory is up, data is copied and + * bss is cleared. Now we call the main routine and + * let it do the rest. + */ + post_code(POST_PRE_HARDWAREMAIN) /* post fe */ + + andl $0xFFFFFFF0, %esp + + call main + /* NOTREACHED */ +.Lhlt: + post_code(POST_DEAD_CODE) /* post ee */ + hlt + jmp .Lhlt + + .globl gdt, gdt_end + +gdtaddr: + .word gdt_end - gdt - 1 +#ifdef __x86_64__ + .quad gdt +#else + .long gdt /* we know the offset */ +#endif + + .data + + /* This is the gdt for GCC part of coreboot. + * It is different from the gdt in ROMCC/ASM part of coreboot + * which is defined in entry32.inc + * + * When the machine is initially started, we use a very simple + * gdt from ROM (that in entry32.inc) which only contains those + * entries we need for protected mode. + * + * When we're executing code from RAM, we want to do more complex + * stuff, like initializing PCI option ROMs in real mode, or doing + * a resume from a suspend to RAM. + */ +gdt: + /* selgdt 0, unused */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 8, unused */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 0x10, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for + * limit + */ + + /* selgdt 0x18, flat data segment */ + .word 0xffff, 0x0000 +#ifdef __x86_64__ + .byte 0x00, 0x92, 0xcf, 0x00 +#else + .byte 0x00, 0x93, 0xcf, 0x00 +#endif + + /* selgdt 0x20, unused */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x00, 0x00, 0x00 + + /* The next two entries are used for executing VGA option ROMs */ + + /* selgdt 0x28 16 bit 64k code at 0x00000000 */ + .word 0xffff, 0x0000 + .byte 0, 0x9a, 0, 0 + + /* selgdt 0x30 16 bit 64k data at 0x00000000 */ + .word 0xffff, 0x0000 + .byte 0, 0x92, 0, 0 + + /* The next two entries are used for ACPI S3 RESUME */ + + /* selgdt 0x38, flat data segment 16 bit */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for + * limit + */ + + /* selgdt 0x40, flat code segment 16 bit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for + * limit + */ + +#ifdef __x86_64__ + /* selgdt 0x48, flat x64 code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 +#endif +gdt_end: + + .section ".text._start", "ax", @progbits +#ifdef __x86_64__ +SetCodeSelector: + # save rsp because iret will align it to a 16 byte boundary + mov %rsp, %rdx + + # use iret to jump to a 64-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov %ss, %ax # need to push ss.. + push %rax # push ss instuction not valid in x64 mode, + # so use ax + push %rsp + pushfq + push %rcx # cx is code segment selector from caller + mov $setCodeSelectorLongJump, %rax + push %rax + + # the iret will continue at next instruction, with the new cs value + # loaded + iretq + +setCodeSelectorLongJump: + # restore rsp, it might not have been 16-byte aligned on entry + mov %rdx, %rsp + ret + + .previous +.code64 +#else + .previous +.code32 +#endif diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 769a758..234c716 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -126,6 +126,9 @@ /* Align stack to 16 bytes at call instruction. */ andl $0xfffffff0, %esp +#if CONFIG(SKIP_RAMSTAGE) + call cstart +#endif /* Call into main for postcar. */ call main /* Should never return. */ diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index b6e8913..1865be5 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -38,3 +38,8 @@ postcar-y += lz4_wrapper.c ramstage-y += sort.c + +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +postcar-y += sort.c +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5e..922d340 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -3,3 +3,6 @@ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +endif \ No newline at end of file diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc index 48ec55d..68b46c7 100644 --- a/src/cpu/intel/turbo/Makefile.inc +++ b/src/cpu/intel/turbo/Makefile.inc @@ -1 +1,2 @@ +postcar-$(CONFIG_SKIP_RAMSTAGE) += turbo.c ramstage-y += turbo.c diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a664..e68f21e 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -37,3 +37,29 @@ $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_PARALLEL_MP) += mp_init.c +postcar-y += backup_default_smm.c + +ifeq ($(CONFIG_PARALLEL_MP),y) +postcar-srcs += $(SIPI_BIN).manual +endif +rmodules_$(ARCH-postcar-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-postcar-y),src/cpu/x86/sipi_vector.S) + $(CC_rmodules_$(ARCH-postcar-y)) $(CFLAGS_rmodules_$(ARCH-postcar-y)) -nostdlib -r -o $@ $^ + +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) +endif + +$(SIPI_BIN): $(SIPI_RMOD) + $(OBJCOPY_postcar) -O binary $< $@ + +$(call src-to-obj,postcar,$(SIPI_BIN).manual): $(SIPI_BIN) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-postcar-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +endif diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..a6a59c7 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += lapic.c +postcar-$(CONFIG_SKIP_RAMSTAGE) += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..47ba4c2 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += mtrr.c +postcar-$(CONFIG_SKIP_RAMSTAGE) += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 5dba1a2..e1515496 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += name.c +postcar-$(CONFIG_SKIP_RAMSTAGE) += name.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..7bcd10e 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -14,10 +14,16 @@ ## ramstage-y += smm_module_loader.c +postcar-$(CONFIG_SKIP_RAMSTAGE) += smm_module_loader.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) $(eval $(call create_class_compiler,smmstub,x86_32)) +#if CONFIG(SKIP_RAMSTAGE) +else ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call create_class_compiler,smm,x86_32)) +$(eval $(call create_class_compiler,smmstub,x86_32)) +#endif else $(eval $(call create_class_compiler,smm,x86_64)) $(eval $(call create_class_compiler,smmstub,x86_64)) @@ -36,6 +42,12 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +endif + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -45,6 +57,11 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smmstub.manual +endif + # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) @@ -53,6 +70,10 @@ # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) +#if CONFIG(SKIP_RAMSTAGE) +else ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) +#endif else $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) endif @@ -64,10 +85,20 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +endif + # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +#if CONFIG(SKIP_RAMSTAGE) +else ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +#endif else $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif @@ -84,6 +115,9 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual +endif endif smm-y += smmhandler.S diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index baa45be..90c814d 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -7,6 +7,13 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-y += smbus_ops.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-y += device.c +postcar-y += root_device.c +postcar-y += cpu_device.c +postcar-y += device_util.c +endif + ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif @@ -22,7 +29,16 @@ bootblock-y += pci_early.c verstage-y += pci_early.c romstage-y += pci_early.c + +ifneq ($(CONFIG_SKIP_RAMSTAGE),y) postcar-y += pci_early.c +else +postcar-y += pci_device.c +postcar-y += pci_rom.c +postcar-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c +postcar-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c +postcar-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c +endif ramstage-y += pci_class.c ramstage-y += pci_device.c diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..fcf995f 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,11 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c +ifneq ($(CONFIG_SKIP_RAMSTAGE),y) postcar-$(CONFIG_ELOG_PRERAM) += elog.c +else +postcar-$(CONFIG_ELOG) += elog.c +endif ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d627a3d..b363214 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -39,6 +39,13 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_RUN_FSP_GOP) += graphics.c +postcar-y += silicon_init.c +postcar-y += util.c +postcar-y += debug.c +endif + postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc index 67c4966..dc75f29 100644 --- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc +++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc @@ -13,4 +13,7 @@ # GNU General Public License for more details. # +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c +endif ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index e128ad6..3a6af8b 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -20,7 +20,9 @@ endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c - +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_INTEL_GMA_ACPI) += opregion.c +endif # add_vbt_to_cbfs, first argument is the filename in cbfs, the second one # is the filename in the coreboot tree. add_vbt_to_cbfs= \ diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc index 0d226fe..a58285f 100644 --- a/src/drivers/mrc_cache/Makefile.inc +++ b/src/drivers/mrc_cache/Makefile.inc @@ -1,2 +1,5 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +endif ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e3..86dcd94 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) +postcar-$(CONFIG_SKIP_RAMSTAGE) += isa-dma.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 4593c73..44b5eb8 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -34,6 +34,12 @@ romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-y += ec.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c +endif + CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec # These are Chrome EC firmware images that a payload (such as depthcharge) can diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..6a1b5c1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -165,6 +165,18 @@ postcar-y += imd_cbmem.c postcar-y += imd.c postcar-y += romstage_handoff.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-y += region_file.c +postcar-y += selfboot.c +postcar-y += coreboot_table.c +postcar-y += bootmem.c +postcar-y += malloc.c +postcar-y += fallback_boot.c +postcar-y += compute_ip_checksum.c +postcar-y += stack.c +postcar-y += wrdd.c +postcar-y += memrange.c +endif bootblock-y += hexdump.c ramstage-y += hexdump.c diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6d2096d..f4217ba 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -47,6 +47,13 @@ romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-y += gbb.c +postcar-y += vbnv.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +endif + bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c verstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c romstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..9d131a3 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -21,6 +21,11 @@ ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +postcar-y += vbt.c +endif + bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c verstage-$(CONFIG_TPM_CR50) += tpm_tis.c romstage-$(CONFIG_TPM_CR50) += tpm_tis.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..5b72336 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -13,6 +13,12 @@ ## GNU General Public License for more details. ## +ifeq ($(CONFIG_SKIP_RAMSTAGE),y) +postcar-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c +endif + ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -- To view, visit https://review.coreboot.org/c/coreboot/+/32675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5269d562baf8f216e17794ffceb8f97061483515 Gerrit-Change-Number: 32675 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src/drivers/intel/fsp1_0: add option to specify MRC and ucode location
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30752 Change subject: src/drivers/intel/fsp1_0: add option to specify MRC and ucode location ...................................................................... src/drivers/intel/fsp1_0: add option to specify MRC and ucode location Change aims to give better control over CBFS content on FSP1.0 boards. Specifying location of MRC cache and microcode will allow to save more space in CBFS. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I23e4e43bdddd7836ef74a2831e631d77599cdcca --- M src/drivers/intel/fsp1_0/Kconfig M src/drivers/intel/fsp1_0/Makefile.inc 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30752/1 diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index c7f6c18..6044c0e 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -89,6 +89,19 @@ should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in. +config MRC_CACHE_LOC + hex "MRC cache location in CBFS" + depends on ENABLE_MRC_CACHE && !MRC_CACHE_FMAP + help + Define the location of MRC cache data in CBFS. + +config CPU_MICROCODE_CBFS_LOC + hex "Microcode update base address in CBFS" + depends on CPU_MICROCODE_CBFS_GENERATE || CPU_MICROCODE_CBFS_EXTERNAL_HEADER + help + The location (base address) in CBFS that contains the + microcode update binary. + config VIRTUAL_ROM_SIZE hex "Virtual ROM Size" default ROM_SIZE diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 67741a9..4936022 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -44,6 +44,9 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache +ifneq ($(CONFIG_MRC_CACHE_LOC),) +mrc.cache-COREBOOT-position := $(CONFIG_MRC_CACHE_LOC) +endif endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23e4e43bdddd7836ef74a2831e631d77599cdcca Gerrit-Change-Number: 30752 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: [WIP]drivers/fsp1.0: Use common code for to save fastboot data
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30792 Change subject: [WIP]drivers/fsp1.0: Use common code for to save fastboot data ...................................................................... [WIP]drivers/fsp1.0: Use common code for to save fastboot data Change-Id: Ie8c355687d3d691ae4e3ca179b0b063598ff5ac2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_0/Kconfig M src/drivers/intel/fsp1_0/Makefile.inc D src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/vendorcode/intel/Makefile.inc 11 files changed, 61 insertions(+), 425 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/30792/1 diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 4d1c4df..fa1b4c8 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -61,57 +61,12 @@ config ENABLE_FSP_FAST_BOOT bool "Enable Fast Boot" - select ENABLE_MRC_CACHE default n help Enabling this feature will force the MRC data to be cached in NV storage to be used for speeding up boot time on future reboots and/or power cycles. -config ENABLE_MRC_CACHE - bool - default y if HAVE_ACPI_RESUME - default n - help - Enabling this feature will cause MRC data to be cached in NV storage. - This can either be used for fast boot, or just because the FSP wants - it to be saved. - -config MRC_CACHE_FMAP - bool "Use MRC Cache in FMAP" - depends on ENABLE_MRC_CACHE - default n - help - Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS. - You must define a region in your FMAP named "RW_MRC_CACHE". - -config MRC_CACHE_SIZE - hex "Fast Boot Data Cache Size" - default 0x10000 - depends on ENABLE_MRC_CACHE - depends on !MRC_CACHE_FMAP - help - This is the amount of space in NV storage that is reserved for the - fast boot data cache storage. - - WARNING: Because this area will be erased and re-written, the size - should be a full sector of the flash ROM chip and nothing else should - be included in CBFS in any sector that the fast boot cache data is in. - -config VIRTUAL_ROM_SIZE - hex "Virtual ROM Size" - default ROM_SIZE - depends on ENABLE_MRC_CACHE - help - This is used to calculate the offset of the MRC data cache in NV - Storage for fast boot. If in doubt, leave this set to the default - which sets the virtual size equal to the ROM size. - - Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are - loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When - the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM - size is 16 MB. - config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 67741a9..5580a8b7 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -18,9 +18,6 @@ ramstage-y += fsp_util.c hob.c romstage-y += fsp_util.c hob.c -ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c - CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc @@ -33,18 +30,4 @@ fsp.bin-options := --xip endif -ifeq ($(CONFIG_ENABLE_MRC_CACHE),y) -ifneq ($(CONFIG_MRC_CACHE_FMAP),y) -$(obj)/mrc.cache: - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache -endif -endif - endif diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c deleted file mode 100644 index 76241c8..0000000 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <device/device.h> -#include <cbmem.h> -#include <spi-generic.h> -#include <spi_flash.h> -#include <lib.h> // hexdump -#include "fsp_util.h" - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size; - - if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) { - struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - *mrc_region_ptr = rdev_mmap_full(&rdev); - return region_device_sz(&rdev); - } - *mrc_region_ptr = NULL; - return 0; - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - - return region_size; - } -} - -/* - * Find the largest index block in the MRC cache. Return NULL if none is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ -#if !defined(__PRE_RAM__) -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - u32 mrc_data_size = mrc_cache->mrc_data_size; - - mrc_cache = next_mrc_block(mrc_cache); - if (((u32)mrc_cache + mrc_data_size) >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating fast boot cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - struct spi_flash flash; - - if (!current) { - printk(BIOS_ERR, "No fast boot cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "Fast boot cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find fast boot cache area\n", - __func__); - return; - } - - /* - * we need to: - * 0. compare MRC data to last mrc-cache block (exit if same) - */ - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - /* 1. use spi_flash_probe() to find the flash, then... */ - spi_init(); - if (spi_flash_probe(0, 0, &flash)) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - /* 2. look up the first unused block */ - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - spi_flash_erase(&flash, to_flash_offset(cache_base), - cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - /* 4. write mrc data with spi_flash_write() */ - printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", - cache); - spi_flash_write(&flash, to_flash_offset(cache), - current->mrc_data_size + sizeof(*current), current); -} - -#endif /* !defined(__PRE_RAM__) */ - -void *find_and_set_fastboot_cache(void) -{ - struct mrc_data_container *mrc_cache = NULL; - if (((mrc_cache = find_current_mrc_cache()) == NULL) || - (mrc_cache->mrc_data_size == -1UL)) { - printk(BIOS_DEBUG, "FSP MRC cache not present.\n"); - return NULL; - } - printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache); - printk(BIOS_SPEW, "Saved MRC data:\n"); - hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4); - return (void *) mrc_cache->mrc_data; -} - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find fast boot cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - * 0. compare MRC data to last mrc-cache block (exit if same) - */ - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 71f6416..7253a56 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -23,6 +23,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <cpu/intel/microcode.h> +#include <mrc_cache.h> #ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ @@ -213,6 +214,38 @@ } #endif /* FSP_RESERVE_MEMORY_SIZE */ +#if defined(__ROMSTAGE__) +/** + * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM + */ +enum cb_err save_mrc_data(void *hob_start, uint32_t version) +{ + u32 *mrc_hob; + u32 *mrc_hob_data; + u32 mrc_hob_size; + int output_len; + const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + + mrc_hob = GetNextGuidHob(&mrc_guid, hob_start); + if (mrc_hob == NULL){ + printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n"); + return CB_ERR; + } + + mrc_hob_data = GET_GUID_HOB_DATA(mrc_hob); + mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob); + + printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n", + (void *)mrc_hob_data, mrc_hob_size); + + output_len = ALIGN(mrc_hob_size, 16); + + return mrc_cache_stash_data(MRC_TRAINING_DATA, version, mrc_hob_data, + mrc_hob_size); +} +#endif + + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { @@ -237,86 +270,6 @@ (u8)(fsp_header_ptr->ImageRevision & 0xff)); } - -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) -/** - * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM - */ -int save_mrc_data(void *hob_start) -{ - u32 *mrc_hob; - u32 *mrc_hob_data; - u32 mrc_hob_size; - struct mrc_data_container *mrc_data; - int output_len; - const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - - mrc_hob = GetNextGuidHob(&mrc_guid, hob_start); - if (mrc_hob == NULL){ - printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n"); - return(0); - } - - mrc_hob_data = GET_GUID_HOB_DATA (mrc_hob); - mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob); - - printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n", - (void *)mrc_hob_data, mrc_hob_size); - - output_len = ALIGN(mrc_hob_size, 16); - - /* Save the MRC S3/fast boot/ADR restore data to cbmem */ - mrc_data = cbmem_add (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); - - /* Just return if there was a problem with getting CBMEM */ - if (mrc_data == NULL) { - printk(BIOS_WARNING, "CBMEM was not available to save the fast boot cache data.\n"); - return 0; - } - - printk(BIOS_DEBUG, "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n", - (void *)mrc_hob_data, mrc_data, output_len); - - mrc_data->mrc_signature = MRC_DATA_SIGNATURE; - mrc_data->mrc_data_size = output_len; - mrc_data->reserved = 0; - memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size); - - /* Zero the unused space in aligned buffer. */ - if (output_len > mrc_hob_size) - memset((mrc_data->mrc_data + mrc_hob_size), 0, - output_len - mrc_hob_size); - - mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data, - mrc_data->mrc_data_size); - - printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n"); - hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); - return (1); -} -#endif /* CONFIG_ENABLE_MRC_CACHE */ - -static void find_fsp_hob_update_mrc(void *unused) -{ - /* Set the global HOB list pointer */ - FspHobListPtr = (void *)*((u32 *) cbmem_find(CBMEM_ID_HOB_POINTER)); - - if (!FspHobListPtr){ - printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n"); - } else { - /* 0x0000: Print all types */ - print_hob_type_structure(0x000, FspHobListPtr); - - #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) - if (save_mrc_data(FspHobListPtr)) - update_mrc_cache(NULL); - else - printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - #endif - } -} - /** @brief Notify FSP for PostPciEnumeration * * @param unused @@ -348,7 +301,4 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); -/* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index d5d0160..b960158 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -19,10 +19,7 @@ #include <chipset_fsp_util.h> #include "fsp_values.h" -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) -int save_mrc_data(void *hob_start); -void *find_and_set_fastboot_cache(void); -#endif +enum cb_err save_mrc_data(void *hob_start, uint32_t version); volatile u8 *find_fsp(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); @@ -75,10 +72,6 @@ struct mrc_data_container *find_current_mrc_cache(void); -#if !defined(__PRE_RAM__) -void update_mrc_cache(void *unused); -#endif - #endif /* The offset in bytes from the start of the info structure */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig index 67ed66b..30fc94f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig @@ -18,7 +18,6 @@ select PLATFORM_USES_FSP1_0 select USE_GENERIC_FSP_CAR_INC select FSP_USES_UPD - select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data config FSP_FILE string diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 7977575..03c51b3 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <include/mrc_cache.h> #include <fspvpd.h> #include <fspbootmode.h> #include "../chip.h" @@ -160,9 +161,11 @@ pFspInitParams->NvsBufferPtr = NULL; pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; - /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); - + struct region_device rdev; + if (mrc_cache_get_current(MRC_TRAINING_DATA, 1, &rdev)) { + /* Find the fastboot cache that was saved in the ROM */ + pFspInitParams->NvsBufferPtr = rdev_mmap_full(&rdev); + } return; } diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 3786c0c..99f9548 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -24,6 +24,7 @@ #include <device/pci_def.h> #include <soc/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <include/mrc_cache.h> #include "../chip.h" #include <arch/io.h> #include <soc/pmc.h> @@ -307,10 +308,13 @@ ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) - /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif + if (IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)) { + struct region_device rdev; + if (mrc_cache_get_current(MRC_TRAINING_DATA, 1, &rdev)) { + /* Find the fastboot cache that was saved in the ROM */ + pFspInitParams->NvsBufferPtr = rdev_mmap_full(&rdev); + } + } if (prev_sleep_state == ACPI_S3) { /* S3 resume */ diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 800f686..3de1cea 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -24,6 +24,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <include/mrc_cache.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <chip.h> @@ -128,11 +129,13 @@ ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) - /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif - + if (IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)) { + struct region_device rdev; + if (mrc_cache_get_current(MRC_TRAINING_DATA, 1, &rdev)) { + /* Find the fastboot cache that was saved in the ROM */ + pFspInitParams->NvsBufferPtr = rdev_mmap_full(&rdev); + } + } return; } diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 003ae22..590aec8 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -117,12 +117,15 @@ post_code(0x4d); cbmem_was_initted = !cbmem_recovery(0); - /* Save the HOB pointer in CBMEM to be used in ramstage*/ + /* Save the HOB pointer in CBMEM to be used in ramstage */ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); if (cbmem_hob_ptr == NULL) die("Could not allocate cbmem for HOB pointer"); *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; +#define MRC_CACHE_VERSION 1 /* TODO fetch FSP version */ + save_mrc_data(cbmem_hob_ptr, 1); + /* Load the ramstage. */ post_code(0x4e); run_ramstage(); diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 33b2f81..9543756 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -18,6 +18,7 @@ FSP_PATH := $(call strip_quotes,$(CONFIG_FSP_VENDORCODE_HEADER_PATH)) FSP_SRC_FILES := $(wildcard src/vendorcode/intel/$(FSP_PATH)/srx/*.c) FSP_C_INPUTS := $(foreach file, $(FSP_SRC_FILES), $(FSP_PATH)/srx/$(notdir $(file))) +romstage-y += $(FSP_C_INPUTS) ramstage-y += $(FSP_C_INPUTS) CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include -- To view, visit https://review.coreboot.org/c/coreboot/+/30792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8c355687d3d691ae4e3ca179b0b063598ff5ac2 Gerrit-Change-Number: 30792 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: Documentation: Explain SimpleELF
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33447 Change subject: Documentation: Explain SimpleELF ...................................................................... Documentation: Explain SimpleELF Explain coreboot's SELF format. Change-Id: Ia217af7d39505393ed9324fbe53b4ca7f3069e2e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/lib/payloads/index.md A Documentation/lib/payloads/selfboot.md M Documentation/payloads.md 3 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33447/1 diff --git a/Documentation/lib/payloads/index.md b/Documentation/lib/payloads/index.md index 44daef1..b8eca8c 100644 --- a/Documentation/lib/payloads/index.md +++ b/Documentation/lib/payloads/index.md @@ -6,6 +6,10 @@ coreboot supports multiple payloads, depending on the architecture of the selected mainboard. +## SimpleELF + +- [SimpleELF format](selfboot.md) + ## FIT - [uImage.FIT support](fit.md) diff --git a/Documentation/lib/payloads/selfboot.md b/Documentation/lib/payloads/selfboot.md new file mode 100644 index 0000000..62a4393 --- /dev/null +++ b/Documentation/lib/payloads/selfboot.md @@ -0,0 +1,28 @@ +# Simple ELF standard + +coreboot is able to use static linked ELF binaries as payload. +To reduce complexity the ELF binaries are converted to coreboot's SimpleELF +(SELF) format. +The payload is therefore split into multiple sections by `cbfstool` at +build time, each having a unique loading address and possible compression. + +## SELF loader +The SELF loader implementation can be found in `src/lib/selfboot.c`. +It decompresses the SELF sections and places them in memory. + +If the payload overlaps with the loading stage (*RAMSTAGE*) and +`CONFIG_RELOCATABLE_RAMSTAGE` is selected, the loading stage is moved to another +location in RAM. + +SELF payloads are **never** relocatable and will always be placed at the +address they specify. If it's not possible to load the payload at the specified +address, the system won't boot. + +### Calling conventions +The SELF payload is called with a pointer to the coreboot tables as first +argument. + +**Note:** The only exception is made on [RISC-V] which does use the *HARTID* +and a pointer to the *FDT* as arguments. + +[RISC-V]: ../../arch/riscv/index.md diff --git a/Documentation/payloads.md b/Documentation/payloads.md index b1eae61..650818e 100644 --- a/Documentation/payloads.md +++ b/Documentation/payloads.md @@ -7,6 +7,12 @@ There is various software in that space that is either explicitly written as payload or can be made to work as one. +## ELF + +Executable and linking format (ELF) compatible static linked binaries can be +loaded as payload. +ELF binaries are loaded through the [SELF] boot mechanism. + ## SeaBIOS [SeaBIOS](https://www.seabios.org) is an open source implementation of @@ -14,6 +20,7 @@ since. While originally written for emulators such as QEMU, it can be made to work as a coreboot payload and all the necessary code is in SeaBIOS' mainline code. +SeaBIOS is loaded through the [SELF] boot mechanism. ## Tianocore @@ -40,3 +47,8 @@ firmware project drivers that often reinvent the wheel) and the ability to define boot policy with familiar tools, no matter if those are shell scripts or compiled userland programs written in C, Go or other programming languages. + +On x86 platforms Linux is loaded through the [SELF] boot mechanism, by adding a +*tampoline code* at the start of the kernel. + +[SELF]: lib/payloads/selfboot.md -- To view, visit https://review.coreboot.org/c/coreboot/+/33447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia217af7d39505393ed9324fbe53b4ca7f3069e2e Gerrit-Change-Number: 33447 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 12

Change in coreboot[master]: vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redun...
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36001 ) Change subject: vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redundant FIS code ...................................................................... vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redundant FIS code From looking at neighboring code, disabling FIS based switching appears intentional, possibly due to errata. Clean and comment code so it is apparent. Change-Id: I4529716e951a9e7b63bdee11611dd78f2d41b464 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> --- M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c 1 file changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36001/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c index 9f526d8..293ea57 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c @@ -367,11 +367,8 @@ AndMaskDword |= BIT12; } - if ( FchSataFisBasedSwitching ) { - AndMaskDword |= BIT10; - } else { - AndMaskDword |= BIT10; - } + // FchSataFisBasedSwitching + AndMaskDword |= BIT10; if ( FchSataAggrLinkPmCap ) { OrMaskDword |= BIT11; @@ -431,11 +428,8 @@ RwMem ((Bar5 + 0x0FC), AccessWidth32, (UINT32)~(BIT20), 0x00); } - if ( FchSataFisBasedSwitching ) { - RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00); - } else { - RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00); - } + // FchSataFisBasedSwitching + RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00); if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) { RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, BIT0); -- To view, visit https://review.coreboot.org/c/coreboot/+/36001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4529716e951a9e7b63bdee11611dd78f2d41b464 Gerrit-Change-Number: 36001 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [WIP]Documentation: Add Intel microcode update mechanism
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36539 ) Change subject: [WIP]Documentation: Add Intel microcode update mechanism ...................................................................... [WIP]Documentation: Add Intel microcode update mechanism Document microcode updates and how secure microcode updates are done in GNU/Linux. Propose how to do microcode updates in coreboot. Change-Id: I78350fc81cb0de7b0b2d9cbd8537e6b3815916c0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/microcode/index.md 2 files changed, 111 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36539/1 diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index f30ff9a..1cf8548 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -2,6 +2,10 @@ This section contains documentation about coreboot on specific Intel SOCs. +## Common + +- [Microcode updates](microcode/index.md) + ## Platforms - [Common code development strategy](code_development_model/code_development_model.md) diff --git a/Documentation/soc/intel/microcode/index.md b/Documentation/soc/intel/microcode/index.md new file mode 100644 index 0000000..b7f5949 --- /dev/null +++ b/Documentation/soc/intel/microcode/index.md @@ -0,0 +1,107 @@ +# Microcode updates on Intel CPUs + +## What are microcodes? + +```eval_rst +Microcode is a computer hardware technique that interposes a layer of +organisation between the CPU hardware and the programmer-visible +instruction set architecture of the computer. [#1]_ +``` + +In coreboot the microcode updates are stored in files in the CBFS and +are used to update the CPU microcode at runtime using a special instruction. + +## How does a microcode update look like? + +The microcode update is a binary provided by Intel consisting out of +a header and data. +The header holds the processor signature for which the update is +intented and additional metadata. +For detailed information check the [Intel SDM] 253668-060US Chapter 9.11.1 + +## When are mirocode updates done? + +Microcode updates are stored in the CPU's SRAM and thus needs to be loaded +after a hard reset. However loading microcode updates is done multiple times +in coreboot's boot sequence. + +On some CPUs it's neccessary to do an microcode update before: +* Cache-As-RAM is enabled +* Legacy Intel TXT FIT boot is run +* MultiProcessor-Init is run + +On some CPUs it's neccessary to do an microcode update after: +* SMM setup was done +* SGX setup was done + +## How to do microcode updates? + +The following chapter is based multiple sources and testing due to lack of clear +documentation. + +In order to safely update microcode on any generation the GNU/Linux kernel +"late loading mechanism" takes a conservative approach and obeys the following +rules: + +```eval_rst +* All physical CPU cores must be updated with the same microcode version [#2]_ +* Caches need to be flushed on certain CPUs prior to microcode update [#3]_ +* The sibling thread must be idle while a microcode update is ongoing [#4]_ +* All other APs on the same package should be idle (or in Wait-for-SIPI) [#5]_ +* The microcode update is done sequentially [#6]_ +``` + +The downside of this approach is that it's very slow. + +It seems to be possible to run microcode updates in parallel on APs on specific +CPUs. + +## How to do microcode updates in coreboot ramstage? + +*TBD* + +Proposal: +1. Run microcode update sequential by default +2. Flush caches in non CAR environment before running a microcode update +3. Switch to parallel microcode update after extensive testing (10000 boot cycles) + +For parallel microcde update: +1. On Intel HT enabled CPUs spinlock the slibing thread of a logical core +2. On Intel HT enabled CPUs only update one thread of a physical core +3. Synchronize microcode loading. This will make sure no other computational work + is being done while an update occurs (thus no Wait-for-SIPI). + +## Intel Hyper-Threading enabled CPUs + +```eval_rst +According to Intel SDM a Hyper-Threading enabled core shares the microcode unit +between the logical CPU cores [#4]_. Intel NetBurst CPUs must not attempt to +update the microcode on both logical cores at the same time, this is safe for +newer CPU generations. +``` + +## Where to obtain the microcode updates? + +The microcode update files can be found on Intel's [Github Microcode]. + +## References +- [Wikipedia microcode] +- [Github Microcode] +- [Intel SDM] + +------------- +```eval_rst +.. [#1] Kent, Allen; Williams, James G. (April 5, 1993). `Encyclopedia of Computer Science and Technology: Volume 28 <http://https://books.google.com/books?id=EjWV8J8CQEYC>`_ +.. [#2] `Intel SDM Document 253668-060US`_ Chapter 9.11.6.3 "Update in a System Supporting Intel Hyper-Threading Technology" +.. [#3] GNU/Linux commit by Ashok Raj `<https://lore.kernel.org/patchwork/patch/890717/>`_ +.. [#4] `Intel SDM Document 253668-060US`_ Chapter 8.8.5 "Microcode Update Resources" +.. [#5] GNU/Linux commit by Ashok Raj `<https://lore.kernel.org/patchwork/patch/890713/>`_ +.. [#6] `Intel SDM Document 253668-060US`_ Chapter 9.11.6.3 "Update in a System Supporting Intel Hyper-Threading Technology" + +.. _Intel SDM Document 253668-060US: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-… + +``` + +[Wikipedia microcode]: https://en.wikipedia.org/wiki/Microcode +[Github Microcode]: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files +[Intel SDM]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-… -- To view, visit https://review.coreboot.org/c/coreboot/+/36539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78350fc81cb0de7b0b2d9cbd8537e6b3815916c0 Gerrit-Change-Number: 36539 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: lib.h: Add convenient memcpy() variants
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32740 Change subject: lib.h: Add convenient memcpy() variants ...................................................................... lib.h: Add convenient memcpy() variants Add two macros that should help in cases where the arguments are objects (not pointers) and the count of bytes to be copied is the size of one of them (or both). * memcpy_dlen(dst, src) copies `sizeof(dst)` bytes (destination length). * memcpy_elen(dst, src) asserts that both sizes match and copies as many bytes (equal length). Change-Id: I2b23066b3bcc29ff679e620f723ce1da5057aa03 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/lib.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32740/1 diff --git a/src/include/lib.h b/src/include/lib.h index 098d62d..6cbe6f3 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -18,6 +18,7 @@ #ifndef __LIB_H__ #define __LIB_H__ #include <stdint.h> +#include <string.h> #include <types.h> /* Defined in src/lib/lzma.c. Returns decompressed size or 0 on error. */ @@ -69,4 +70,18 @@ /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +/* memcpy destination length (memcpy_dlen) copies `sizeof(dst)` bytes. */ +#define memcpy_dlen(dst, src) memcpy(dst, src, sizeof(dst)) + +/* + * memcpy equal length (memcpy_elen) + * Asserts that both objects `dst` and `src` + * have the same size and copies as many bytes. + */ +#define memcpy_elen(dst, src) do { \ + _Static_assert(sizeof(dst) == sizeof(src), \ + "`dst` and `src` need equal length!"); \ + memcpy_dlen(dst, src); \ +} while (0) + #endif /* __LIB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b23066b3bcc29ff679e620f723ce1da5057aa03 Gerrit-Change-Number: 32740 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: WIP: Add complete board list with libre/blobby status
by Damien Zammit (Code Review) 07 Aug '23

07 Aug '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32237 Change subject: WIP: Add complete board list with libre/blobby status ...................................................................... WIP: Add complete board list with libre/blobby status Please comment on the list so we can remove the third '?' category Change-Id: I526b453ca30d8bcb6a55b40f4e53c6852f7cf4c7 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A Documentation/libre-boards.csv 1 file changed, 219 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32237/1 diff --git a/Documentation/libre-boards.csv b/Documentation/libre-boards.csv new file mode 100644 index 0000000..94c87ca --- /dev/null +++ b/Documentation/libre-boards.csv @@ -0,0 +1,219 @@ +Manufacturer/Model,Fully libre?,Reason for exclusion +amd/samba,?,Should be deleted from tree +cavium/cn8100_sff_evb,?,cavium +cubietech/cubieboard,?, +google/cheza,?,Qualcomm +google/daisy,?,Exynos +google/foster,?,Nvidia Tegra210 +google/gale,?,Qualcomm +google/gru,?,RockChip rk3399 +google/kukui,?,Mediatek mt8183 soc +google/mistral,?,Qualcomm +google/nyan,?,Nvidia Tegra124 +google/nyan_big,?,Nvidia Tegra124 +google/nyan_blaze,?,Nvidia Tegra124 +google/oak,?,Mediatek mt8173 soc +google/storm,?,Qualcomm +google/veyron,?,RockChip rk3288 +google/veyron_mickey,?,RockChip rk3288 +google/veyron_rialto,?,RockChip rk3288 +opencellular/elgon,?,cavium +sifive/hifive-unleashed,?,Sifive soc +adi/rcc-dff,n,Needs FSP for RAM init +adlink/cExpress-GFR,n,Needs VGA-ROM +adlink/CM2-GF,n,Needs VGA-ROM +advansus/a785e-i,n,Needs VGA-ROM +amd/bettong,n,Needs AMD PI for initialisation +amd/bimini_fam10,n,Needs VGA-ROM +amd/db-ft3b-lc,n,Needs AMD PI for initialisation +amd/gardenia,n,Needs AMD PI for initialisation +amd/inagua,n,Needs VGA-ROM +amd/lamar,n,Needs AMD PI for initialisation +amd/mahogany_fam10,n,Needs VGA-ROM +amd/olivehill,n,Needs VGA-ROM +amd/olivehillplus,n,Needs AMD PI for initialisation +amd/parmer,n,Needs VGA-ROM +amd/persimmon,n,Needs VGA-ROM +amd/serengeti_cheetah_fam10,n,Needs VGA-ROM +amd/south_station,n,Needs VGA-ROM +amd/thatcher,n,Needs VGA-ROM +amd/tilapia_fam10,n,Needs VGA-ROM +amd/torpedo,n,Needs VGA-ROM +amd/union_station,n,Needs VGA-ROM +aopen/dxplplusu,n,Needs VGA-ROM +asrock/e350m1,n,Needs VGA-ROM +asrock/h110m,n,Needs FSP for RAM init +asrock/h81m-hds,n,Needs FSP for RAM init +asrock/imb-a180,n,Needs VGA-ROM +asus/am1i-a,n,Needs VGA-ROM +asus/f2a85-m,n,Needs VGA-ROM +asus/f2a85-m_fam10,n,Needs VGA-ROM +asus/kcma-d8,n,Needs VGA-ROM +asus/kfsn4-dre,n,Needs VGA-ROM +asus/kfsn4-dre_k8,n,Needs VGA-ROM +asus/kgpe-d16,n,Needs VGA-ROM +asus/m4a78-em,n,Needs VGA-ROM +asus/m4a785-m,n,Needs VGA-ROM +asus/m4a785t-m,n,Needs VGA-ROM +asus/m5a88-v,n,Needs VGA-ROM +avalue/eax-785e,n,Needs VGA-ROM +bap/ode_e20XX,n,Needs VGA-ROM +bap/ode_e21XX,n,Needs AMD PI for initialisation +biostar/a68n_5200,n,Needs VGA-ROM +biostar/am1ml,n,Needs VGA-ROM +elmex/pcm205400,n,Needs VGA-ROM +elmex/pcm205401,n,Needs VGA-ROM +esd/atom15,n,Needs FSP for RAM init +facebook/watson,n,Needs FSP for RAM init +gigabyte/ma785gm,n,Needs VGA-ROM +gigabyte/ma785gmt,n,Needs VGA-ROM +gigabyte/ma78gm,n,Needs VGA-ROM +gizmosphere/gizmo,n,Needs VGA-ROM +gizmosphere/gizmo2,n,Needs VGA-ROM +google/auron,n,Needs FSP for RAM init +google/beltino,n,Needs FSP for RAM init +google/butterfly,n,Sandy/Ivy unported +google/cyan,n,Needs blob for Braswell SOC +google/dragonegg,n,Needs blob for Icelake SOC +google/eve,n,Needs FSP for RAM init +google/fizz,n,Needs FSP for RAM init +google/glados,n,Needs FSP for RAM init +google/hatch,n,Needs Blob for Cannonlake SOC +google/jecht,n,Needs FSP for RAM init +google/kahlee,n,Needs AMD PI for initialisation +google/link,n,Sandy/Ivy unported +google/octopus,n,Needs blob for GLK soc +google/parrot,n,Sandy/Ivy unported +google/poppy,n,Needs FSP for RAM init +google/rambi,n,Needs FSP for RAM init +google/reef,n,Needs FSP for RAM init +google/sarien,n,Needs blob for Whiskeylake SOC +google/slippy,n,Needs FSP for RAM init +google/stout,n,Sandy/Ivy unported +hp/abm,n,Needs VGA-ROM +hp/dl165_g6_fam10,n,Needs VGA-ROM +hp/pavilion_m6_1035dx,n,Needs VGA-ROM +ibase/mb899,n,Needs VGA-ROM +iei/kino-780am2-fam10,n,Needs VGA-ROM +intel/apollolake_rvp,n,Needs FSP for RAM init +intel/baskingridge,n,Needs FSP for RAM init +intel/bayleybay_fsp,n,Needs FSP for RAM init +intel/camelbackmountain_fsp,n,Needs FSP for RAM init +intel/cannonlake_rvp,n,Needs FSP for RAM init +intel/coffeelake_rvp,n,Needs FSP for RAM init +intel/emeraldlake2,n,Sandy/Ivy unported +intel/galileo,n,Needs FSP for RAM init +intel/glkrvp,n,Needs FSP for RAM init +intel/harcuvar,n,Needs blob for Denverton SOC +intel/icelake_rvp,n,Needs FSP for RAM init +intel/kblrvp,n,Needs FSP for RAM init +intel/kunimitsu,n,Needs FSP for RAM init +intel/leafhill,n,Needs FSP for RAM init +intel/littleplains,n,Needs FSP for RAM init +intel/minnow3,n,Needs FSP for RAM init +intel/minnowmax,n,Needs FSP for RAM init +intel/mohonpeak,n,Needs FSP for RAM init +intel/saddlebrook,n,Needs FSP for RAM init +intel/strago,n,Needs blob for Braswell SOC +intel/wtm2,n,Needs FSP for RAM init +jetway/pa78vm5,n,Needs VGA-ROM +kontron/986lcd-m,n,Needs VGA-ROM +lenovo/g505s,n,Needs VGA-ROM +lippert/frontrunner-af,n,Needs VGA-ROM +lippert/toucan-af,n,Needs VGA-ROM +msi/ms7721,n,Needs VGA-ROM +msi/ms9652_fam10,n,Needs VGA-ROM +ocp/monolake,n,Needs FSP for RAM init +ocp/wedge100s,n,Needs FSP for RAM init +opencellular/rotundu,n,Needs FSP for RAM init +pcengines/apu1,n,Needs VGA-ROM +pcengines/apu2,n,Needs AMD PI for initialisation +purism/librem_bdw,n,Needs FSP for RAM init +purism/librem_skl,n,Needs FSP for RAM init +roda/rk886ex,n,Needs VGA-ROM +roda/rk9,n,Needs VGA-ROM +samsung/lumpy,n,Sandy/Ivy unported +samsung/stumpy,n,Sandy/Ivy unported +scaleway/tagada,n,Needs blob for Denverton SOC +siemens/mc_apl1,n,Needs FSP for RAM init +siemens/mc_bdx1,n,Needs FSP for RAM init +siemens/mc_tcu3,n,Needs FSP for RAM init +supermicro/h8dmr_fam10,n,Needs VGA-ROM +supermicro/h8qme_fam10,n,Needs VGA-ROM +supermicro/h8scm_fam10,n,Needs VGA-ROM +supermicro/x10slm-f,n,Needs FSP for RAM init +tyan/s2912_fam10,n,Needs VGA-ROM +via/epia-m850,n,Needs VGA-ROM +apple/macbook21,Y, +apple/macbookair4_2,Y, +asrock/b75pro3-m,Y, +asrock/g41c-gs,Y, +asus/h61m-cs,Y, +asus/maximus_iv_gene-z,Y, +asus/p2b,Y, +asus/p2b-d,Y, +asus/p2b-ds,Y, +asus/p2b-f,Y, +asus/p2b-ls,Y, +asus/p3b-f,Y, +asus/p5gc-mx,Y, +asus/p5qc,Y, +asus/p5qpl-am,Y, +asus/p8h61-m_lx,Y, +asus/p8h61-m_pro,Y, +compulab/intense_pc,Y, +emulation/qemu-armv7,Y, +emulation/qemu-i440fx,Y, +emulation/qemu-power8,Y, +emulation/qemu-q35,Y, +emulation/qemu-riscv,Y, +emulation/spike-riscv,Y, +foxconn/d41s,Y, +foxconn/g41s-k,Y, +getac/p470,Y, +gigabyte/ga-945gcm-s2l,Y, +gigabyte/ga-b75m-d3h,Y, +gigabyte/ga-b75m-d3v,Y, +gigabyte/ga-g41m-es2l,Y, +gigabyte/ga-h61m-s2pv,Y, +google/peach_pit,Y,Needs confirmation +google/smaug,Y,Needs confirmation +google/urara,Y,Needs confirmation +hp/2570p,Y, +hp/2760p,Y, +hp/8460p,Y, +hp/8470p,Y, +hp/8770w,Y, +hp/compaq_8200_elite_sff,Y, +hp/folio_9470m,Y, +hp/revolve_810_g1,Y, +intel/d510mo,Y, +intel/d945gclf,Y, +intel/dcp847ske,Y, +intel/dg41wv,Y, +intel/dg43gt,Y, +jetway/nf81-t56n-lf,Y, +kontron/ktqm77,Y, +lenovo/l520,Y, +lenovo/s230u,Y, +lenovo/t400,Y, +lenovo/t420,Y, +lenovo/t420s,Y, +lenovo/t430,Y, +lenovo/t430s,Y, +lenovo/t520,Y, +lenovo/t530,Y, +lenovo/t60,Y, +lenovo/thinkcentre_a58,Y, +lenovo/x1_carbon_gen1,Y, +lenovo/x131e,Y, +lenovo/x200,Y, +lenovo/x201,Y, +lenovo/x220,Y, +lenovo/x230,Y, +lenovo/x60,Y, +lenovo/z61t,Y, +packardbell/ms2290,Y, +roda/rv11,Y, +sapphire/pureplatinumh61,Y, +ti/beaglebone,Y, -- To view, visit https://review.coreboot.org/c/coreboot/+/32237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I526b453ca30d8bcb6a55b40f4e53c6852f7cf4c7 Gerrit-Change-Number: 32237 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-MessageType: newchange

14 41

Change in ...coreboot[master]: security/tpm: Apply clang-format with new changes
by Philipp Deppenwiese (Code Review) 07 Aug '23

07 Aug '23

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31816 Change subject: security/tpm: Apply clang-format with new changes ...................................................................... security/tpm: Apply clang-format with new changes * Fix 80 lines length issues as expected Change-Id: Ieeb675e96b95f6bf2d6a5b9d2be3ca8fd4ed6946 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/tpm/tspi/log.c 1 file changed, 16 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31816/1 diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 18ab288..dc8a1e4 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -33,8 +33,9 @@ if (cbmem_possibly_online()) { tclt = cbmem_find(CBMEM_ID_TCPA_LOG); if (!tclt) { - size_t tcpa_log_len = sizeof(struct tcpa_table) + - MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); + size_t tcpa_log_len = + sizeof(struct tcpa_table) + + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); tclt = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_log_len); if (tclt) { tclt->max_entries = MAX_TCPA_LOG_ENTRIES; @@ -51,11 +52,9 @@ /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ - if (!cbmem_possibly_online() && - !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) + if (!cbmem_possibly_online() && !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) return (struct tcpa_table *)_vboot2_tpm_log; - else if (ENV_ROMSTAGE && - !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) { + else if (ENV_ROMSTAGE && !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) { tclt = tcpa_cbmem_init(); if (!tclt) return (struct tcpa_table *)_vboot2_tpm_log; @@ -84,17 +83,15 @@ for (j = 0; j < tce->digest_length; j++) printk(BIOS_INFO, "%02x", tce->digest[j]); - printk(BIOS_INFO, " %s [%s]\n", - tce->digest_type, tce->name); + printk(BIOS_INFO, " %s [%s]\n", tce->digest_type, tce->name); } } printk(BIOS_INFO, "\n"); } void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - enum vb2_hash_algorithm digest_algo, - const uint8_t *digest, - const size_t digest_len) + enum vb2_hash_algorithm digest_algo, const uint8_t *digest, + const size_t digest_len) { struct tcpa_table *tclt = tcpa_log_init(); if (!tclt) { @@ -121,9 +118,8 @@ return; } - strncpy(tce->digest_type, - vb2_get_hash_algorithm_name(digest_algo), - TCPA_PCR_HASH_LEN - 1); + strncpy(tce->digest_type, vb2_get_hash_algorithm_name(digest_algo), + TCPA_PCR_HASH_LEN - 1); tce->digest_length = digest_len; memcpy(tce->digest, digest, tce->digest_length); } @@ -144,7 +140,8 @@ int i; if (preram_log->num_entries > MAX_PRERAM_TCPA_LOG_ENTRIES) { - printk(BIOS_WARNING, "TCPA: Pre-RAM TCPA log is too full, possible corruption\n"); + printk(BIOS_WARNING, + "TCPA: Pre-RAM TCPA log is too full, possible corruption\n"); return; } @@ -164,8 +161,10 @@ return; } - strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); - tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); + strncpy(tce->digest_type, preram_log->entries[i].digest_type, + TCPA_PCR_HASH_LEN - 1); + tce->digest_length = + MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeb675e96b95f6bf2d6a5b9d2be3ca8fd4ed6946 Gerrit-Change-Number: 31816 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: southbridge/amd/pi/hudson : Revert partially commit bfb5c807e720761f4...
by Jorge Fernandez (Code Review) 07 Aug '23

07 Aug '23

Jorge Fernandez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37617 ) Change subject: southbridge/amd/pi/hudson : Revert partially commit bfb5c807e720761f4457d5106bb919f2aacb5535 ...................................................................... southbridge/amd/pi/hudson : Revert partially commit bfb5c807e720761f4457d5106bb919f2aacb5535 For AMD Bettong board to boot these changes should be reverted. The three options must be enabled to boot. Change-Id: Ied530563f5ff961b50213ffad874351bbd0d3ae3 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37617/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 33f59c7..29cf6d0 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -85,10 +85,10 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -- To view, visit https://review.coreboot.org/c/coreboot/+/37617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied530563f5ff961b50213ffad874351bbd0d3ae3 Gerrit-Change-Number: 37617 Gerrit-PatchSet: 1 Gerrit-Owner: Jorge Fernandez Gerrit-MessageType: newchange

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