coreboot-gerrit October 2019

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Change in coreboot[master]: Doc/mb/asus: Add H110M-E/M.2 Documentation
by Pavel Sayekat (Code Review) 09 Jun '23

09 Jun '23

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35011 ) Change subject: Doc/mb/asus: Add H110M-E/M.2 Documentation ...................................................................... Doc/mb/asus: Add H110M-E/M.2 Documentation Followed and adapted from the ASRock H110M-DVS Documentation Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b --- A Documentation/mainboard/asus/h110m-e_m2.md 1 file changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35011/1 diff --git a/Documentation/mainboard/asus/h110m-e_m2.md b/Documentation/mainboard/asus/h110m-e_m2.md new file mode 100644 index 0000000..134dca8 --- /dev/null +++ b/Documentation/mainboard/asus/h110m-e_m2.md @@ -0,0 +1,136 @@ +# ASUS H110M-E/M.2 + +This page describes how to run coreboot on the [ASUS H110M-E/M.2]. + +## Required proprietary blobs + +Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. +Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md) +(intel FSP 2.0) to initialize this generation silicon. Please see this +[document](../../soc/intel/code_development_model/code_development_model.md). + +FSP Information: + +```eval_rst ++-----------------------------+-------------------+-------------------+ +| FSP Project Name | Directory | Specification | ++-----------------------------+-------------------+-------------------+ +| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 | +| processors and chipsets | | | +| (formerly Kaby Lake) | | | ++-----------------------------+-------------------+-------------------+ +``` + +## Building coreboot + +The following steps set the default parameters for this board to build a +fully working image: + +```bash +make distclean +touch .config +./util/scripts/config --enable VENDOR_ASUS +./util/scripts/config --enable BOARD_ASUS_H110M_E_M2 +./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES +./util/scripts/config --enable CONFIG_FSP_USE_REPO +./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" +make olddefconfig +``` + +However, it is strongly advised to use `make menuconfig` afterwards +(or instead), so that you can see all of the settings. + +Use the following command to disable the serial console if debugging +output is not required: + +```bash +./util/scripts/config --disable CONSOLE_SERIAL +``` + +However, a more flexible method is to change the console log level from +within an OS using `util/nvramtool`, or with the `nvramcui` payload. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region, such as the Management Engine or firmware descriptor, then +an external programmer is required (unless you find a clever way around +the flash protection). More information about this [here](../../flash_tutorial/index.md). + +### External programming + +The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a +GIgaDevice GD25B128CPIG, whose datasheet can be found [here][GD25B128CPIG]. +The chip is located to the bottom right-hand side of the board. For +a precise location, refer to section 1.3 (Motherboard Layout) of the +[H110M-E/M.2 manual], where the chip is labelled "128Mb BIOS". Take note of +the chip's orientation, remove it from its socket, and flash it with +an external programmer. For reference, the notch in the chip should be +facing towards the bottom of the board. + +## Known issues + +- The VGA port doesn't work. Discrete graphic card is used as primary + device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not + set). Dynamic switching between iGPU and PEG is not yet supported. + +- SuperIO GPIO pin is used to reset Realtek chip. However, since the + Logical Device 7 (GPIO7, GPIO8) is not initialized, the network + chip is in a reset state all the time. + +## Untested + +- parallel port +- PS/2 keyboard +- PS/2 mouse +- EHCI debug +- TPM +- infrared module +- chassis intrusion header +- chassis speaker header + +## Working + +- integrated graphics init with libgfxinit (see [Known issues](#known-issues)) +- PCIe x1 +- PEG x16 Gen3 +- SATA +- USB +- serial port +- onboard audio +- using `me_cleaner` +- using `flashrom` + +## TODO + +- NCT5539D GPIOs +- onboard network (see [Known issues](#known-issues)) +- S3 suspend/resume +- Wake-on-LAN +- hardware monitor + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Skylake/Kaby Lake (LGA1151) | ++------------------+--------------------------------------------------+ +| PCH | Intel Sunrise Point H110 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT5539D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[ASUS H110M-E/M.2]: https://www.asus.com/Motherboards/H110M-E-M-2/overview/ +[GD25B128CPIG]: https://www.gigadevice.com/datasheet/gd25b127d/ [The closest match found] +[flashrom]: https://flashrom.org/Flashrom +[ASUS H110M-E/M.2 manual]: https://dlcdnets.asus.com/pub/ASUS/mb/LGA1151/H110M-E_M2/E11622_H110M-E_M2_… -- To view, visit https://review.coreboot.org/c/coreboot/+/35011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b Gerrit-Change-Number: 35011 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/soc/intel: Add documentation for MCU update
by Varshit B Pandya (Code Review) 09 Jun '23

09 Jun '23

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34657 ) Change subject: Documentation/soc/intel: Add documentation for MCU update ...................................................................... Documentation/soc/intel: Add documentation for MCU update Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- A Documentation/soc/intel/ucode_update/Flash_Layout.PNG A Documentation/soc/intel/ucode_update/microcode_update_model.md 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34657/1 diff --git a/Documentation/soc/intel/ucode_update/Flash_Layout.PNG b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG new file mode 100644 index 0000000..ac18977 --- /dev/null +++ b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG Binary files differ diff --git a/Documentation/soc/intel/ucode_update/microcode_update_model.md b/Documentation/soc/intel/ucode_update/microcode_update_model.md new file mode 100644 index 0000000..e2d7f35 --- /dev/null +++ b/Documentation/soc/intel/ucode_update/microcode_update_model.md @@ -0,0 +1,43 @@ +# Microcode update mechanism for devices in field + +## Introduction + +Processor microcode (MCU) is akin to processor firmware. Processors may need updates to their microcode to operate correctly. These updates fix bugs/errata that can cause anything from incorrect processing, to code and data corruption, and system lockups. + +##Problem Statement + +As per chrome design, any field updatable FW has to be first verified by vboot (chrome root of trust - CROT) before it is allowed to run on the system. CROT executes on the CPU, hence FW such as MCU loaded before the CPU reset cannot be verified before it actually gets loaded. As a result today Chromebooks are not able to apply MCU in the field. This proposal tries to address the issue + +Prior to CPU reset, the CPU HW locates the FIT table from the storage, walks over the FIT table and picks-up the MCU that matches the CPU Family, Model, Stepping and PLATFORM ID with the highest revision ID. CPU verifies that MCU is signed by Intel and once verification is successful, it attempts to load the MCU. + +However FIT does not contain any fall back mechanism. If one MCU loading fails for whatever reason, it drops the further loading process and moves on to CPU reset. While it is fairly a remote chance, in case of any failure to load MCU which cause hang like situations before CPU reset, a platform based mechanism can be put in place to enter recovery mode. As detailed below, if we are using BUC register based top swap implementation, then an RTC reset may be required to clear top swap bit. + +## Design Proposal + +The proposal relies on the following Intel SoC features: + +1. Top swap, which enables the BIOS to have 2 bootblocks and bot from either using a RTC backed Top swap control bit in BUC register. +2. Firmware Interface Table (FIT) based MCU loading. + +The idea is to have 2 bootblocks, each having its own FIT table. The FIT in one of them will be configured to point to an MCU in RO firmware, and the FIT in other one will point to a fixed flash region (aka MCU staging area), which will contain an MCU from RW firmware. + +Top-swap feature of Intel CPUs, will be used to switch between 2 bootblocks, based on the bootmode i.e., recovery or normal/developer mode. + +Coreboot will keep the MCU staging area updated with the MCU from the currently selected RW firmware. + +## Implementation Details + +1. Create 2 BBs (bb_ro_ucode and bb_staged_ucode) each containing their own FIT tables. Both bootblocks will be in the RO section. + a. bb_ro_ucode contains a FIT which has pointer to MCU (microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. + b. bb_staged_ucode is identical to bb_ro_ucode but contains a FIT which has pointer to a MCU that will reside in a staging area. +2. Create a MCU staging area + a. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for that SoC. This is a RW region just lke the RW_MRC_CACHE. + b. MCU from RW-A/RW-B will be copied to this region during boot. + c. A Flash Protected Range (FPR) should be configured to write protect this MCU Staging area. + d. bb_staged_ucode FIT points to the MCU in this staging area. +3. The resulting flash layout is shown below, +**Flash Layout** +![Flash Layout][flash_layout] +[flash_layout]: Flash_Layout.PNG + +4. The proposed design uses the PCR register based control for top-swap -- To view, visit https://review.coreboot.org/c/coreboot/+/34657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3deb24550c1f1cd4c7b8082af75115ca174c295a Gerrit-Change-Number: 34657 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: vendorcode/google: load sar config from CBFS first then VPD
by Marco Chen (Code Review) 09 Jun '23

09 Jun '23

Hello Marco Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33661 to review the following change. Change subject: vendorcode/google: load sar config from CBFS first then VPD ...................................................................... vendorcode/google: load sar config from CBFS first then VPD SAR config provisioned in RO VPD can be done in the factory only. Once it is wrong, we can override the SAR config by updating FW RW which can carry new SAR config in CBFS. As a result, we should check CBFS first then VPD. Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1 Signed-off-by: Marco Chen <marcochen(a)chromium.org> --- M src/vendorcode/google/chromeos/sar.c 1 file changed, 23 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33661/1 diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index bbcb211..a5a2c3b 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -82,36 +82,37 @@ sizeof(struct wifi_sar_delta_table); } - /* Try to read the SAR limit entry from VPD */ - if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, - buffer_size, VPD_ANY)) { - printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", - wifi_sar_limit_key); - - if (!CONFIG(WIFI_SAR_CBFS)) - return -1; - + if (CONFIG(WIFI_SAR_CBFS)) { printk(BIOS_DEBUG, "Checking CBFS for default SAR values\n"); sar_cbfs_len = load_sar_file_from_cbfs( (void *) wifi_sar_limit_str, sar_expected_len); - if (sar_cbfs_len != sar_expected_len) { - printk(BIOS_ERR, "%s has bad len in CBFS\n", - WIFI_SAR_CBFS_FILENAME); - return -1; - } - } else { - /* VPD key "wifi_sar" found. strlen is checked with addition of - * 1 as we have created buffer size 1 char larger for the reason - * mentioned at start of this function itself */ - if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) { - printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n"); - return -1; - } + if (sar_cbfs_len == sar_expected_len) + goto done; + + printk(BIOS_ERR, "%s has bad len in CBFS\n", + WIFI_SAR_CBFS_FILENAME); } + /* Try to read the SAR limit entry from VPD */ + if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, + buffer_size, VPD_ANY)) { + printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", + wifi_sar_limit_key); + return -1; + } + + /* VPD key "wifi_sar" found. strlen is checked with addition of + * 1 as we have created buffer size 1 char larger for the reason + * mentioned at start of this function itself */ + if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) { + printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n"); + return -1; + } + +done: /* Decode the heximal encoded string to binary values */ if (hexstrtobin(wifi_sar_limit_str, bin_buffer, bin_buff_adjusted_size) < bin_buff_adjusted_size) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1 Gerrit-Change-Number: 33661 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newchange

7 17

Change in ...coreboot[master]: Documentation: Explain DDR3 read training
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32334 Change subject: Documentation: Explain DDR3 read training ...................................................................... Documentation: Explain DDR3 read training Add lots of colorful graphics to explain DDR3 read training in detail, what is done inside MCH and what needs to be done on firmware level. Besides read training give a short explenation what DDR3 "FlyBy" is and compare it with DDR2 DIMMs. Besides the SVG all sources files are added. Change-Id: Ib477bd332984c397289404cfc33c65a2d4469257 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/getting_started/index.md A Documentation/getting_started/ram_initialization/16delay.dia A Documentation/getting_started/ram_initialization/16delay.svg A Documentation/getting_started/ram_initialization/64delay.dia A Documentation/getting_started/ram_initialization/64delay.svg A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.dia A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.svg A Documentation/getting_started/ram_initialization/ddr3_flyby.md A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg A Documentation/getting_started/ram_initialization/index.md A Documentation/getting_started/ram_initialization/read_training.dia A Documentation/getting_started/ram_initialization/read_training.svg A Documentation/getting_started/ram_initialization/read_training2.dia A Documentation/getting_started/ram_initialization/read_training2.svg A Documentation/getting_started/ram_initialization/read_training3.dia A Documentation/getting_started/ram_initialization/read_training3.svg A Documentation/getting_started/ram_initialization/read_training_pattern.dia A Documentation/getting_started/ram_initialization/read_training_pattern.svg A Documentation/getting_started/ram_initialization/readtraining.md A Documentation/getting_started/ram_initialization/recv_blocks.dia A Documentation/getting_started/ram_initialization/recv_blocks.svg 22 files changed, 1,989 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32334/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..a265c5d 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [DDR3 memory initialization](ram_initialization/index.md) diff --git a/Documentation/getting_started/ram_initialization/16delay.dia b/Documentation/getting_started/ram_initialization/16delay.dia new file mode 100644 index 0000000..d0e0095 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/16delay.svg b/Documentation/getting_started/ram_initialization/16delay.svg new file mode 100644 index 0000000..f661ddd --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.svg @@ -0,0 +1,177 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="38cm" height="18cm" viewBox="366 265 754 351" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="367.719" y="266.052" width="751.775" height="348.316"/> + <rect style="fill: none; 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As every DIMM only needs to terminate the line once at end of PCB, +the DC resistance is much lower as on DDR2 "tree" routing topology, which did +terminate on every IC. + +The disadvantage of "fly-by" is the more complex memory training that needs to +be done to find the DATA lane skew. + +After the skew has been measured, the DATA lanes needs to be delayed by the +memory controller, to make sure all signals are still synchronous to the CLK, +as seen be the memory controller (on READ) or the DRAM (on WRITE). + +![][flyby] + +[flyby]: ddr3_vs_ddr2.svg + +```eval_rst ++---------------------------+------------+----------------+ +| Feature | DDR2 | DDR3 | ++===========================+============+================+ +| Frequency | 200-533 | 400-800 | ++---------------------------+------------+----------------+ +| Routing | complex | easy | ++---------------------------+------------+----------------+ +| Termination DC resistance | very high | low | ++---------------------------+------------+----------------+ +| Memory training | easy | complex | ++---------------------------+------------+----------------+ +``` + diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia new file mode 100644 index 0000000..e4b4d09 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg new file mode 100644 index 0000000..0b8db34 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg @@ -0,0 +1,298 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="17cm" height="10cm" viewBox="507 221 325 192" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="508.366" y="221.748" width="323.85" height="190.069"/> + <rect style="fill: none; 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It is usually done by firmware. +As soon as the skew is known, the DATA lanes can be individually delayed +by a constant rate to synchronize the DATA arriving at the MCH. + +For read training the DIMM is placed into a special mode where it outputs +a known pattern. The pattern looks like this: + +![][pat] + +[pat]: read_training_pattern.svg + +Due to the different skew of the lanes, the data arrives at different times +on the MCH. It's no longer synchronous to the CLK or other DATA lanes: + +![][read1] + +[read1]: read_training.svg + +The MCH must delay the signals to synchronize them again. + +### Delay units +The MCH is able to delay all lanes individually or at once. The delay +circuit inside the MCH consists of a *phase delay unit* and *CLK delay units*. +The *phase delay unit* delays by a fraction of the CLK, while the +*CLK delay unit* delays in multiple of the CLK. + +They can be configured by firmware using registers inside the MCH. + +#### Phase delay +The phase delay unit might look like this: + +![][delay64] + +[delay64]: 64delay.svg + +The phase delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be shifted by 64 1/64 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the CLK as seen by the MCH: + +![][read2] + +[read2]: read_training2.svg + + +#### CLK delay +The CLK delay unit might look like this: + +![][delay16] + +[delay16]: 16delay.svg + +The CLK delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be delayed by 16 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the other DQS lanes: + +![][read3] + +[read3]: read_training3.svg + +#### Combined delay + +Both units are connected in row for each DQS/DATA lane: + +![][blocks] + +[blocks]: recv_blocks.svg + +For each lane (here 8 + 1), there's a 10bit register allowing to adjust the +delay. + +## Finding the right delay + +Assuming a 1/64th phase delay unit, the firmware guesses the initial skew and then places the phase in the alternating data pattern. It then adjest the phase and measures the sampled value. + +The following algorithm is used: + +1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern. +2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low". +3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern. +4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge. +5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge. + +Read training has now found the exact delay for each lane and stores the values for the next boot. This feature is known as *Fast Boot* or *MRC cache*. + + +[FlyBy routing]: ddr3_flyby.md diff --git a/Documentation/getting_started/ram_initialization/recv_blocks.dia b/Documentation/getting_started/ram_initialization/recv_blocks.dia new file mode 100644 index 0000000..cf554ae --- /dev/null +++ b/Documentation/getting_started/ram_initialization/recv_blocks.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/recv_blocks.svg b/Documentation/getting_started/ram_initialization/recv_blocks.svg new file mode 100644 index 0000000..562d0dd --- /dev/null +++ b/Documentation/getting_started/ram_initialization/recv_blocks.svg @@ -0,0 +1,627 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="36cm" height="36cm" viewBox="165 -414 717 702" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="167" y="-412" width="714" height="699"/> + <rect style="fill: none; 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Change in ...coreboot[master]: arch/x86/mmio: Avoid pointer aliasing in write8()
by Nico Huber (Code Review) 09 Jun '23

09 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31945 Change subject: arch/x86/mmio: Avoid pointer aliasing in write8() ...................................................................... arch/x86/mmio: Avoid pointer aliasing in write8() Don't literally dereference a pointer to `char`. Use array indexing instead to avoid aliasing rules. Otherwise, the compiler might treat any memory as clobbered. Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/include/arch/mmio.h 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31945/1 diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..790b699 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -45,7 +45,15 @@ static __always_inline void write8(volatile void *addr, uint8_t value) { - *((volatile uint8_t *)(addr)) = value; + /* + * Don't literally dereference a pointer to `char`. Use array + * indexing instead to avoid aliasing rules. Otherwise, the + * compiler might treat any memory as clobbered. + */ + volatile struct { + uint8_t reg[1]; + } *const ref = addr; + ref->reg[0] = value; } static __always_inline void write16(volatile void *addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/31945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I441c27e789ad92a8125c92837244474a26250c8a Gerrit-Change-Number: 31945 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: arch/riscv: Fix arch timer timebase
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33797 Change subject: arch/riscv: Fix arch timer timebase ...................................................................... arch/riscv: Fix arch timer timebase The arch timer uses a platform specific clock source. Add a Kconfig that holds this clock frequency and use it to calculate the time passed by. Tested on qemu-system-riscv: Fixes delays being ten times shorter as expected. Change-Id: I2588149e2ee32130a2c41695c4c723b57d4fa827 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/arch_timer.c M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33797/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 25a3980..6b12ff0 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -72,5 +72,9 @@ bool default n +config RISCV_ARCH_TIMER_FREQ + int + depends on RISCV_USE_ARCH_TIMER + config RISCV_WORKING_HARTID int diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 55b1f72..71b9771 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -20,9 +20,18 @@ #include <timer.h> #include <mcall.h> +/* mtime is clocked by platform specific clock source */ +static const uint32_t clocks_per_usec = CONFIG_RISCV_ARCH_TIMER_FREQ/1000000; + void timer_monotonic_get(struct mono_time *mt) { + uint64_t raw; + if (HLS()->time == NULL) die("time not set in HLS"); - mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time))); + if (!clocks_per_usec) + die("Unsupported mtime clock frequency"); + + raw = read64((void *)(HLS()->time)); + mono_time_set_usecs(mt, (long)(raw / clocks_per_usec)); } diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..a10a146 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,8 @@ int default 0 +config RISCV_ARCH_TIMER_FREQ + int + default 1000000 + endif diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index ad48c1c..49887a4 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -14,6 +14,10 @@ if SOC_UCB_RISCV +config RISCV_ARCH_TIMER_FREQ + int + default 10000000 + if ARCH_RISCV_RV64 config RISCV_ARCH -- To view, visit https://review.coreboot.org/c/coreboot/+/33797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2588149e2ee32130a2c41695c4c723b57d4fa827 Gerrit-Change-Number: 33797 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: RFC: smbios: allow setting BIOS-version string from VPD variable
by Łukasz Siudut (Code Review) 09 Jun '23

09 Jun '23

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32905 Change subject: RFC: smbios: allow setting BIOS-version string from VPD variable ...................................................................... RFC: smbios: allow setting BIOS-version string from VPD variable As in the title. Such approach allows for convenient setting of the firmware version and keep it in partition that is easily readable from both - coreboot binary and already running operating system. vpd_find is used directly as it returns pointer to vpd value which, by spec, is terminated by 0x00 (VPD_TYPE_TERMINATOR) anyway. This way we avoid copying string around and coming up with temporary buffer. Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Signed-off-by: Lukasz Siudut <lsiudut(a)gmail.com> --- M src/arch/x86/smbios.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32905/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 589f4f0..2ffd2dd 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,9 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> +#if CONFIG(VPD) +#include <drivers/vpd/vpd.h> +#endif #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -347,6 +350,15 @@ const char *__weak smbios_mainboard_bios_version(void) { +#if CONFIG(VPD) + /* size is unused for now */ + int size; + const char *coreboot_vpd_version = vpd_find("version", &size, VPD_RO); + + /* if found, vpd value will be terminated by 0x00 (VPD_TYPE_TERMINATOR) */ + if(coreboot_vpd_version) + return coreboot_vpd_version; +#endif if (strlen(CONFIG_LOCALVERSION)) return CONFIG_LOCALVERSION; else -- To view, visit https://review.coreboot.org/c/coreboot/+/32905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Gerrit-Change-Number: 32905 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues
by Nico Huber (Code Review) 09 Jun '23

09 Jun '23

Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Michael Niewöhner, Duncan Laurie, David Wu, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36328 to review the following change. Change subject: [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues ...................................................................... [RFC, scratch] Documentation/fsp: Start discussion around FSP-S issues To get some discussion started, list some heavy issues with FSP(-S). I've copy pasted some things together, and added a few words on top and bottom. Not sure yet, where this should lead. To convince Intel to contribute open-source code on their own, we might want to add a list of initialization steps, that should be open. Feel free to amend this commit in any way :) Change-Id: Ied0d8ad60fa487272a05fc73b16a7c343cc4d993 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A Documentation/fsp/fsp-s_discussion.md 1 file changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36328/1 diff --git a/Documentation/fsp/fsp-s_discussion.md b/Documentation/fsp/fsp-s_discussion.md new file mode 100644 index 0000000..7ac649a --- /dev/null +++ b/Documentation/fsp/fsp-s_discussion.md @@ -0,0 +1,165 @@ +Introduction +============ + +*FSP* is an ABI that allows silicon vendors to provide pre-compiled +binaries of their silicon-initialization code for the integration +into firmware frameworks such as coreboot. Current, 2.x versions +of *FSP* describe three binaries with rough responsibilities: + +* `FSP-T`: Sets up a temporary RAM environment (usually some sort + of Cache as RAM, CAR) among other things. + +* `FSP-M`: Initializes the memory (DRAM) controller, among other + things. + +* `FSP-S`: Performs various silicon-initialization steps left. + +However, what operations these binaries perform exactly and what +operations are left to the firmware framework, is neither specified +nor documented. + +Historically, all these responsibilities were left to coreboot. +Later, pre-compiled reference code for the memory-controller +initialization was introduced, then for other silicon init, and +finally there are attempts to replace coreboot's CAR setup with +FSP-T. + +While the FSP-M integration saves coreboot developers time, because +of the complex nature of the memory-controller initialization, the +integration of FSP-S turns out to be harder than implementing the +necessary code natively in coreboot. We'll discuss why that is the +case and provide an incomplete list of issues with current FSP-S +binaries. + + +Bug Fixing +---------- + +Many companies rely on the pre-built FSP binaries. Yet, there is +no common procedure to get bugs fixed or even acknowledged. This +leads to an increase of workarounds in firmware frameworks, +especially for older hardware generations. + + +Lack of Documentation +--------------------- + +Many of the initialization steps performed by FSP-S are merely +translating mainboard-specific configuration into register settings. +This is reflected by a list of hundreds of configuration options of +FSP-S. While these steps are quite simple, the additional translation +from FSP options to register values heavily increases the integration +costs. Not only are the register settings usually much better documented +than their FSP counterparts, but FSP also uses different terms so that +the existing hardware documentation often can't assist developers when +dealing with FSP. + +FSP-S also performs locking of several registers so that they can't +be written anymore afterwards. It is not documented what locks are +set by FSP. This creates heavy security issues for multiple reasons: + +* One either has to assume that FSP doesn't perform any locking + and do it redundantly in the firmware framework, or expensively + test what is locked and keep doing so for every new FSP revision. + +* Some registers may be locked before they are configured in a + secure manner. This may result in workarounds in the firmware + framework to configure things early. Sometimes it's even + impossible to do so, because relevant information isn't + available yet. + +This shows that no matter the many options that are implemented in +FSP-S, there will always be things that must be controlled by the +firmware framework. Locking should either be a separate, last step +in FSP, or be left entirely to the firmware framework. And most of +all, the locking has to be documented. + + +Arbitrary Interface Changes +--------------------------- + +Within coreboot, we try to keep code-compatibility with older hardware +generations. The FSP ABI isn't stable, however. Even when the hardware +doesn't change between minor platform updates, the configuration +settings of FSP are sometimes adapted without backwards compatibility +in mind. This increases costs, just to translate configuration data +from one representation to another only to let FSP translate it again. +In such cases, directly configuring registers from coreboot, would +save two layers of indirection. + +Another problem is the disappearance of options in newer FSP releases. +See [SpiFlashCfgLockDown UPD vanished after KBL] +(https://github.com/IntelFsp/FSP/issues/25), for instance. Current +coreboot code seems to still rely on this option. It boots, though, +only security assumptions are broken. Which again shows, locking +shouldn't be part of FSP, or at least optional. + + +FSP Switches SAI +---------------- + +A problem that multiplies with the lack of documentation is that FSP-S +switches to `POSTBOOT_SAI` on newer platforms. While it probably tries +to achieve the opposite, this undermines firmware quality and security. + +* In some firmware frameworks FSP may run long before End-of-Post, this + means most of the framework runs with `POSTBOOT_SAI`. + +* In the EDS, implications of the SAI switch are _not_ documented. + Virtually for every register, it is unknown if it is still accessible + after the SAI switch. This seems to be a problem for developers both + inside and outside of Intel. + +* The SAI switch seems to force the firmware framework to do some things + in SMM. However, the use of SMM as a more privileged execution mode is + generally discouraged. This means FSP forces firmware development to + go backwards. + +Especially the lack of documentation leads to many bugs in firmware. +Even Intel developers working on coreboot don't seem to know the +implications of the SAI switch or lack the resources to re-evaluate +all code wrt. the SAI switch. + + +FSP Creates Legal Uncertainty +----------------------------- + +Many companies sell coreboot together with FSP as part of their products. +Especially, the function pointers to GPL code that were introduced with +FSP 2.1 seem unprecedented. However, they could be compared with runtime +linking which seems troubling. + + +Mitigations +----------- + +None of the listed issues would exist if FSP were open-source and the +initialization steps could be integrated into coreboot, like they were +before. An open-source approach would not only cut costs heavily but +might also decrease time-to-market if the whole coreboot community +could work together on new platforms. + +However, in the absence of such a firmware-development utopia, there +may be more realistic approaches. As mentioned earlier, not all of FSP +has a negative impact on development performance. FSP-M, for instance, +rarely causes trouble. And due to its complex nature, it is no surprise +if memory-controller initialization is kept secret. The configuration +done by FSP-S, on the other hand, overlaps with many of coreboot's +responsibilities. The few lines of code in FSP-S that help to get a +mainboard running, don't outweigh the damage it does. However, one +can't have the cherries without taking the whole menu, which takes +years to digest. + +One approach could be to split FSP-S further up and identify parts +that are necessarily closed source and parts that could as well be +reimplemented in coreboot. However, if parts that are left closed +source change the state of the execution environment (e.g. switch +SAI), finalize any settings or raise legal concerns, the ABI would +have to change to solve all aforementioned issues. + +Another approach could be to align older platforms with open-source +coreboot, step by step. Currently, everything from Skylake on relies +on FSP-S. However, it seems Intel has already abandoned development +for this platform (while the coreboot integration was never finished). +It would seem reasonable to release abandoned code to the public, or +at least clear existing documentation for older platforms from NDAs. -- To view, visit https://review.coreboot.org/c/coreboot/+/36328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied0d8ad60fa487272a05fc73b16a7c343cc4d993 Gerrit-Change-Number: 36328 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...
by junaid (Code Review) 09 Jun '23

09 Jun '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B
by Branden Waldner (Code Review) 09 Jun '23

09 Jun '23

Branden Waldner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35530 ) Change subject: mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B ...................................................................... mb/asus/p2-99: add Asus P2-99 as a variant of Asus P2B Squash add Asus P2-99 as clone of Asus P2B and convert clone to variant Change-Id: I78bd3e215c9c35d272919850f52feac135d06ed8 --- M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/Kconfig.name 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35530/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f34b4dd..0c77779 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -12,7 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B +if BOARD_ASUS_P2B || BOARD_ASUS_P2_99 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,12 +28,18 @@ string default asus/p2b +config VARIANT_DIR + string + default "p2-99" if BOARD_ASUS_P2_99 + default "p2b" if BOARD_ASUS_P2B + config MAINBOARD_PART_NUMBER string + default "P2-99" if BOARD_ASUS_P2_99 default "P2B" config IRQ_SLOT_COUNT int default 6 -endif # BOARD_ASUS_P2B +endif # BOARD_ASUS_P2B || BOARD_ASUS_P2_99 diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index 60d6028..a299a35 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASUS_P2B bool "P2B" + +config BOARD_ASUS_P2_99 + bool "P2-99" -- To view, visit https://review.coreboot.org/c/coreboot/+/35530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd3e215c9c35d272919850f52feac135d06ed8 Gerrit-Change-Number: 35530 Gerrit-PatchSet: 1 Gerrit-Owner: Branden Waldner <scruffy99(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019