coreboot-gerrit June 2018

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Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

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Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25509 ) Change subject: [Do Not Merge] add i945G based mainboard ...................................................................... Patch Set 17: (7 comments) https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… File src/mainboard/nec/945g-m4/superio_hwm.c: https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 90: //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) line over 80 characters https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 135: hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 140: temperatures[cpufan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 141: hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature line over 80 characters https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 149: hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 154: temperatures[sysfan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/17/src/mainboard/nec/945g-m4/superio_… PS17, Line 155: hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature line over 80 characters -- To view, visit https://review.coreboot.org/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 17 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Jun 2018 07:56:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/i945: Correct udelay for Netburst
by Arthur Heymans (Code Review) 30 Jun '18

30 Jun '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27296 ) Change subject: nb/intel/i945: Correct udelay for Netburst ...................................................................... Patch Set 1: This udelay implementation is only used in SMM. I think you'd better drop this one in favor of the lapic udelay. -- To view, visit https://review.coreboot.org/27296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68 Gerrit-Change-Number: 27296 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 30 Jun 2018 07:46:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

1 0

Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25509 ) Change subject: [Do Not Merge] add i945G based mainboard ...................................................................... Patch Set 16: (7 comments) https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… File src/mainboard/nec/945g-m4/superio_hwm.c: https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 90: //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) line over 80 characters https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 135: hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 140: temperatures[cpufan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 141: hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature line over 80 characters https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 149: hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 154: temperatures[sysfan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/16/src/mainboard/nec/945g-m4/superio_… PS16, Line 155: hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature line over 80 characters -- To view, visit https://review.coreboot.org/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 16 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Jun 2018 07:45:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/i945: Correct udelay for Netburst
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27296 ) Change subject: nb/intel/i945: Correct udelay for Netburst ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29682/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75625/ : SUCCESS -- To view, visit https://review.coreboot.org/27296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68 Gerrit-Change-Number: 27296 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Jun 2018 07:41:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/i945: Correct udelay for Netburst
by Elyes HAOUAS (Code Review) 30 Jun '18

30 Jun '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27296 Change subject: nb/intel/i945: Correct udelay for Netburst ...................................................................... nb/intel/i945: Correct udelay for Netburst NetBurst have FSB information at MSR_EBC_FREQUENCY_ID. Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/udelay.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27296/1 diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 8447453..b02f13b 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -18,6 +18,7 @@ #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> +#include <arch/cpu.h> /** * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock @@ -30,9 +31,18 @@ msr_t msr; u32 fsb = 0, divisor; u32 d; /* ticks per us */ + u8 fsbcfg; + const u32 eax = cpuid_eax(1); - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + switch (fsbcfg) { case 5: fsb = 400; break; -- To view, visit https://review.coreboot.org/27296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I588383dbdfd3d630c605c7d4d6014a3f82354e68 Gerrit-Change-Number: 27296 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

1 0

Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 30 Jun '18

30 Jun '18

1 0

Change in coreboot[master]: Documentation/soc/intel: Add common code design document
by Philipp Deppenwiese (Code Review) 30 Jun '18

30 Jun '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27087 ) Change subject: Documentation/soc/intel: Add common code design document ...................................................................... Patch Set 6: Let me give you +2 here. We are currently setting up infrastructure to review doc.coreboot.org changes. I guess this will help us a lot. -- To view, visit https://review.coreboot.org/27087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Gerrit-Change-Number: 27087 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Jun 2018 01:24:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit June 2018