coreboot-gerrit May 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/generic/bayhub: Add driver for BayHub BH720
by build bot (Jenkins) (Code Review) 01 May '18

01 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25966 ) Change subject: drivers/generic/bayhub: Add driver for BayHub BH720 ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/71083/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/25257/ : SUCCESS -- To view, visit https://review.coreboot.org/25966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Gerrit-Change-Number: 25966 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 May 2018 18:12:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee/variants/grunt: Enable BayHub720 driver
by build bot (Jenkins) (Code Review) 01 May '18

01 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25967 ) Change subject: mb/google/kahlee/variants/grunt: Enable BayHub720 driver ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/71082/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/25258/ : SUCCESS -- To view, visit https://review.coreboot.org/25967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Gerrit-Change-Number: 25967 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 May 2018 18:11:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/generic/bayhub: Add driver for BayHub BH720
by build bot (Jenkins) (Code Review) 01 May '18

01 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25966 ) Change subject: drivers/generic/bayhub: Add driver for BayHub BH720 ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/71079/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/25254/ : SUCCESS -- To view, visit https://review.coreboot.org/25966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Gerrit-Change-Number: 25966 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 May 2018 18:11:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee/variants/grunt: Enable BayHub720 driver
by build bot (Jenkins) (Code Review) 01 May '18

01 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25967 ) Change subject: mb/google/kahlee/variants/grunt: Enable BayHub720 driver ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/71081/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/25256/ : SUCCESS -- To view, visit https://review.coreboot.org/25967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Gerrit-Change-Number: 25967 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 May 2018 18:10:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee/variants/grunt: Enable BayHub720 driver
by build bot (Jenkins) (Code Review) 01 May '18

01 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25967 ) Change subject: mb/google/kahlee/variants/grunt: Enable BayHub720 driver ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/71080/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/25255/ : SUCCESS -- To view, visit https://review.coreboot.org/25967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Gerrit-Change-Number: 25967 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 May 2018 18:03:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee/variants/grunt: Enable BayHub720 driver
by Simon Glass (Code Review) 01 May '18

01 May '18

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/25967 Change subject: mb/google/kahlee/variants/grunt: Enable BayHub720 driver ...................................................................... mb/google/kahlee/variants/grunt: Enable BayHub720 driver Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 >From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg(a)chromium.org> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/grunt/devicetree.cb 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/25967/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 22925f4..24881b5 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -36,6 +36,7 @@ select SOC_AMD_PSP_SELECTABLE_SMU_FW select SOC_AMD_SMU_FANLESS select HAVE_ACPI_RESUME + select DRIVERS_GENERIC_BH720 if BOARD_GOOGLE_GRUNT if BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index cfc3198..0d4ad09 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -58,11 +58,16 @@ device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge + device pci 2.0 on end # PCIe Host Bridge device pci 2.1 on end # device pci 2.2 on end # device pci 2.3 on end # - device pci 2.4 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # device pci 2.5 on end # device pci 8.0 on end # PSP device pci 9.0 on end # PCIe Host Bridge -- To view, visit https://review.coreboot.org/25967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Gerrit-Change-Number: 25967 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Glass <sjg(a)chromium.org>

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Change in coreboot[master]: drivers/generic/bayhub: Add driver for BayHub BH720
by Simon Glass (Code Review) 01 May '18

01 May '18

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/25966 Change subject: drivers/generic/bayhub: Add driver for BayHub BH720 ...................................................................... drivers/generic/bayhub: Add driver for BayHub BH720 Add a driver which puts the device into power-saving mode. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- A src/drivers/generic/bayhub/Kconfig A src/drivers/generic/bayhub/Makefile.inc A src/drivers/generic/bayhub/bh720.c A src/drivers/generic/bayhub/chip.h M src/include/device/pci_ids.h 5 files changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/25966/1 diff --git a/src/drivers/generic/bayhub/Kconfig b/src/drivers/generic/bayhub/Kconfig new file mode 100644 index 0000000..882e8f9 --- /dev/null +++ b/src/drivers/generic/bayhub/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_BH720 + bool diff --git a/src/drivers/generic/bayhub/Makefile.inc b/src/drivers/generic/bayhub/Makefile.inc new file mode 100644 index 0000000..3458815 --- /dev/null +++ b/src/drivers/generic/bayhub/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_BH720) += bh720.c diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c new file mode 100644 index 0000000..cd9dd25 --- /dev/null +++ b/src/drivers/generic/bayhub/bh720.c @@ -0,0 +1,94 @@ +/* + * Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge + * + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +enum { + BH720_PROTECT = 0xd0, + BH720_PROTECT_OFF = 0, + BH720_PROTECT_ON = 1, + + BH720_RTD3_L1 = 0x3e0, + BH720_RTD3_L1_DISABLE_L1 = BIT(28), + + BH720_LINK_CTRL = 0x90, + BH720_LINK_CTRL_L0_ENABLE = BIT(0), + BH720_LINK_CTRL_L1_ENABLE = BIT(1), + BH720_LINK_CTRL_CLKREQ = BIT(8), +}; + +static void bh720_init(struct device *dev) +{ + struct drivers_generic_bayhub_config *config = dev->chip_info; + + pci_dev_init(dev); + + if (config && config->power_saving) { + /* + * This procedure for enabling power-saving mode is from the + * BayHub BIOS Implementation Guideline document. + */ + pci_write_config32(dev, BH720_PROTECT, BH720_PROTECT_OFF); + pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1); + pci_or_config32(dev, BH720_LINK_CTRL, + BH720_LINK_CTRL_L0_ENABLE | + BH720_LINK_CTRL_L1_ENABLE); + pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ); + pci_write_config32(dev, BH720_PROTECT, BH720_PROTECT_ON); + printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n", + pci_read_config32(dev, BH720_LINK_CTRL)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations bh720_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_ops, + .init = bh720_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_O2_BH720, + 0 +}; + +static const struct pci_driver bayhub_bh720 __pci_driver = { + .ops = &bh720_ops, + .vendor = PCI_VENDOR_ID_O2, + .devices = pci_device_ids, +}; + +static void bh720_enable(struct device *dev) +{ + dev->ops = &bh720_ops; +} + +struct chip_operations bayhub_bh720_ops = { + CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge") + .enable_dev = bh720_enable, +}; diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h new file mode 100644 index 0000000..a9254b8 --- /dev/null +++ b/src/drivers/generic/bayhub/chip.h @@ -0,0 +1,9 @@ +#include <arch/acpi_device.h> + +/* + * Bayhub BG720 PCI to eMMC bridge + */ +struct drivers_generic_bayhub_config { + /* 1 to enable power-saving mode, 0 to disable */ + int power_saving; +}; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7dc3e00..a0fcdda 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1688,6 +1688,7 @@ #define PCI_DEVICE_ID_O2_6730 0x673a #define PCI_DEVICE_ID_O2_6832 0x6832 #define PCI_DEVICE_ID_O2_6836 0x6836 +#define PCI_DEVICE_ID_O2_BH720 0x8620 #define PCI_VENDOR_ID_3DFX 0x121a #define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 -- To view, visit https://review.coreboot.org/25966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Gerrit-Change-Number: 25966 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Glass <sjg(a)chromium.org>

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Change in coreboot[master]: Documentation/Intel: Add MultiProcessorInit documentation
by Nico Huber (Code Review) 01 May '18

01 May '18

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Change in coreboot[master]: Documentation/Intel: Add MultiProcessorInit documentation
by Subrata Banik (Code Review) 01 May '18

01 May '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/25921 ) Change subject: Documentation/Intel: Add MultiProcessorInit documentation ...................................................................... Patch Set 3: > (4 comments) I agree with you on most this comments that you have put, but my only point is that, if i tries to put this implementation of creating EDK2 interface inside Coreboot to do certain thinks might not justify the purpose of adding those "foreign" interface as your words. Today coreboot code is so independent in nature so that we don;t need to talk help of such EDK2 interface to do certain things, if we really want to increase mp_init.c capability we could have done the same using native c why UEFI? UEFI is because this implementation only targeted for Intel fsp 9th gen + designs where we might want to do few things using coreboot callback from fsp, hence i could see a direct dependencies between this implementation proposal and supporting FSP model to justify that callback using SkipMpInit=0. if i make this code into common x86 place as well, no one will use this except 9th gen + socs from intel with proper FSP support. whats the point of keeping certain code into common when there are no user of that code expect intel native FSP support? Hope i could able to explain my concern, i have written this document so that i can keep it anywhere but myself not very convinced about why other users will interested to make use of EFI code interface inside x86/coreboot when mp_init.c is capable of doing everything without those APIs. -- To view, visit https://review.coreboot.org/25921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Gerrit-Change-Number: 25921 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Tue, 01 May 2018 12:34:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation/Intel: Add MultiProcessorInit documentation
by Nico Huber (Code Review) 01 May '18

01 May '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/25921 ) Change subject: Documentation/Intel: Add MultiProcessorInit documentation ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/#/c/25921/3/Documentation/Intel/MultiProcessorI… File Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md: https://review.coreboot.org/#/c/25921/3/Documentation/Intel/MultiProcessorI… PS3, Line 7: for Intel 9th Gen (Cannon Lake) and beyond CPUs > i have made this clear why we need to create this API interface in > this section. > > Although i agree this is very generic implementation and dependent > on mp_init.c so going forward we might feel a feed to make it > generic, today we can't do because it has some EDK2 header > dependencies which is only available for intel UDK2017 platform > (CNL onwards). I don't care. If somebody made a mess with these headers, fix it please. Something like "vendor x does weird stuff with API headers y" shouldn't stop progress of coreboot. On second thought, you don't have to do anything. A correct solu- tion would let the user decide, based on a properly guarded Kconfig option. And then you don't have any compilation conflicts because the code would simply not be compiled. > > btw, why you might need to have 2 document, i'm not going to > explain how mp_init works on x86 platform, those are already in > SDM, this document is to only talk about why we are creating EDK2 > interface in coreboot and how intel thinks this can help our > partners design. That's ok, I didn't mean a general document about MP init. Just in case you can figure out the header problem, the API documen- tation should be separated from the justification / Intel speci- fics. https://review.coreboot.org/#/c/25921/3/Documentation/Intel/MultiProcessorI… PS3, Line 25: closed source in nature > i don;t understand what you mean by can't be trusted ? It is my try to interpret English (I'm not a native speaker). I tried to make something up that "closed source in nature" could mean. If you would publish it, would it change its nature? That seems wrong to me. But I might just need help how the term "nature" is used in English. https://review.coreboot.org/#/c/25921/3/Documentation/Intel/MultiProcessorI… PS3, Line 35: It’s also possible for coreboot to extend its own : support model and create a sets of APIs which later can be used by FSP to run CPU feature : programming using coreboot published APIs > i guess you have missed problem statement, you are referring to proposal and try to understand why i […] Sorry I think we're talking past each other. Just this sentence alone. You say "coreboot [can] create a set of APIs which later can be used by FSP". I say, coreboot has created a set of APIs (cpu/x86/mp.h) and they can be published and used by FSP now. Those are two conflicting statements no matter the problem state- ment, AFAICS. https://review.coreboot.org/#/c/25921/3/Documentation/Intel/MultiProcessorI… PS3, Line 68: 1. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming. > not sure what you mean by coreboot? this is a UPD which is intel fsp specific. […] I meant "coreboot was using SkipMpInit=1" isn't true for all boards. coreboot has a setting "FspSkipMpInit" that is set per board in the devicetree. So a board maintainer already had the choice to enable MpInit in FSP. -- To view, visit https://review.coreboot.org/25921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Gerrit-Change-Number: 25921 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Tue, 01 May 2018 12:22:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit May 2018