coreboot-gerrit April 2018

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Change in coreboot[master]: libpayload: Move GDB functions to stdlib.h
by Julius Werner (Code Review) 19 Apr '18

19 Apr '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/25730 Change subject: libpayload: Move GDB functions to stdlib.h ...................................................................... libpayload: Move GDB functions to stdlib.h When GDB support is compiled in, halt() in libpayload will call gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in <libpayload.h>. Usually files just include <libpayload.h> so this is not a problem, but in some situatons a payload may just include <stdlib.h> (or a file including it like <assert.h>), leading to an undeclared identifier here. Move the GDB functions to <stdlib.h> to solve this. Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/stdlib.h 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/25730/1 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 83658d1..43ecd05 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -440,11 +440,6 @@ /* Defined in arch/${ARCH}/selfboot.c */ void selfboot(void *entry); -/* Enter remote GDB mode. Will initialize connection if not already up. */ -void gdb_enter(void); -/* Disconnect existing GDB connection if one exists. */ -void gdb_exit(s8 exit_status); - /* look for area "name" in "fmap", setting offset and size to describe it. Returns 0 on success, < 0 on error. */ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 658fe61..a2e612d 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -211,6 +211,11 @@ void srand(unsigned int seed); /** @} */ +/* Enter remote GDB mode. Will initialize connection if not already up. */ +void gdb_enter(void); +/* Disconnect existing GDB connection if one exists. */ +void gdb_exit(s8 exit_status); + /** * Stop execution and halt the processor (this function does not return). */ -- To view, visit https://review.coreboot.org/25730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071 Gerrit-Change-Number: 25730 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: commonlib/cbfs: Add hook function
by Philipp Deppenwiese (Code Review) 19 Apr '18

19 Apr '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/24967 ) Change subject: commonlib/cbfs: Add hook function ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/24967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ie5d51c1f5a353fbcdec3ce9b4c051c4621780582 Gerrit-Change-Number: 24967 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: lib/fmap: Add hook function.
by Philipp Deppenwiese (Code Review) 19 Apr '18

19 Apr '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/24966 ) Change subject: lib/fmap: Add hook function. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/24966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I699eec879e2c61976832c394b70cd6cfa5bae584 Gerrit-Change-Number: 24966 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/crypto: Add RSA signature verification support
by Philipp Deppenwiese (Code Review) 19 Apr '18

19 Apr '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/23218 ) Change subject: security/crypto: Add RSA signature verification support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/23218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ic58be92ad184cccaa8d6fc87d2c60bad63f3ec3b Gerrit-Change-Number: 23218 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/common/block/pi/heapmanager.c: Simplify code
by build bot (Jenkins) (Code Review) 19 Apr '18

19 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25703 ) Change subject: soc/amd/common/block/pi/heapmanager.c: Simplify code ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70332/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24556/ : SUCCESS -- To view, visit https://review.coreboot.org/25703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Gerrit-Change-Number: 25703 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 16:45:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by build bot (Jenkins) (Code Review) 19 Apr '18

19 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24905 ) Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70331/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24555/ : SUCCESS -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 15:43:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure
by build bot (Jenkins) (Code Review) 19 Apr '18

19 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25726 ) Change subject: soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70329/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24553/ : SUCCESS -- To view, visit https://review.coreboot.org/25726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Gerrit-Change-Number: 25726 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 15:20:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/vboot: Add interface for FSP 2.0 mrc caching
by build bot (Jenkins) (Code Review) 19 Apr '18

19 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Add interface for FSP 2.0 mrc caching ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70330/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24554/ : SUCCESS -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 15:15:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure
by Richard Spiegel (Code Review) 19 Apr '18

19 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25726 Change subject: soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure ...................................................................... soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/bootblock/bootblock.c M src/mainboard/amd/gardenia/gpio.c M src/mainboard/amd/gardenia/gpio.h M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/kahlee/gpio.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 11 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25726/1 diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index cb2a135..140bc07 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -21,7 +21,7 @@ void bootblock_mainboard_early_init(void) { size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; gpios = early_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index cb10e74..acd4edd 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -26,7 +26,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +const struct soc_amd_gpio gpio_set_stage_reset[] = { /* NFC PU */ PAD_GPO(GPIO_64, HIGH), /* PCIe presence detect */ @@ -47,7 +47,7 @@ PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), }; -const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +const struct soc_amd_gpio gpio_set_stage_ram[] = { /* BT radio disable */ PAD_GPO(GPIO_14, HIGH), /* NFC wake */ @@ -58,13 +58,13 @@ PAD_GPO(GPIO_70, HIGH), }; -const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size) +const struct soc_amd_gpio *early_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_reset); return gpio_set_stage_reset; } -const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size) +const struct soc_amd_gpio *gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index f386944..1d3a8a2 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -16,7 +16,7 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H -const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size); -const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size); +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 71fa257..9853803 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -81,7 +81,7 @@ static void mainboard_init(void *chip_info) { size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; gpios = gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 641287c..843bf4e 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -23,7 +23,7 @@ void bootblock_mainboard_early_init(void) { size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; /* Enable the EC as soon as we have visibility */ mainboard_ec_init(); diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e82569e..cd37c90 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -159,7 +159,7 @@ size_t num; int boardid = board_id(); size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; printk(BIOS_INFO, "Board ID: %d\n", boardid); diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 6b81b3e..1a03acd 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -25,7 +25,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = { +const static struct soc_amd_gpio gpio_set_stage_reset_old[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), @@ -196,7 +196,7 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +const static struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), @@ -370,7 +370,7 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = { +const static struct soc_amd_gpio gpio_set_stage_ram_old[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), @@ -429,7 +429,7 @@ PAD_GPI(GPIO_135, PULL_UP), }; -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +const static struct soc_amd_gpio gpio_set_stage_ram[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), @@ -486,7 +486,7 @@ }; const __attribute__((weak)) -struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) +struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { if (board_id() < 2) { *size = ARRAY_SIZE(gpio_set_stage_reset_old); @@ -498,7 +498,7 @@ } const __attribute__((weak)) -struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +struct soc_amd_gpio *variant_gpio_table(size_t *size) { if (board_id() < 2) { *size = ARRAY_SIZE(gpio_set_stage_ram_old); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index bc35ff5..fa74b56 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -29,8 +29,8 @@ int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); -const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size); -const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index 2f40546..a621a58 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -25,7 +25,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +const struct soc_amd_gpio gpio_set_stage_reset[] = { /* AGPIO2, to become event generator */ { GPIO_2, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, @@ -72,7 +72,7 @@ {GPIO_144, Function1, INPUT } }; -const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +const struct soc_amd_gpio gpio_set_stage_ram[] = { /* AGPIO 12 */ { GPIO_12, Function2, FCH_GPIO_PULL_UP_ENABLE | INPUT }, @@ -102,13 +102,13 @@ {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, }; -const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_reset); return gpio_set_stage_reset; } -const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index c0a48b3..5af9a6e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -352,7 +352,7 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) -struct soc_amd_stoneyridge_gpio { +struct soc_amd_gpio { uint8_t gpio; uint8_t function; uint8_t control; @@ -449,7 +449,7 @@ * * @return none */ -void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, +void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr, size_t size); /** * @brief Find the size of a particular wide IO diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a2a54c2..43d6f76 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -172,7 +172,7 @@ return irq_association; } -void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, +void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr, size_t size) { void *tmp_ptr; -- To view, visit https://review.coreboot.org/25726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Gerrit-Change-Number: 25726 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: pci: Add dummy file for ARM64
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25722 ) Change subject: pci: Add dummy file for ARM64 ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70327/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24551/ : SUCCESS -- To view, visit https://review.coreboot.org/25722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Gerrit-Change-Number: 25722 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 18 Apr 2018 13:30:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018