coreboot-gerrit April 2018

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Change in coreboot[master]: [WIP/TODO] arch/riscv: Configure delegation only in ramstage
by build bot (Jenkins) (Code Review) 23 Apr '18

23 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25791 ) Change subject: [WIP/TODO] arch/riscv: Configure delegation only in ramstage ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70562/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24774/ : SUCCESS -- To view, visit https://review.coreboot.org/25791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63 Gerrit-Change-Number: 25791 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Apr 2018 14:35:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Add HiFive Unleashed documentation
by build bot (Jenkins) (Code Review) 23 Apr '18

23 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25792 ) Change subject: Documentation: Add HiFive Unleashed documentation ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70563/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24775/ : SUCCESS -- To view, visit https://review.coreboot.org/25792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Gerrit-Change-Number: 25792 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Apr 2018 14:30:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/uart: Add a driver for SiFive's UART
by build bot (Jenkins) (Code Review) 23 Apr '18

23 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25768 ) Change subject: drivers/uart: Add a driver for SiFive's UART ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70558/ : SUCCESS -- To view, visit https://review.coreboot.org/25768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3 Gerrit-Change-Number: 25768 Gerrit-PatchSet: 5 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marcello Sylvester Bauer Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Mon, 23 Apr 2018 14:30:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/sifive: Add HiFive Unleashed mainboard
by build bot (Jenkins) (Code Review) 23 Apr '18

23 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25790 ) Change subject: mb/sifive: Add HiFive Unleashed mainboard ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70560/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/24773/ : SUCCESS -- To view, visit https://review.coreboot.org/25790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I52ef2da9148809923c90178a00ba94babba8d2f8 Gerrit-Change-Number: 25790 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Apr 2018 14:28:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/riscvtools: Rename to util/riscv/
by build bot (Jenkins) (Code Review) 23 Apr '18

23 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25700 ) Change subject: util/riscvtools: Rename to util/riscv/ ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24771/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/70559/ : SUCCESS -- To view, visit https://review.coreboot.org/25700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I515e2df3b87580ddd31d18fe63451a98e92ead61 Gerrit-Change-Number: 25700 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Apr 2018 14:28:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/sifive: Add the SiFive Freedom Unleashed 540 SoC
by build bot (Jenkins) (Code Review) 23 Apr '18

23 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25789 ) Change subject: src/sifive: Add the SiFive Freedom Unleashed 540 SoC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24772/ : SUCCESS -- To view, visit https://review.coreboot.org/25789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Gerrit-Change-Number: 25789 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Apr 2018 14:23:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/sifive: Add HiFive Unleashed mainboard
by Jonathan Neuschäfer (Code Review) 23 Apr '18

23 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25790 Change subject: mb/sifive: Add HiFive Unleashed mainboard ...................................................................... mb/sifive: Add HiFive Unleashed mainboard Change-Id: I52ef2da9148809923c90178a00ba94babba8d2f8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- A src/mainboard/sifive/Kconfig A src/mainboard/sifive/Kconfig.name A src/mainboard/sifive/hifive-unleashed/Kconfig A src/mainboard/sifive/hifive-unleashed/Kconfig.name A src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/board_info.txt A src/mainboard/sifive/hifive-unleashed/devicetree.cb A src/mainboard/sifive/hifive-unleashed/mainboard.c A src/mainboard/sifive/hifive-unleashed/memlayout.ld A src/mainboard/sifive/hifive-unleashed/romstage.c 10 files changed, 161 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/25790/1 diff --git a/src/mainboard/sifive/Kconfig b/src/mainboard/sifive/Kconfig new file mode 100644 index 0000000..1527705 --- /dev/null +++ b/src/mainboard/sifive/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SIFIVE + +choice + prompt "Mainboard model" + +source "src/mainboard/sifive/*/Kconfig.name" + +endchoice + +source "src/mainboard/sifive/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "SiFive" + +endif # VENDOR_SIFIVE diff --git a/src/mainboard/sifive/Kconfig.name b/src/mainboard/sifive/Kconfig.name new file mode 100644 index 0000000..4cc741e --- /dev/null +++ b/src/mainboard/sifive/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SIFIVE + bool "SiFive" diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig new file mode 100644 index 0000000..5e49f19 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -0,0 +1,33 @@ +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Jonathan Neuschäfer +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +if BOARD_SIFIVE_HIFIVE_UNLEASHED + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_SIFIVE_FU540 + select BOARD_ROMSIZE_KB_32768 + +config MAINBOARD_DIR + string + default sifive/hifive-unleashed + +config MAX_CPUS + int + default 4 + +config MAINBOARD_PART_NUMBER + string + default "HiFive Unleashed" + +endif diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig.name b/src/mainboard/sifive/hifive-unleashed/Kconfig.name new file mode 100644 index 0000000..1ee3793 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIFIVE_HIFIVE_UNLEASHED + bool "HiFive Unleashed" diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc new file mode 100644 index 0000000..27ddcba --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -0,0 +1,18 @@ +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Jonathan Neuschäfer +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +romstage-y += romstage.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/sifive/hifive-unleashed/board_info.txt b/src/mainboard/sifive/hifive-unleashed/board_info.txt new file mode 100644 index 0000000..7d3e171 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/board_info.txt @@ -0,0 +1,5 @@ +ROM package: SOIC-16 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Board URL: https://www.crowdsupply.com/sifive/hifive-unleashed diff --git a/src/mainboard/sifive/hifive-unleashed/devicetree.cb b/src/mainboard/sifive/hifive-unleashed/devicetree.cb new file mode 100644 index 0000000..1c9f79a --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/devicetree.cb @@ -0,0 +1,16 @@ +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Jonathan Neuschäfer +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +chip soc/sifive/fu540 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/sifive/hifive-unleashed/mainboard.c b/src/mainboard/sifive/hifive-unleashed/mainboard.c new file mode 100644 index 0000000..ab4d6ae --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <timestamp.h> + +static void mainboard_enable(device_t dev) +{ +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sifive/hifive-unleashed/memlayout.ld b/src/mainboard/sifive/hifive-unleashed/memlayout.ld new file mode 100644 index 0000000..d1a6d65 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c new file mode 100644 index 0000000..b30b736 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <program_loading.h> + +void main(void) +{ + console_init(); + + /* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */ + + run_ramstage(); +} -- To view, visit https://review.coreboot.org/25790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I52ef2da9148809923c90178a00ba94babba8d2f8 Gerrit-Change-Number: 25790 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: [WIP/TODO] arch/riscv: Configure delegation only in ramstage
by Jonathan Neuschäfer (Code Review) 23 Apr '18

23 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25791 Change subject: [WIP/TODO] arch/riscv: Configure delegation only in ramstage ...................................................................... [WIP/TODO] arch/riscv: Configure delegation only in ramstage On the FU540 the bootblock runs on a core without lesser privilege modes, so the medeleg/mideleg CSRs are not implemented on that core. Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/virtual_memory.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/25791/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 3bee868..7830519 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -54,9 +54,10 @@ // Delegate supervisor timer and other interrupts // to supervisor mode. - set_csr(mideleg, MIP_STIP | MIP_SSIP); + //set_csr(mideleg, MIP_STIP | MIP_SSIP); - set_csr(medeleg, delegate); + //set_csr(medeleg, delegate); + (void)delegate; // Enable all user/supervisor-mode counters using // v1.10 register addresses. -- To view, visit https://review.coreboot.org/25791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63 Gerrit-Change-Number: 25791 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: Documentation: Add HiFive Unleashed documentation
by Jonathan Neuschäfer (Code Review) 23 Apr '18

23 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25792 Change subject: Documentation: Add HiFive Unleashed documentation ...................................................................... Documentation: Add HiFive Unleashed documentation Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- A Documentation/mainboard/sifive/hifive-unleashed.md 1 file changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/25792/1 diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md new file mode 100644 index 0000000..87641d1 --- /dev/null +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -0,0 +1,104 @@ +# SiFive HiFive Unleashed + +This page describes how to run coreboot on the [HiFive Unleashed] development +board from [SiFive], the first RISC-V board on the market with enough resources +to run a multiuser operating system. + +For general setup instructions, please refer to the [Getting Started Guide]. + + +## TODO + +The following things are still missing from this coreboot port: + +- Trampoline in the MBR block to support boot mode 1 +- SiFive UART driver +- CBMEM support +- FU540 clock configuration +- FU540 RAM init +- Placing the ramstage in DRAM +- Starting the U54 cores +- FU540 PIN configuration and GPIO access macros +- FU540 OTP driver and serial number read-out +- Support for booting Linux on RISC-V + + +## Configuration + +Run `make menuconfig` and select _SiFive_/_HiFive Unleashed_ in the Mainboard +menu. + + +### Boot modes + +A total of 16 boot modes can be configured using the switches labeled `MSEL0` +through `MSEL3`. The most important ones are as follows: + +- **MSEL=1**: Jump directly into the SPI flash, bypassing ROM1 +- **MSEL=11**: Load FSBL from SD-card +- **MSEL=15**: Default boot mode; Load FSBL/coreboot from a GPT partition on + SPI flash + + +## Flashing coreboot + +The HiFive Unleashed has an **ISSI IS25WP256D** SPI flash, that can be programmed +from within Linux running on the board, via USB/JTAG, or directly with an SPI +programmer. + +### Internal programming + +The SPI flash can be accessed as `/dev/mtd0` from Linux. + +### USB/JTAG + +To program the flash via USB/JTAG, connect the USB port to a computer; If the +board is powered on, two new serial ports, for example `/dev/ttyUSB0` and +`/dev/ttyUSB1` will appear. The first is JTAG, and the second is connected to +the SoC's UART. + +- Download and build the [RISC-V fork of OpenOCD]. +- Download the [OpenOCD script] for Freedom Unleashed. +- Start OpenOCD with `openocd -f openocd.cfg` +- Connect to OpenOCD's command interface (via telnet) and enter the line + marked with `> `: +``` +> flash write_image erase unlock build/coreboot.rom 0x20000000 +auto erase enabled +auto unlock enabled +wrote 33554432 bytes from file build/coreboot.rom in 1524.943848s (21.488 KiB/s) +``` + Note that programming the whole flash with OpenOCD isn't fast. In this + example it took just over 25 minutes. This process can be sped up + considerably by building/flashing a smaller image; OpenOCD does not check if + the image and the flash have the same size. + + +### External programming + +External programming with a SPI adapter and [flashrom] may work, but has not +been tested. Please study the [schematics] before going this route. + + +## Error codes + +The zeroth-stage bootloader (ZSBL) in ROM1 can print error codes on the serial +console, in certain situations. + +``` +// Error codes are formatted as follows: +// [63:60] [59:56] [55:0] +// bootstage trap errorcode +// If trap == 1, then errorcode is actually the mcause register with the +// interrupt bit shifted to bit 55. +``` +(--- from the [SiFive forum](https://forums.sifive.com/t/loading-fsbl-from-sd/1156/4)) + + +[HiFive Unleashed]: https://www.crowdsupply.com/sifive/hifive-unleashed +[SiFive]: https://www.sifive.com/ +[Getting Started Guide]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleash… +[RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd +[OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a… +[flashrom]: https://flashrom.org/Flashrom +[schematics]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleash… -- To view, visit https://review.coreboot.org/25792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Gerrit-Change-Number: 25792 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: src/sifive: Add the SiFive Freedom Unleashed 540 SoC
by Jonathan Neuschäfer (Code Review) 23 Apr '18

23 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25789 Change subject: src/sifive: Add the SiFive Freedom Unleashed 540 SoC ...................................................................... src/sifive: Add the SiFive Freedom Unleashed 540 SoC The FU540 is the first RISC-V SoC with the necessary resources to run Linux (an external memory interface, MMU, etc). More information is available on SiFive's website: https://www.sifive.com/products/hifive-unleashed/ Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- A src/soc/sifive/Kconfig A src/soc/sifive/fu540/Kconfig A src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/bootblock.c A src/soc/sifive/fu540/cbmem.c A src/soc/sifive/fu540/include/soc/addressmap.h A src/soc/sifive/fu540/include/soc/memlayout.ld A src/soc/sifive/fu540/media.c A src/soc/sifive/fu540/uart.c A util/riscv/sifive-gpt.py 10 files changed, 407 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25789/1 diff --git a/src/soc/sifive/Kconfig b/src/soc/sifive/Kconfig new file mode 100644 index 0000000..14900be --- /dev/null +++ b/src/soc/sifive/Kconfig @@ -0,0 +1,2 @@ +# Load all chipsets +source "src/soc/sifive/*/Kconfig" diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig new file mode 100644 index 0000000..d247c28 --- /dev/null +++ b/src/soc/sifive/fu540/Kconfig @@ -0,0 +1,26 @@ +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Jonathan Neuschäfer +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +config SOC_SIFIVE_FU540 + bool + select ARCH_RISCV + select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select BOOTBLOCK_CONSOLE + select DRIVERS_UART_SIFIVE + +if SOC_SIFIVE_FU540 + +endif diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc new file mode 100644 index 0000000..8a2f3a6 --- /dev/null +++ b/src/soc/sifive/fu540/Makefile.inc @@ -0,0 +1,33 @@ +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Jonathan Neuschäfer +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +ifeq ($(CONFIG_SOC_SIFIVE_FU540),y) + +bootblock-y += uart.c +bootblock-y += media.c +bootblock-y += bootblock.c + +romstage-y += uart.c +romstage-y += media.c + +ramstage-y += uart.c +ramstage-y += media.c +ramstage-y += cbmem.c + +CPPFLAGS_common += -Isrc/soc/sifive/fu540/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf " GPT $(notdir $(@))\n" + @util/riscv/sifive-gpt.py $< $@ + +endif diff --git a/src/soc/sifive/fu540/bootblock.c b/src/soc/sifive/fu540/bootblock.c new file mode 100644 index 0000000..203081c --- /dev/null +++ b/src/soc/sifive/fu540/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <soc/addressmap.h> + +void bootblock_soc_init(void) +{ + printk(BIOS_INFO, "Boot mode: %d\n", read32((uint32_t *)FU540_MSEL)); +} diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c new file mode 100644 index 0000000..8648370 --- /dev/null +++ b/src/soc/sifive/fu540/cbmem.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + /* dummy value */ + return (void *)(4ULL * GiB); +} diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h new file mode 100644 index 0000000..904c8b6 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/addressmap.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define FU540_MSEL 0x00001000 +#define FU540_DTIM 0x01000000 +#define FU540_L2LIM 0x08000000 +#define FU540_UART0 0x10010000 +#define FU540_UART(x) (FU540_UART0 + 0x1000 * (x)) +#define FU540_PRCI 0x10000000 +#define FU540_QSPI0 0x10040000 +#define FU540_QSPI1 0x10041000 +#define FU540_QSPI2 0x10050000 +#define FU540_GPIO 0x10060000 +#define FU540_OTP 0x10070000 +#define FU540_PINCTRL 0x10080000 +#define FU540_ETHMAC 0x10090000 +#define FU540_ETHMGMT 0x100a0000 +#define FU540_DDRCTRL 0x100b0000 +#define FU540_DDRMGMT 0x100c0000 +#define FU540_QSPI0FLASH 0x20000000 +#define FU540_QSPI1FLASH 0x30000000 +#define FU540_DRAM 0x80000000 diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld new file mode 100644 index 0000000..a03c03d --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <soc/addressmap.h> + +#include <arch/header.ld> + +#define L2LIM_START(addr) SYMBOL(l2lim, addr) +#define L2LIM_END(addr) SYMBOL(el2lim, addr) + +SECTIONS +{ + L2LIM_START(FU540_L2LIM) + BOOTBLOCK(FU540_L2LIM, 64K) + STACK(FU540_L2LIM + 64K, 4K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K) + ROMSTAGE(FU540_L2LIM + 128K, 128K) + L2LIM_END(FU540_L2LIM + 2M) + + DRAM_START(FU540_DRAM) + RAMSTAGE(FU540_DRAM, 256K) +} diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c new file mode 100644 index 0000000..7b9ccb0 --- /dev/null +++ b/src/soc/sifive/fu540/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> + +/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ +static struct mem_region_device mdev = + MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &mdev.rdev; +} diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c new file mode 100644 index 0000000..940dc97 --- /dev/null +++ b/src/soc/sifive/fu540/uart.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <soc/addressmap.h> + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 2) + return FU540_UART(idx); + else + return 0; +} diff --git a/util/riscv/sifive-gpt.py b/util/riscv/sifive-gpt.py new file mode 100755 index 0000000..cb77302 --- /dev/null +++ b/util/riscv/sifive-gpt.py @@ -0,0 +1,181 @@ +#!/usr/bin/python3 +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Jonathan Neuschäfer +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +import sys, os, struct, uuid, zlib, io + +# This script wraps the bootblock in a GPT partition, because that's what +# SiFive's bootrom will load. + + +# Size of a GPT disk block, in bytes +BLOCK_SIZE = 512 +BLOCK_MASK = BLOCK_SIZE - 1 + +# Size of the bootcode part of the MBR +MBR_BOOTCODE_SIZE = 0x1be + +# A protecive MBR, without the bootcode part +PROTECTIVE_MBR_FOOTER = bytes([ + 0x00, 0x00, 0x02, 0x00, 0xee, 0xff, 0xff, 0xff, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x55, 0xaa +]) + + +# A "protective MBR"[1], which may also contain some boot code. +# [1]: https://en.wikipedia.org/wiki/GUID_Partition_Table#PROTECTIVE-MBR +class ProtectiveMBR: + def __init__(self): + self.bootcode = bytes(MBR_BOOTCODE_SIZE) + + def generate(self, stream): + assert len(self.bootcode) == MBR_BOOTCODE_SIZE + mbr = self.bootcode + PROTECTIVE_MBR_FOOTER + assert len(mbr) == BLOCK_SIZE + stream.write(mbr) + + +# Generate a GUID from a string +class GUID(uuid.UUID): + def __init__(self, string): + super().__init__(string) + + def get_bytes(self): + return self.bytes_le + +DUMMY_GUID_DISK_UNIQUE = GUID('17145242-abaa-441d-916a-3f26c970aba2') +DUMMY_GUID_PART_UNIQUE = GUID('7552133d-c8de-4a20-924c-0e85f5ea81f2') +GUID_TYPE_FSBL = GUID('5B193300-FC78-40CD-8002-E86C45580B47') + + +# A GPT disk header +# https://en.wikipedia.org/wiki/GUID_Partition_Table#Partition_table_header_(… +class GPTHeader: + def __init__(self): + self.current_lba = 1 + self.backup_lba = 1 + self.first_usable_lba = 2 + self.last_usable_lba = 0xff # dummy value + self.uniq = DUMMY_GUID_DISK_UNIQUE + self.part_entries_lba = 2 + self.part_entries_number = 0 + self.part_entries_crc32 = 0 + self.part_entry_size = 128 + + def pack_with_crc(self, crc): + header_size = 92 + header = struct.pack('<8sIIIIQQQQ16sQIII', + b'EFI PART', 0x100, header_size, crc, 0, + self.current_lba, self.backup_lba, self.first_usable_lba, + self.last_usable_lba, self.uniq.get_bytes(), + self.part_entries_lba, self.part_entries_number, + self.part_entry_size, self.part_entries_crc32) + assert len(header) == header_size + return header + + def generate(self, stream): + crc = zlib.crc32(self.pack_with_crc(0)) + header = self.pack_with_crc(crc) + stream.write(header.ljust(BLOCK_SIZE, b'\0')) + + +# A GPT partition entry. +# https://en.wikipedia.org/wiki/GUID_Partition_Table#Partition_entries_(LBA_2… +class GPTPartition: + def __init__(self): + self.type = GUID('00000000-0000-0000-0000-000000000000') + self.uniq = GUID('00000000-0000-0000-0000-000000000000') + self.first_lba = 0 + self.last_lba = 0 + self.attr = 0 + self.name = '' + + def generate(self, stream): + name_utf16 = self.name.encode('UTF-16LE') + part = struct.pack('<16s16sQQQ72s', + self.type.get_bytes(), self.uniq.get_bytes(), + self.first_lba, self.last_lba, self.attr, + name_utf16.ljust(72, b'\0')) + assert len(part) == 128 + stream.write(part) + + +class GPTImage: + # The final image consists of: + # - A protective MBR + # - A GPT header + # - A few GPT partition entries + # - The content of the bootblock + def __init__(self): + self.mbr = ProtectiveMBR() + self.header = GPTHeader() + self.partitions = [ GPTPartition() for i in range(8) ] + self.bootblock = b'' + + + # Fix up a few numbers to ensure consistency between the different + # components. + def fixup(self): + # Align the bootblock to a whole number to LBA blocks + bootblock_size = (len(self.bootblock) + BLOCK_SIZE - 1) & ~BLOCK_MASK + self.bootblock = self.bootblock.ljust(bootblock_size) + + # Propagate the number of partition entries + self.header.part_entries_number = len(self.partitions) + self.header.first_usable_lba = 2 + self.header.part_entries_number // 4 + + # Create a partition entry for the bootblock + self.partitions[0].type = GUID_TYPE_FSBL + self.partitions[0].uniq = DUMMY_GUID_PART_UNIQUE + self.partitions[0].first_lba = self.header.first_usable_lba + self.partitions[0].last_lba = \ + self.header.first_usable_lba + bootblock_size // BLOCK_SIZE + + # Calculate the CRC32 checksum of the partitions array + partition_array = io.BytesIO() + for part in self.partitions: + part.generate(partition_array) + self.header.part_entries_crc32 = zlib.crc32(partition_array.getvalue()) + + + def generate(self, stream): + self.mbr.generate(stream) + self.header.generate(stream) + for part in self.partitions: + part.generate(stream) + stream.write(self.bootblock) + + +if __name__ == '__main__': + if len(sys.argv) != 3: + print('Usage:', file=sys.stderr) + print(' %s bootblock.raw.bin bootblock.bin' % sys.argv[0], + file=sys.stderr) + sys.exit(1) + + image = GPTImage() + + with open(sys.argv[1], 'rb') as f: + image.bootblock = f.read() + + image.fixup() + + with open(sys.argv[2], 'wb') as f: + image.generate(f) -- To view, visit https://review.coreboot.org/25789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Gerrit-Change-Number: 25789 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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coreboot-gerrit April 2018