coreboot-gerrit January 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/kahlee: Add grunt trackpad in devicetree
by build bot (Jenkins) (Code Review) 30 Jan '18

30 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23508 ) Change subject: mb/google/kahlee: Add grunt trackpad in devicetree ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21396/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66798/ : SUCCESS -- To view, visit https://review.coreboot.org/23508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Gerrit-Change-Number: 23508 Gerrit-PatchSet: 2 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Jan 2018 18:08:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Fix common timer frequency
by build bot (Jenkins) (Code Review) 30 Jan '18

30 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23509 ) Change subject: soc/intel/skylake: Fix common timer frequency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21397/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66799/ : SUCCESS -- To view, visit https://review.coreboot.org/23509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335 Gerrit-Change-Number: 23509 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Jan 2018 18:08:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/eve: Enable HotPlug on PCIe root port for WiFi
by Duncan Laurie (Code Review) 30 Jan '18

30 Jan '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/23512 Change subject: mb/google/eve: Enable HotPlug on PCIe root port for WiFi ...................................................................... mb/google/eve: Enable HotPlug on PCIe root port for WiFi Enable HotPlug for the PCIe root port that the WiFi device is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/23512/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 2880066..2e62f41 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -146,6 +146,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" #RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" -- To view, visit https://review.coreboot.org/23512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799 Gerrit-Change-Number: 23512 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Add devicetree variable for PCIe HotPlug
by Duncan Laurie (Code Review) 30 Jan '18

30 Jan '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/23511 Change subject: soc/intel/skylake: Add devicetree variable for PCIe HotPlug ...................................................................... soc/intel/skylake: Add devicetree variable for PCIe HotPlug Add a variable to fill out the FSP UPD variable for PCIe HotPlug, which allows a mainboard to enable HotPlug on individual root ports. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 3 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/23511/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8002270..f60c08d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -121,6 +121,8 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug)); params->EnableLan = config->EnableLan; params->Cio2Enable = config->Cio2Enable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4e8cb81..b019631 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -218,6 +218,9 @@ */ u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Enable/Disable HotPlug support for Root Port */ + u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ccda303..98a1abd 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -165,6 +165,8 @@ sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug)); /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for -- To view, visit https://review.coreboot.org/23511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 Gerrit-Change-Number: 23511 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Always add PM1_TMR block to FADT
by Duncan Laurie (Code Review) 30 Jan '18

30 Jan '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/23510 Change subject: soc/intel/skylake: Always add PM1_TMR block to FADT ...................................................................... soc/intel/skylake: Always add PM1_TMR block to FADT Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/acpi.c 1 file changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23510/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 61360da..0839927 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -247,16 +247,14 @@ fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; - if (config->PmTimerDisabled == 0) - fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; - if (config->PmTimerDisabled == 0) - fadt->pm_tmr_len = 4; + fadt->pm_tmr_len = 4; /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; @@ -323,14 +321,12 @@ fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - if (config->PmTimerDisabled == 0) { - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - } + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 0; fadt->x_gpe0_blk.bit_width = 0; -- To view, visit https://review.coreboot.org/23510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8 Gerrit-Change-Number: 23510 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Fix common timer frequency
by Duncan Laurie (Code Review) 30 Jan '18

30 Jan '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/23509 Change subject: soc/intel/skylake: Fix common timer frequency ...................................................................... soc/intel/skylake: Fix common timer frequency The calculation to set up the PM timer emulation is using an incorrect common timer clock value that was copied from Apollolake. According to the PDG Skylake and Kabylake clocks are derived from a 24MHz XTAL, not 19.2MHz like Apollolake. Fixing this value results in the proper "correction value" to be programmed into the PM timer emulation MSR that matches the raw value that would be programmed by FSP. (if it were doing MpInit) Old PM timer correction value: 0x2fba2e25 New PM timer correction value: 0x262e8b51 Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/include/soc/cpu.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/23509/1 diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 8073fcd..cc76b19 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -40,8 +40,8 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 19.2MHz. */ -#define CTC_FREQ 19200000 +/* Common Timer Copy (CTC) frequency - 24MHz. */ +#define CTC_FREQ 24000000 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) -- To view, visit https://review.coreboot.org/23509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335 Gerrit-Change-Number: 23509 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: mb/google/kahlee: Add grunt trackpad in devicetree
by build bot (Jenkins) (Code Review) 30 Jan '18

30 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23508 ) Change subject: mb/google/kahlee: Add grunt trackpad in devicetree ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66797/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21395/ : SUCCESS -- To view, visit https://review.coreboot.org/23508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Gerrit-Change-Number: 23508 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Jan 2018 18:00:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Add grunt trackpad in devicetree
by Justin TerAvest (Code Review) 30 Jan '18

30 Jan '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23508 Change subject: mb/google/kahlee: Add grunt trackpad in devicetree ...................................................................... mb/google/kahlee: Add grunt trackpad in devicetree This commit removes a manually written asl file in favor of configuring the trackpad through devicetree. BUG=b:72121803 TEST=cat /proc/interrupts with trackpad connected Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/23508/1 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index d2453a1..22c3653 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -81,6 +81,15 @@ device pci 18.4 on end device pci 18.5 on end end #domain + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + # TODO(teravest): Add wake + device i2c 15 on end + end + end device mmio 0xfedc5000 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl index 900a838..4f91d72 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl @@ -15,4 +15,3 @@ #include <baseboard/acpi/mainboard.asl> #include <baseboard/acpi/audio.asl> -#include <baseboard/acpi/touchpad.asl> -- To view, visit https://review.coreboot.org/23508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Gerrit-Change-Number: 23508 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: mb/google/kahlee: Add grunt trackpad in devicetree
by Justin TerAvest (Code Review) 30 Jan '18

30 Jan '18

Justin TerAvest has abandoned this change. ( https://review.coreboot.org/23507 ) Change subject: mb/google/kahlee: Add grunt trackpad in devicetree ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/23507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I8977090bdf07cd2f28265317a53dd82196a3fe9a Gerrit-Change-Number: 23507 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: mb/google/kahlee: Add grunt trackpad in devicetree
by Justin TerAvest (Code Review) 30 Jan '18

30 Jan '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23507 Change subject: mb/google/kahlee: Add grunt trackpad in devicetree ...................................................................... mb/google/kahlee: Add grunt trackpad in devicetree This commit removes a manually written asl file in favor of configuring the trackpad through devicetree. BUG=b:72121803 TEST=cat /proc/interrupts with trackpad connected Change-Id: I8977090bdf07cd2f28265317a53dd82196a3fe9a Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/23507/1 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index d2453a1..22c3653 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -81,6 +81,15 @@ device pci 18.4 on end device pci 18.5 on end end #domain + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + # TODO(teravest): Add wake + device i2c 15 on end + end + end device mmio 0xfedc5000 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl index 900a838..4f91d72 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl @@ -15,4 +15,3 @@ #include <baseboard/acpi/mainboard.asl> #include <baseboard/acpi/audio.asl> -#include <baseboard/acpi/touchpad.asl> -- To view, visit https://review.coreboot.org/23507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8977090bdf07cd2f28265317a53dd82196a3fe9a Gerrit-Change-Number: 23507 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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coreboot-gerrit January 2018