Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/23496
to look at the new patch set (#2).
Change subject: [WIP,NOTFORMERGE]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
[WIP,NOTFORMERGE]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK
When the rom is cached in bootblock, ramstage currently fails to
run properly. If no mtrr covers the ROM it boots fine, but ofc
romstage will be terribly slow...
Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/Makefile.inc
A src/cpu/intel/car/bootblock.c
M src/cpu/intel/car/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/car/teardown_car.S
M src/cpu/intel/common/Kconfig
M src/cpu/intel/common/Makefile.inc
A src/cpu/intel/common/util.c
A src/cpu/intel/common/util.h
M src/cpu/intel/socket_441/Kconfig
M src/mainboard/intel/d945gclf/Makefile.inc
A src/mainboard/intel/d945gclf/bootblock.c
M src/mainboard/intel/d945gclf/romstage.c
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/i945/ram_calc.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/superio/smsc/lpc47m15x/Makefile.inc
19 files changed, 426 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23496/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861
Gerrit-Change-Number: 23496
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23502
Change subject: [RFC]drivers/intel/gma: Add common devicetree structure
......................................................................
[RFC]drivers/intel/gma: Add common devicetree structure
Add a platform independend structure to hold all required GPU related
information. Every field has a clear description and usage.
Instead of using the northbridge device, the new field will be attached
to the GMA device.
To be used on all Intel platforms.
Change-Id: I29c5090a21537f823d14bda2b1d5f03dd8d58c1c
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
A src/drivers/intel/gma/chip.h
1 file changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/23502/1
diff --git a/src/drivers/intel/gma/chip.h b/src/drivers/intel/gma/chip.h
new file mode 100644
index 0000000..b05ebe5
--- /dev/null
+++ b/src/drivers/intel/gma/chip.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com>
+ * Copyright (C) 2012 Duncan Laurie <dlaurie(a)google.com>
+ * Copyright (C) 2012 Stefan Reinauer <reinauer(a)google.com>
+ * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _INTEL_GMA_CHIP_H_
+#define _INTEL_GMA_CHIP_H_
+
+struct drivers_intel_gma_config {
+ /* Optional: Non default register for SWSMI / SWSCI */
+ u8 reg_swsmisci;
+ /* Enable spread spectrum control */
+ u8 use_spread_spectrum_clock;
+ /* Use 270 Mhz link frequency */
+ u8 link_frequency_270_mhz;
+ /* Enable CRT connector */
+ u8 use_crt;
+ /* Enable LVDS connector */
+ u8 use_lvds;
+
+ /*
+ * Digital Port Hotplug Enable:
+ * 0x04 = Enabled, 2ms short pulse
+ * 0x05 = Enabled, 4.5ms short pulse
+ * 0x06 = Enabled, 6ms short pulse
+ * 0x07 = Enabled, 100ms short pulse
+ */
+ u8 dp_b_hotplug; /* Digital Port B Hotplug Config */
+ u8 dp_c_hotplug; /* Digital Port C Hotplug Config */
+ u8 dp_d_hotplug; /* Digital Port D Hotplug Config */
+
+ u8 panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
+ u8 panel_power_cycle_delay; /* T4 time sequence */
+ u16 panel_power_up_delay; /* T1+T2 time sequence */
+ u16 panel_power_down_delay; /* T3 time sequence */
+ u16 panel_power_backlight_on_delay; /* T5 time sequence */
+ u16 panel_power_backlight_off_delay; /* Tx time sequence */
+
+ u32 cpu_backlight; /* CPU Backlight PWM value */
+ u32 pch_backlight; /* PCH Backlight PWM value */
+
+ /* Hot-pluggable connectors */
+ u32 hotplug;
+
+ /*
+ * Default panel brightness level in percent.
+ * If zero the value is ignored.
+ */
+ u8 duty_cycle;
+
+ /* Number of devices attached to display adapter. Up to 5 */
+ u8 ndid;
+ /* Devices attached to display adapter */
+ u32 did[5];
+};
+
+
+#endif /* _INTEL_GMA_CHIP_H_ */
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I29c5090a21537f823d14bda2b1d5f03dd8d58c1c
Gerrit-Change-Number: 23502
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>