Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/23511
Change subject: soc/intel/skylake: Add devicetree variable for PCIe HotPlug ......................................................................
soc/intel/skylake: Add devicetree variable for PCIe HotPlug
Add a variable to fill out the FSP UPD variable for PCIe HotPlug, which allows a mainboard to enable HotPlug on individual root ports.
BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port.
Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 Signed-off-by: Duncan Laurie dlaurie@chromium.org --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 3 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/23511/1
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8002270..f60c08d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -121,6 +121,8 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug));
params->EnableLan = config->EnableLan; params->Cio2Enable = config->Cio2Enable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4e8cb81..b019631 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -218,6 +218,9 @@ */ u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+ /* Enable/Disable HotPlug support for Root Port */ + u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ccda303..98a1abd 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -165,6 +165,8 @@ sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug));
/* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for