coreboot-gerrit May 2017

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Change in coreboot[master]: nb/intel/x4x/raminit: Make programming launch ddr3 specific
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19872 ) Change subject: nb/intel/x4x/raminit: Make programming launch ddr3 specific ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10131/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54408/ : SUCCESS -- To view, visit https://review.coreboot.org/19872 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Add DDR3 rcomp
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19875 ) Change subject: nb/intel/x4x: Add DDR3 rcomp ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10134/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54411/ : SUCCESS -- To view, visit https://review.coreboot.org/19875 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: DDR3 specific ODT
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19876 ) Change subject: nb/intel/x4x/raminit: DDR3 specific ODT ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10135/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54412/ : SUCCESS -- To view, visit https://review.coreboot.org/19876 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Make programming crossclock suppo...
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19871 ) Change subject: [WIP]nb/intel/x4x/raminit: Make programming crossclock support DDR3 ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10129/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54407/ : SUCCESS -- To view, visit https://review.coreboot.org/19871 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Support programming DDR3 timings
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19873 ) Change subject: nb/intel/x4x/raminit: Support programming DDR3 timings ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10132/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54409/ : SUCCESS -- To view, visit https://review.coreboot.org/19873 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Rename a things that are not ddr2 specific
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19870 ) Change subject: nb/intel/x4x: Rename a things that are not ddr2 specific ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10130/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54406/ : SUCCESS -- To view, visit https://review.coreboot.org/19870 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Support programming initials DD3 DLL s...
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19874 ) Change subject: nb/intel/x4x/raminit: Support programming initials DD3 DLL setting ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10133/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54410/ : SUCCESS -- To view, visit https://review.coreboot.org/19874 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia79b216ad69a02d4706ffc74f867a85db3eb2d6c Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: pciexp_device: Prevent race condition with retrain link
by Arthur Heymans (Code Review) 25 May '17

25 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19556 ) Change subject: pciexp_device: Prevent race condition with retrain link ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/19556 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Limit DDR3 to 400MHz
by Arthur Heymans (Code Review) 25 May '17

25 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19919 ) Change subject: nb/intel/x4x/raminit: Limit DDR3 to 400MHz ...................................................................... nb/intel/x4x/raminit: Limit DDR3 to 400MHz Faster does not seem to boot, while limiting it to this frequency makes it reliable. TESTED on Asrock g41c-gs with 1 1Rx8 2G in both channels; on Gigabyte ga-g41mt-es2l (with ga-g41m-es2l code) with 2G, 2+4G, 4+4G even with ECC DIMMs on which vendor bails out. (ECC is not supported) Change-Id: I120b22ca8febc5a3644339045218e997d8e8496e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/spd_ddr3_decode.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19919/1 diff --git a/src/northbridge/intel/x4x/spd_ddr3_decode.c b/src/northbridge/intel/x4x/spd_ddr3_decode.c index eab0548..0a99e4d 100644 --- a/src/northbridge/intel/x4x/spd_ddr3_decode.c +++ b/src/northbridge/intel/x4x/spd_ddr3_decode.c @@ -82,6 +82,7 @@ } min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); + min_tCLK = TCK_400MHZ; /* FIXME: faster frequency fail */ normalize_tCLK(&min_tCLK); if (min_tCLK == 0) { printk(BIOS_ERR, "DRAM frequency is under lowest supported " -- To view, visit https://review.coreboot.org/19919 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I120b22ca8febc5a3644339045218e997d8e8496e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Adapt post JEDEC for DDR3
by Arthur Heymans (Code Review) 25 May '17

25 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19918 ) Change subject: nb/intel/x4x: Adapt post JEDEC for DDR3 ...................................................................... nb/intel/x4x: Adapt post JEDEC for DDR3 Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/19918/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index fab0df6..b5fcbd8 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -2338,10 +2338,19 @@ // After JEDEC reset MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) - reg32 = (2 << 18) | (3 << 13) | (5 << 8); - else - reg32 = (2 << 18) | (3 << 13) | (4 << 8); + reg32 = 0; + reg32 |= (2 << 18); + reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] + [s->selected_timings.mem_clk][0] << 13; + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && + s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && + ch == 1) { + reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk] + [s->selected_timings.mem_clk][1] - 1) << 8; + } else { + reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] + [s->selected_timings.mem_clk][1] << 8; + } MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32; MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80; MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index fabfe18..55ec708 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -247,6 +247,23 @@ {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */ }; +const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */ +{ /* FSB DDR */ + {{0x3, 0x5}, /* 800 667 */ + {0x3, 0x4}, /* 800 800 */ + }, + {{0x4, 0x8}, /* 1067 667 */ + {0x4, 0x6}, /* 1067 800 */ + {0x3, 0x5}, /* 1067 1066 */ + }, + {{0x5, 0x9}, /* 1333 667 */ + {0x4, 0x7}, /* 1333 800 */ + {0x4, 0x7}, /* 1333 1066 */ + {0x4, 0x7} /* 1333 1333 */ + }, +}; + + const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ /* 115h[15:0] 117h[23:0] */ { /* 1N mode */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index a243e23..07cc71b 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -379,6 +379,7 @@ extern const struct dll_setting ddr3_dll_setting_1066[2][23]; extern const struct dll_setting ddr3_dll_setting_1333[2][23]; extern const u8 ddr3_emrs1_config[16][4]; +extern const u8 post_jedec_tab[3][4][2]; extern const u32 ddr3_c2_tab[2][3][6][2]; extern const u8 ddr3_c2_x264[3][6]; extern const u16 ddr3_c2_x23c[3][6]; -- To view, visit https://review.coreboot.org/19918 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit May 2017