coreboot-gerrit May 2017

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Change in coreboot[master]: src/include/device: Add PCIe root ports device ids
by Martin Roth (Code Review) 14 May '17

14 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19664 ) Change subject: src/include/device: Add PCIe root ports device ids ...................................................................... src/include/device: Add PCIe root ports device ids Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/19664 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h 1 file changed, 60 insertions(+), 0 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f243414..5a2e1b2 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2673,6 +2673,66 @@ #define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 +/* Intel PCIE device ids */ +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4 0x9d13 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5 0x9d14 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6 0x9d15 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7 0x9d16 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8 0x9d17 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9 0x9d18 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10 0x9d19 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11 0x9d1a +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12 0x9d1b + +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 0xa110 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2 0xa111 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3 0xa112 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4 0xa113 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5 0xa114 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6 0xa115 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7 0xa116 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8 0xa117 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9 0xa118 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10 0xa119 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11 0xa11a +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12 0xa11b +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13 0xa11c +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14 0xa11d +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15 0xa11e +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16 0xa11f +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17 0xa167 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18 0xa168 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19 0xa169 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20 0xa16a + +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 0xa290 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2 0xa291 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3 0xa292 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4 0xa293 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5 0xa294 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6 0xa295 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7 0xa296 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8 0xa297 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9 0xa298 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10 0xa299 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11 0xa29a +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12 0xa29b +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13 0xa29c +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14 0xa29d +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15 0xa29e +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16 0xa29f +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17 0xa2e7 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18 0xa2e8 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19 0xa2e9 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20 0xa2ea +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21 0xa2eb +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22 0xa2ec +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23 0xa2ed +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24 0xa2ee + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 -- To view, visit https://review.coreboot.org/19664 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [RFC]mb/*/*: Remove rtc nvram configurable baud rate
by Martin Roth (Code Review) 14 May '17

14 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19682 ) Change subject: [RFC]mb/*/*: Remove rtc nvram configurable baud rate ...................................................................... Patch Set 4: (1 comment) I think this will have to be rebased manually now - I just merged a patch that said it conflicted with this: https://review.coreboot.org/#/c/19663 https://review.coreboot.org/#/c/19682/4/src/mainboard/via/epia-m700/driving… File src/mainboard/via/epia-m700/driving_clk_phase_data.c: Line 22 > I used rather simple sed commands to do this. I'll try to see if there are I looked through all the rest - this was the only one I noticed that looked unrelated. -- To view, visit https://review.coreboot.org/19682 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c
by Martin Roth (Code Review) 14 May '17

14 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19663 ) Change subject: drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c ...................................................................... drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c And don't link it. It's for ROMCC. To make code happy that uses the ROMCC interface read_option(), read_option_lowlevel() is ported to mc146818rtc.c along with a message to use get_option() instead. Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/19663 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/pc80/rtc/Makefile.inc M src/drivers/pc80/rtc/mc146818rtc.c R src/drivers/pc80/rtc/mc146818rtc_romcc.c M src/drivers/uart/util.c M src/include/pc80/mc146818rtc.h 5 files changed, 13 insertions(+), 5 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Philippe Mathieu-Daudé: Looks good to me, but someone else must approve Raptor Engineering Automated Test Stand: Verified Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 5edb59b..5d7aef1 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -1,9 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c - -ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ifeq ($(CONFIG_USE_OPTION_TABLE),y) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index a102917..33860b8 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -304,6 +304,17 @@ return CB_SUCCESS; } +unsigned int read_option_lowlevel(unsigned int start, unsigned int size, + unsigned int def) +{ + printk(BIOS_NOTICE, "NOTICE: read_option() used to access CMOS " + "from non-ROMCC code, please use get_option() instead.\n"); + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + const unsigned char byte = cmos_read(start / 8); + return (byte >> (start & 7U)) & ((1U << size) - 1U); + } + return def; +} enum cb_err set_option(const char *name, void *value) { diff --git a/src/drivers/pc80/rtc/mc146818rtc_early.c b/src/drivers/pc80/rtc/mc146818rtc_romcc.c similarity index 100% rename from src/drivers/pc80/rtc/mc146818rtc_early.c rename to src/drivers/pc80/rtc/mc146818rtc_romcc.c diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 86da8dc..e1b83ba 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -24,7 +24,7 @@ static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; unsigned b_index = 0; -#if defined(__PRE_RAM__) +#if defined(__ROMCC__) b_index = read_option(baud_rate, 0xff); #else if (get_option(&b_index, "baud_rate") != CB_SUCCESS) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index ef19a15..ec0bf8e 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -188,7 +188,7 @@ unsigned int def); #else /* defined(__ROMCC__) */ -#include <drivers/pc80/rtc/mc146818rtc_early.c> +#include <drivers/pc80/rtc/mc146818rtc_romcc.c> #endif /* !defined(__ROMCC__) */ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default)) -- To view, visit https://review.coreboot.org/19663 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Reviewer: lava.coreboot.org <lavacoreboot(a)gmail.com>

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Martin Roth (Code Review) 14 May '17

14 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... mainboard: Add ASRock G41C-GS Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18993 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- A src/mainboard/asrock/g41c-gs/Kconfig A src/mainboard/asrock/g41c-gs/Kconfig.name A src/mainboard/asrock/g41c-gs/Makefile.inc A src/mainboard/asrock/g41c-gs/acpi/ec.asl A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi/platform.asl A src/mainboard/asrock/g41c-gs/acpi/superio.asl A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi_tables.c A src/mainboard/asrock/g41c-gs/board_info.txt A src/mainboard/asrock/g41c-gs/cmos.default A src/mainboard/asrock/g41c-gs/cmos.layout A src/mainboard/asrock/g41c-gs/cstates.c A src/mainboard/asrock/g41c-gs/devicetree.cb A src/mainboard/asrock/g41c-gs/dsdt.asl A src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/hda_verb.c A src/mainboard/asrock/g41c-gs/romstage.c 18 files changed, 880 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig new file mode 100644 index 0000000..669d8a5 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -0,0 +1,50 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASROCK_G41C_GS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_NUVOTON_NCT6776 + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + +config MAINBOARD_DIR + string + default "asrock/g41c-gs" + +config MAINBOARD_PART_NUMBER + string + default "G41C-GS" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASROCK_G41C_GS diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name new file mode 100644 index 0000000..3511047 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_G41C_GS + bool "G41C-GS" diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc new file mode 100644 index 0000000..f3d7e76 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += cstates.c +romstage-y += gpio.c diff --git a/src/mainboard/asrock/g41c-gs/acpi/ec.asl b/src/mainboard/asrock/g41c-gs/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..bb8745e --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + /* PCI1 SLOT 1 */ + Package() { 0x0001ffff, 0, 0, 0x16}, + Package() { 0x0001ffff, 1, 0, 0x17}, + Package() { 0x0001ffff, 2, 0, 0x14}, + Package() { 0x0001ffff, 3, 0, 0x15}, + + /* PCI1 SLOT 2 */ + Package() { 0x0002ffff, 0, 0, 0x17}, + Package() { 0x0002ffff, 1, 0, 0x14}, + Package() { 0x0002ffff, 2, 0, 0x15}, + Package() { 0x0002ffff, 3, 0, 0x16}, + + /* device not in lspci but in vendor DSDT */ + /* Package() { 0x0008ffff, 0, 0, 0x14}, */ + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + /* device not in lspci but in vendor DSDT */ + /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */ + }) +} diff --git a/src/mainboard/asrock/g41c-gs/acpi/platform.asl b/src/mainboard/asrock/g41c-gs/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asrock/g41c-gs/acpi/superio.asl b/src/mainboard/asrock/g41c-gs/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..5bec150 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, 0, 0x10 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 0x10 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 0x10 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 0x10 }, + Package() { 0x001cffff, 1, 0, 0x11 }, + Package() { 0x001cffff, 2, 0, 0x12 }, + Package() { 0x001cffff, 3, 0, 0x13 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 0x17 }, + Package() { 0x001dffff, 1, 0, 0x13 }, + Package() { 0x001dffff, 2, 0, 0x12 }, + Package() { 0x001dffff, 3, 0, 0x10 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, 0, 0x12 }, + Package() { 0x001fffff, 1, 0, 0x13 }, + }) + } Else { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c new file mode 100644 index 0000000..d80fb4c --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <stdint.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asrock/g41c-gs/board_info.txt b/src/mainboard/asrock/g41c-gs/board_info.txt new file mode 100644 index 0000000..96fe80e --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.asrock.com/mb/intel/g41c-gs/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2009 diff --git a/src/mainboard/asrock/g41c-gs/cmos.default b/src/mainboard/asrock/g41c-gs/cmos.default new file mode 100644 index 0000000..177af21 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=64M diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout new file mode 100644 index 0000000..c67cf73 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: cpu +#424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +1024 144 r 0 recv_enable_results +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asrock/g41c-gs/cstates.c b/src/mainboard/asrock/g41c-gs/cstates.c new file mode 100644 index 0000000..128f655 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asrock/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/devicetree.cb new file mode 100644 index 0000000..fd7f271 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/devicetree.cb @@ -0,0 +1,149 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1849 0x2e30 + end + device pci 1.0 on end # PEG + + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1849 0x2e32 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "2" + + register "ide_enable_primary" = "0x1" + register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x440" + + device pci 1b.0 on # Audio + subsystemid 0x1849 0x3662 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1849 0x27c8 + end + device pci 1d.1 on # USB + subsystemid 0x1849 0x27c9 + end + device pci 1d.2 on # USB + subsystemid 0x1849 0x27ca + end + device pci 1d.3 on # USB + subsystemid 0x1849 0x27cb + end + device pci 1d.7 on # USB + subsystemid 0x1849 0x27cc + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1849 0x27b8 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x1c = 0x80 + irq 0x27 = 0x80 + irq 0x2a = 0x60 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # CIR + io 0x60 = 0x230 + irq 0x70 = 3 + end + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe0 = 0x03 + irq 0xe4 = 0x10 # Power dram during s3 + irq 0xe6 = 0x4c + irq 0xe9 = 0x02 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + io 0x62 = 0x200 + irq 0x70 = 0 + end + device pnp 2e.d on end # VID + device pnp 2e.e on # CIR WAKE-UP + io 0x60 = 0x240 + irq 0x70 = 0 + end + device pnp 2e.f on end # GPIO Push-Pull or Open-drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 on end # GPIOA + end + end + device pci 1f.1 on # PATA/IDE + subsystemid 0x1849 0x27df + end + device pci 1f.2 on # SATA + subsystemid 0x1849 0x27c0 + end + device pci 1f.3 on # SMbus + subsystemid 0x1849 0x27da + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl new file mode 100644 index 0000000..e11eb39 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/gpio.c new file mode 100644 index 0000000..6299d62 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/gpio.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c new file mode 100644 index 0000000..1c0474b --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x18493662, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19830), + AZALIA_PIN_CFG(0, 0x19, 0x02a19940), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* coreboot specific header */ + /* Intel Eaglelake HDMI */ + 0x80862803, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 0x00000001, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), + + + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x1565821e, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c40), + AZALIA_PIN_CFG(2, 0x1a, 0x0181343f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c new file mode 100644 index 0000000..dd885db --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <lib.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> +#include <device/pnp_def.h> +#include <timestamp.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +static void mb_lpc_setup(void) +{ + u32 reg32; + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Set GPIOs on superio, enable UART */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x1c, 0x80); + pnp_write_config(SERIAL_DEV, 0x27, 0x80); + pnp_write_config(SERIAL_DEV, 0x2a, 0x60); + + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); + + reg32 = RCBA32(GCS); + reg32 |= (1 << 5); + RCBA32(GCS) = reg32; + RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD + | FD_ACAUD | 1; + RCBA32(CG) = 0x00000001; +} + +static void ich7_enable_lpc(void) +{ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); +} + +void mainboard_romstage_entry(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ + ich7_enable_lpc(); + mb_lpc_setup(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); + +} -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [RFC]mb/*/*: Remove rtc nvram configurable baud rate
by Arthur Heymans (Code Review) 13 May '17

13 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19682 ) Change subject: [RFC]mb/*/*: Remove rtc nvram configurable baud rate ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/19682/4/src/mainboard/via/epia-m700/driving… File src/mainboard/via/epia-m700/driving_clk_phase_data.c: Line 22 > Unrelated? I used rather simple sed commands to do this. I'll try to see if there are others like this. -- To view, visit https://review.coreboot.org/19682 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mainboard/lenovo/t430: Add Thinkpad T430 support
by Patrick Rudolph (Code Review) 13 May '17

13 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/18011 ) Change subject: mainboard/lenovo/t430: Add Thinkpad T430 support ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/18011/9/src/mainboard/lenovo/t430/smihandle… File src/mainboard/lenovo/t430/smihandler.c: Line 29: static void mainboard_smm_init(void) > I've been looking at this lately, because I wanted to trace down It's set in h8_enable if devicetree has correct config0 entry. If devicetree is broken, like the one generated by autoport it wont work at all. -- To view, visit https://review.coreboot.org/18011 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS
by build bot (Jenkins) (Code Review) 13 May '17

13 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19684 ) Change subject: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9391/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53607/ : SUCCESS -- To view, visit https://review.coreboot.org/19684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS
by Lijian Zhao (Code Review) 13 May '17

13 May '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/19684 ) Change subject: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19684/1/src/soc/intel/common/block/pcr/pcr.c File src/soc/intel/common/block/pcr/pcr.c: PS1, Line 27: #if(CONFIG_PCR_BASE_ADDRESS ==0) : #error "PCR_BASE_ADDRESS need to be non-zero!" : #endif > This does not need to be in a function. Move it above all of this. Also, fi Done -- To view, visit https://review.coreboot.org/19684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS
by Lijian Zhao (Code Review) 13 May '17

13 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19684 to look at the new patch set (#2). Change subject: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS ...................................................................... soc/intel/common: Add sanity check of PCR_BASE_ADDRESS PCR_BASE_ADRESS may be zero if SOC Kconfig didn't define the non zero default value. TEST=Remove the PCR_BASE_ADDRESS config in Apollolake Kconfig file and build. BUG=None Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/19684/2 -- To view, visit https://review.coreboot.org/19684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS
by Lijian Zhao (Code Review) 13 May '17

13 May '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/19684 ) Change subject: soc/intel/common: Add sanity check of PCR_BASE_ADDRESS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19684/1/src/soc/intel/common/block/pcr/pcr.c File src/soc/intel/common/block/pcr/pcr.c: PS1, Line 27: #if(CONFIG_PCR_BASE_ADDRESS ==0) : #error "PCR_BASE_ADDRESS need to be non-zero!" : #endif > This does not need to be in a function. Move it above all of this. Also, fi Actually the build here have something can't be explained. Even CONFIG_PCR_BASE_ADDRESS is not set, hence we can't find it in .config, but eventually in generated config.h, there will be #define CONFIG_PCR_BASE_ADDRESS 0, is that expected or can be explained? -- To view, visit https://review.coreboot.org/19684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017