Hannah Williams has uploaded a new patch set (#23). ( https://review.coreboot.org/18917 )
Change subject: soc/intel/common/block:[WIP] Add GPIO common code
......................................................................
soc/intel/common/block:[WIP] Add GPIO common code
Here are some differences between APL and SKL GPIO registers
DW0:
PMODE: SKL[11:10] and APL[12:10]
RXTXENCFG: APL[21:20] and RSVD in SKL
PREGFRXSEL: APL[24] and RSVD in SKL
DW1: SKL only has INTSEL and TERM whereas APL and GLK share same bit
definitions for rest of the bits that are reserved in SKL
(e.g. IoStandby state and term)
EVMAP and EVOUTEN are not there on SKL
DW1_PAD_TOL has been used only in SKL
Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
A src/soc/intel/common/block/gpio/Kconfig
A src/soc/intel/common/block/gpio/Makefile.inc
A src/soc/intel/common/block/gpio/gpio.c
A src/soc/intel/common/block/include/intelblocks/gpio.h
A src/soc/intel/common/block/include/intelblocks/gpio_defs.h
5 files changed, 842 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/18917/23
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Mario Scheithauer has uploaded a new change for review. ( https://review.coreboot.org/19693 )
Change subject: soc/intel/apollolake: Enable decoding for ComA and ComB on LPC
......................................................................
soc/intel/apollolake: Enable decoding for ComA and ComB on LPC
If there is an external 8250 UART, one needs to enable the appropriate
address ranges before console_init() is called so that the init sequence
can reach the external UART.
Furthermore FSPM needs different settings for an external UART port. For
this, the function fill_console_params() have to adapt.
Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/apollolake/include/soc/lpc.h
M src/soc/intel/apollolake/romstage.c
2 files changed, 35 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19693/1
diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h
index 7e3d74a..a40e362 100644
--- a/src/soc/intel/apollolake/include/soc/lpc.h
+++ b/src/soc/intel/apollolake/include/soc/lpc.h
@@ -29,8 +29,9 @@
* IO decode enable macros are in the format IO_<peripheral>_<IO port>.
* For example, to open ports 0x60, 0x64 for the keyboard controller,
* use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range,
- * the port range is selectable via the IO decodes register (not referenced).
+ * the port range is selectable via the IO decodes register.
*/
+#define REG_IO_DECODE 0x80
#define REG_IO_ENABLES 0x82
#define IOE_EC_4E_4F (1 << 13)
#define IOE_SUPERIO_2E_2F (1 << 12)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 98c7015..4386995 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -35,6 +35,7 @@
#include <soc/cpu.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
+#include <soc/lpc.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -85,6 +86,17 @@
/* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE);
+
+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
+ /*
+ * I/O Decode Range Register for LPC
+ * ComA Range 3F8h-3FFh
+ * ComB Range 2F8h-2FF
+ */
+ pci_write_config16(PCH_DEV_LPC, REG_IO_DECODE, 0x0010);
+ /* Enable ComA and ComB Port */
+ lpc_enable_fixed_io_ranges(IOE_COMA_EN | IOE_COMB_EN);
+ }
}
static void disable_watchdog(void)
@@ -245,14 +257,27 @@
static void fill_console_params(FSPM_UPD *mupd)
{
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
- mupd->FspmConfig.SerialDebugPortDevice =
- CONFIG_UART_FOR_CONSOLE;
- /* use MMIO port type */
- mupd->FspmConfig.SerialDebugPortType = 2;
- /* use 4 byte register stride */
- mupd->FspmConfig.SerialDebugPortStrideSize = 2;
- /* used only for port type set to external */
- mupd->FspmConfig.SerialDebugPortAddress = 0;
+ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) {
+ mupd->FspmConfig.SerialDebugPortDevice =
+ CONFIG_UART_FOR_CONSOLE;
+ /* use MMIO port type */
+ mupd->FspmConfig.SerialDebugPortType = 2;
+ /* use 4 byte register stride */
+ mupd->FspmConfig.SerialDebugPortStrideSize = 2;
+ /* used only for port type set to external */
+ mupd->FspmConfig.SerialDebugPortAddress = 0;
+ }
+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
+ /* use external UART for debug */
+ mupd->FspmConfig.SerialDebugPortDevice = 3;
+ /* use I/O port type */
+ mupd->FspmConfig.SerialDebugPortType = 1;
+ /* use 1 byte register stride */
+ mupd->FspmConfig.SerialDebugPortStrideSize = 0;
+ /* used only for port type set to external */
+ mupd->FspmConfig.SerialDebugPortAddress =
+ CONFIG_TTYS0_BASE;
+ }
} else {
mupd->FspmConfig.SerialDebugPortType = 0;
}
--
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/18011 )
Change subject: mainboard/lenovo/t430: Add Thinkpad T430 support
......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/#/c/18011/11/src/mainboard/lenovo/t430/romstage…
File src/mainboard/lenovo/t430/romstage.c:
PS11, Line 36: 0x10001fe0
> Maybe put a TODO here to investigate, if setting the reserved bits
OK
Line 39: /* FIXME: used T530 values here */
> What exactly went wrong? no output? insane output? Bug report
Have a look at patchset 1-2. That's the original autoport generated output. Patchset 3 moved it to romstage.c.
I do not have schematics for T430.
I guess the RCBA registers needs to be dumped on vendor BIOS ?
I'll remove the comments.
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Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19665 )
Change subject: soc/intel/common: Add Intel PCIe common code
......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/19665/3//COMMIT_MSG
Commit Message:
Line 8:
> Please add a commit message body for an addition of 150 lines of code.
Ok.Done.Sorry to miss that.
https://review.coreboot.org/#/c/19665/3/src/soc/intel/common/block/pcie/Kco…
File src/soc/intel/common/block/pcie/Kconfig:
PS3, Line 8: help
> remove this line
Ok.Done.revised under PS#4.
https://review.coreboot.org/#/c/19665/3/src/soc/intel/common/block/pcie/pci…
File src/soc/intel/common/block/pcie/pcie.c:
PS3, Line 42:
> if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
Ok.Done.Revised under PS#4.
PS3, Line 64: tic void pcie_set_L1_ss_max_latency(device
> Where are these Kconfig values? Even if an SoC doesn't want to program this
Ok.Undestood.Revised implementation in PS#4 to be IP centric.
Verified the latency values for upcoming platforms are also same.Please review.
PS3, Line 144:
> Please use a tabulator.
Done
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