coreboot-gerrit March 2017

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Change in coreboot[master]: vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by def...
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/18980 ) Change subject: vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default ...................................................................... vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/Kconfig M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/chell/chromeos.c M src/mainboard/google/cosmos/chromeos.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/Kconfig M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/Kconfig M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/lars/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/nyan/Kconfig M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/Kconfig M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/Kconfig M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/Kconfig M src/mainboard/google/oak/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/purin/chromeos.c M src/mainboard/google/rambi/Kconfig M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/rotor/chromeos.c M src/mainboard/google/slippy/Kconfig M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/Kconfig M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/Kconfig M src/mainboard/google/storm/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/urara/chromeos.c M src/mainboard/google/veyron/Kconfig M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/skylake/Kconfig M src/vboot/bootmode.c M src/vboot/vboot_handoff.c M src/vboot/vboot_logic.c M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/chromeos.c 69 files changed, 17 insertions(+), 289 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 00b4be8..41c9a7c 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -17,10 +17,8 @@ config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select LID_SWITCH select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 61b3e4e..3355136 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -28,7 +28,6 @@ struct lb_gpio chromeos_gpios[] = { {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index c430018..bceb8fb 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -18,7 +18,6 @@ config CHROMEOS select PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 4ee6810..7412c62 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -38,7 +38,6 @@ {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, @@ -56,11 +55,6 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index b2e3356..42f6189 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -29,7 +29,6 @@ #define WP_GPIO 6 #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 -#define FORCE_DEVELOPER_MODE 0 #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -60,13 +59,6 @@ gpios->gpios[1].polarity = ACTIVE_HIGH; gpios->gpios[1].value = get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Developer: virtual GPIO active high */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[2].name,"developer", - GPIO_MAX_NAME_LENGTH); /* lid switch value from EC */ gpios->gpios[3].port = -1; @@ -99,23 +91,6 @@ int get_lid_switch(void) { return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; -} - -int get_developer_mode_switch(void) -{ - int dev_mode = 0; - -#if FORCE_DEVELOPER_MODE - printk(BIOS_DEBUG,"FORCING DEVELOPER MODE.\n"); - return 1; -#endif - - /* Servo GPIO is active low, reverse it for intial state (request) */ - dev_mode = !get_gpio(DEVMODE_GPIO); - printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO, - dev_mode); - - return dev_mode; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index fdd1486..3ff52d9 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -30,7 +30,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c index a405cf0..d43daa2 100644 --- a/src/mainboard/google/cosmos/chromeos.c +++ b/src/mainboard/google/cosmos/chromeos.c @@ -20,11 +20,6 @@ { } -int get_developer_mode_switch(void) -{ - return 0; -} - int get_recovery_mode_switch(void) { return 0; diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6b9d5a2..424c08f 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -17,10 +17,8 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select LID_SWITCH select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config DISPLAY_SPD_DATA bool "Display Memory Serial Presence Detect Data" diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 672bc97..8aac84f 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -35,7 +35,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 452b728..dcac865 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -59,23 +59,10 @@ GPIO_MAX_NAME_LENGTH); count++; - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); gpios->count = count; printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index de83eaa..a77a23e 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -29,7 +29,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 48001e8..bde805f 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -28,7 +28,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 3f02e68..c408ca1 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -28,7 +28,6 @@ config CHROMEOS select VBOOT_VBNV_FLASH - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index e04aff1..3f86c29 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -52,14 +52,6 @@ GPIO_MAX_NAME_LENGTH); count++; - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - /* TODO: Reset: active low (output) */ gpios->gpios[count].port = GPIO(I5); gpios->gpios[count].polarity = ACTIVE_LOW; @@ -72,11 +64,6 @@ gpios->count = count; printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 01e2945..b6639bc 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -33,7 +33,6 @@ config CHROMEOS select VBOOT_DISABLE_DEV_ON_RECOVERY - select VIRTUAL_DEV_SWITCH select WIPEOUT_SUPPORTED config BOARD_VARIANT_DK01 diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 92a16b1..939b061 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -25,8 +25,6 @@ #include <timer.h> #include <vendorcode/google/chromeos/chromeos.h> -#define DEV_SW 41 -#define DEV_POL ACTIVE_LOW #define REC_POL ACTIVE_LOW #define WP_POL ACTIVE_LOW @@ -71,7 +69,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {DEV_SW, DEV_POL, read_gpio(DEV_SW), "developer"}, {get_rec_sw_gpio_pin(), REC_POL, read_gpio(get_rec_sw_gpio_pin()), "recovery"}, {get_wp_status_gpio_pin(), WP_POL, @@ -80,11 +77,6 @@ {-1, ACTIVE_LOW, 0, "lid"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_developer_mode_switch(void) -{ - return 0; } /* diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 9ee6e6f..3cb3d89 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -31,7 +31,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index c9886f6..bd19a29 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -47,11 +47,9 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select MAINBOARD_HAS_SPI_TPM_CR50 if GRU_HAS_TPM2 select SPI_TPM if GRU_HAS_TPM2 select VBOOT_VBNV_FLASH - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 37dac7e..39cee21 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -16,7 +16,6 @@ select CHROMEOS_RAMOOPS_DYNAMIC select PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index c22f942..5f897f3 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -40,7 +40,6 @@ get_gpio(GPIO_SPI_WP), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, @@ -58,11 +57,6 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 42763a7..54f9bbe 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -30,7 +30,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 0469d65..335f1f7 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -54,12 +54,6 @@ gpios->gpios[3].value = 0; strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - /* Developer: a tricky case on Link, there is no switch */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH); - /* Did we load the VGA Option ROM? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 515d16b..7f5854c 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -33,9 +33,7 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select VBOOT_VBNV_EC - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index aa7c9c6..4fb8e78 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -25,7 +25,6 @@ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, {GPIO(I5), ACTIVE_LOW, -1, "reset"}, }; diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index c8411bf..602e778 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -34,9 +34,7 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select VBOOT_VBNV_EC - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 2c9ba28..f466d91 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -25,7 +25,6 @@ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, {GPIO(I5), ACTIVE_LOW, -1, "reset"}, }; diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 530397c..d64eb72 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -35,9 +35,7 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select VBOOT_VBNV_EC - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 2c9ba28..f466d91 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -25,7 +25,6 @@ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, {GPIO(I5), ACTIVE_LOW, -1, "reset"}, }; diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 083ed9c..0efa478 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -35,11 +35,9 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select VBOOT_EC_SLOW_UPDATE select VBOOT_OPROM_MATTERS select VBOOT_VBNV_FLASH - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index fe4574e..a581364 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -40,7 +40,6 @@ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {LID, ACTIVE_HIGH, -1, "lid"}, {POWER_BUTTON, ACTIVE_HIGH, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ, ACTIVE_LOW, -1, "EC interrupt"}, }; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 4dcbfa5..d2448eb 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -56,12 +56,6 @@ gpios->gpios[1].value = get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: Virtual GPIO in the EC ( Servo GPIO17 active low) */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); - /* Lid switch GPIO active high (open). */ gpios->gpios[3].port = 15; gpios->gpios[3].polarity = ACTIVE_HIGH; @@ -86,22 +80,6 @@ int get_lid_switch(void) { return get_gpio(15); -} - -int get_developer_mode_switch(void) -{ - u8 gpio = !get_gpio(17); - /* - * Dev mode is controlled by EC and uboot stores a flag in TPM. - * This GPIO is only for the debug header. - * It is AND'd to the EC request. - */ - - printk(BIOS_DEBUG, "DEV MODE GPIO 17: %x\n", gpio); - - /* GPIO17, active low -- return active high reading and let - * it be inverted by the caller if needed. */ - return gpio; } int get_write_protect_state(void) diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index bc3a279..4cab7dc 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -59,23 +59,10 @@ GPIO_MAX_NAME_LENGTH); count++; - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); gpios->count = count; printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 03a9afe..8004d7b 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -28,7 +28,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c index e6843a1..5e7cdfe 100644 --- a/src/mainboard/google/purin/chromeos.c +++ b/src/mainboard/google/purin/chromeos.c @@ -20,11 +20,6 @@ { } -int get_developer_mode_switch(void) -{ - return 0; -} - int get_recovery_mode_switch(void) { return 0; diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 128e609..9b25b49 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -15,10 +15,8 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select LID_SWITCH select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 10e0762..99a97d8 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -29,7 +29,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 256db16..7b7f2b8 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -25,7 +25,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/rotor/chromeos.c b/src/mainboard/google/rotor/chromeos.c index e03114f..c73fe47 100644 --- a/src/mainboard/google/rotor/chromeos.c +++ b/src/mainboard/google/rotor/chromeos.c @@ -23,11 +23,6 @@ /*TODO: implement fill_lb_gpios */ } -int get_developer_mode_switch(void) -{ - return 0; -} - int get_recovery_mode_switch(void) { return 0; diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 0413cd8..a19c966 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -23,11 +23,9 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select LID_SWITCH select MAINBOARD_DO_NATIVE_VGA_INIT if (BOARD_GOOGLE_FALCO || BOARD_GOOGLE_PEPPY) select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 22ec074..e26c3fb 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -27,7 +27,6 @@ struct lb_gpio chromeos_gpios[] = { {58, ACTIVE_HIGH, 0, "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index ba6252b..5207674 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -34,9 +34,7 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select VBOOT_VBNV_FLASH - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 0372584..fe8e5aa 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -26,7 +26,6 @@ gpio_get(WRITE_PROTECT_L), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {POWER_BUTTON, ACTIVE_LOW, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, }; diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 268b11d..f844cf8 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -32,7 +32,6 @@ config CHROMEOS select VBOOT_DISABLE_DEV_ON_RECOVERY select WIPEOUT_SUPPORTED - select VIRTUAL_DEV_SWITCH config BOARD_VARIANT_AP148 bool "pick this to build an image for ap148" diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index a379280..3110228 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -43,18 +43,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {DEV_SW, ACTIVE_LOW, read_gpio(DEV_SW), "developer"}, {REC_SW, ACTIVE_LOW, read_gpio(REC_SW), "recovery"}, {WP_SW, ACTIVE_LOW, read_gpio(WP_SW), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, {-1, ACTIVE_LOW, 0, "lid"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_developer_mode_switch(void) -{ - return 0; } /* diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index cbb9574..047e6a1 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -49,12 +49,6 @@ gpios->gpios[1].value = get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: Virtual switch */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); - /* Lid Switch: Virtual switch */ gpios->gpios[3].port = -1; gpios->gpios[3].polarity = ACTIVE_HIGH; @@ -90,12 +84,6 @@ { /* hard-code to open */ return 1; -} - -/* The dev-switch is virtual on Stout (and so handled elsewhere). */ -int get_developer_mode_switch(void) -{ - return 0; } /* diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c index 4db06c6..3f7ec32 100644 --- a/src/mainboard/google/urara/chromeos.c +++ b/src/mainboard/google/urara/chromeos.c @@ -29,12 +29,6 @@ printk(BIOS_ERR, "%s unsupported, but called\n", __func__); } -int get_developer_mode_switch(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} - int get_recovery_mode_switch(void) { printk(BIOS_ERR, "%s unsupported, but called\n", __func__); diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index e638652..3eb3252 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -46,9 +46,7 @@ select SPI_FLASH_WINBOND config CHROMEOS - select EC_SOFTWARE_SYNC select VBOOT_VBNV_EC - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index b730622..b8fb3bc 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -47,18 +47,12 @@ get_recovery_mode_switch(), "recovery"}, {GPIO_LID.raw, ACTIVE_HIGH, -1, "lid"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {GPIO_ECINRW.raw, ACTIVE_HIGH, -1, "EC in RW"}, {GPIO_ECIRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 1a94831..24d7921 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -33,7 +33,6 @@ config CHROMEOS select PHYSICAL_REC_SWITCH select VBOOT_VBNV_FLASH - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 5cb9ec4..2988ea7 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -36,15 +36,9 @@ {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, gpio_get(GPIO_RECOVERY), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index b6d3f65..bbd6ffd 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -33,7 +33,6 @@ config CHROMEOS select PHYSICAL_REC_SWITCH select VBOOT_VBNV_FLASH - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index ac1afd9..c68cd7a 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -44,15 +44,9 @@ {GPIO_RECOVERY_PUSHKEY.raw, ACTIVE_LOW, !get_recovery_mode_switch(), "recovery"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_developer_mode_switch(void) -{ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 1666fc5..5ed9e36 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -36,7 +36,6 @@ return; u32 gp_lvl = inl(gpio_base + GP_LVL); - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); u32 gp_lvl3 = inl(gpio_base + GP_LVL3); gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); @@ -54,12 +53,6 @@ gpios->gpios[1].polarity = ACTIVE_HIGH; gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Developer: GPIO48 - BIOS_RESP - J8E4 (silkscreen: J8E3) */ - gpios->gpios[2].port = 48; - gpios->gpios[2].polarity = ACTIVE_LOW; - gpios->gpios[2].value = (gp_lvl2 >> (48-32)) & 1; - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); /* Hard code the lid switch GPIO to open. */ gpios->gpios[3].port = -1; @@ -80,15 +73,6 @@ strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif - -int get_developer_mode_switch(void) -{ - /* - * Developer: GPIO48, Connected to J8E4, however the silkscreen says - * J8E3. The jumper is active low. - */ - return !get_gpio(48); -} int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 896f876..eac995a 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -55,12 +55,6 @@ gpios->gpios[1].value = (gp_lvl >> 22) & 1; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: GPIO57 */ - gpios->gpios[2].port = 57; - gpios->gpios[2].polarity = ACTIVE_LOW; - gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1; - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); - /* Hard code the lid switch GPIO to open. */ gpios->gpios[3].port = -1; gpios->gpios[3].polarity = ACTIVE_HIGH; @@ -80,12 +74,6 @@ strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif - -int get_developer_mode_switch(void) -{ - /* Developer: GPIO57, active high */ - return get_gpio(57); -} int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index cc8831e..70fe113 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -32,11 +32,6 @@ return 0; } -int get_developer_mode_switch(void) -{ - return 0; -} - int get_recovery_mode_switch(void) { return 0; diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index fc1bcd2..4bd802a 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -36,7 +36,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, @@ -53,12 +52,6 @@ /* Lid always open */ return 1; -} - -int get_developer_mode_switch(void) -{ - /* No physical developer mode switch. */ - return 0; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 42763a7..54f9bbe 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -30,7 +30,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 8915323..c7221e9 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -17,10 +17,8 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC select LID_SWITCH select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH config DYNAMIC_VNN_SUPPORT bool "Enables support for Dynamic VNN" diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 6d00d72..fbcbcf7 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -32,7 +32,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 862f4a4..fe98fd8 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -21,8 +21,7 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Compile-time settings for developer and recovery mode. */ -#define DEV_MODE_SETTING 1 +/* Compile-time settings for recovery mode. */ #define REC_MODE_SETTING 0 #ifndef __PRE_RAM__ @@ -33,7 +32,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, 0, "write protect"}, {-1, ACTIVE_HIGH, REC_MODE_SETTING, "recovery"}, - {-1, ACTIVE_HIGH, DEV_MODE_SETTING, "developer"}, {-1, ACTIVE_HIGH, 1, "lid"}, // force open {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, @@ -41,11 +39,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif - -int get_developer_mode_switch(void) -{ - return DEV_MODE_SETTING; -} int get_recovery_mode_switch(void) { diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7cb00e5..db1debb 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -21,6 +21,8 @@ select INTEL_INT15 config CHROMEOS + select PHYSICAL_DEV_SWITCH + select PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS config MAINBOARD_DIR diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 3777f69..f8e9b99 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -18,6 +18,7 @@ select INTEL_INT15 config CHROMEOS + select PHYSICAL_DEV_SWITCH select PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 9b847da..234e290 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -70,14 +70,12 @@ config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC - select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC select SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - select VIRTUAL_DEV_SWITCH config TPM_ON_FAST_SPI bool diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0108372..b7c5552 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -87,7 +87,6 @@ config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC - select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC select SEPARATE_VERSTAGE select VBOOT_EC_SLOW_UPDATE if EC_GOOGLE_CHROMEEC select VBOOT_OPROM_MATTERS @@ -95,7 +94,6 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - select VIRTUAL_DEV_SWITCH config BOOTBLOCK_RESETS string diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 46b78e1..21922d4 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -162,9 +162,6 @@ if (!IS_ENABLED(CONFIG_VBOOT)) return 0; - if (get_developer_mode_switch()) - return 1; - if (cbmem_possibly_online() && vboot_handoff_check_developer_flag()) return 1; diff --git a/src/vboot/vboot_handoff.c b/src/vboot/vboot_handoff.c index 2bd5c09..85be928 100644 --- a/src/vboot/vboot_handoff.c +++ b/src/vboot/vboot_handoff.c @@ -83,7 +83,7 @@ vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } /* TODO: Set these in depthcharge */ - if (IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH)) + if (!IS_ENABLED(CONFIG_PHYSICAL_DEV_SWITCH)) vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; if (IS_ENABLED(CONFIG_EC_SOFTWARE_SYNC)) vb_sd->flags |= VBSD_EC_SOFTWARE_SYNC; diff --git a/src/vboot/vboot_logic.c b/src/vboot/vboot_logic.c index af7e947..fbbe3e8 100644 --- a/src/vboot/vboot_logic.c +++ b/src/vboot/vboot_logic.c @@ -329,7 +329,7 @@ antirollback_read_space_firmware(&ctx); timestamp_add_now(TS_END_TPMINIT); - if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) && + if (IS_ENABLED(CONFIG_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 3c6237a..62e60d4 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -61,6 +61,7 @@ config EC_SOFTWARE_SYNC bool "Enable EC software sync" + default y if EC_GOOGLE_CHROMEEC default n depends on VBOOT help @@ -76,13 +77,6 @@ Whether the EC (or PD) is slow to update and needs to display a screen that informs the user the update is happening. -config VIRTUAL_DEV_SWITCH - bool "Virtual developer switch support" - default n - depends on VBOOT - help - Whether this platform has a virtual developer switch. - config NO_TPM_RESUME bool default n @@ -91,8 +85,17 @@ boards, booting Windows will break if the TPM resume command is sent during an S3 resume. +config PHYSICAL_DEV_SWITCH + bool + default n + help + Whether this platform has a physical developer switch. Note that this + disables virtual dev switch functionality (through secdata). Operation + where both a physical pin and the virtual switch get sampled is not + supported by coreboot. + config PHYSICAL_REC_SWITCH - bool "Physical recovery switch is present" + bool default n help Whether this platform has a physical recovery switch diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index dddce63..4edf74a 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -17,12 +17,6 @@ #include <string.h> #include "chromeos.h" -int __attribute__((weak)) get_developer_mode_switch(void) -{ - // Weak implementation. No physical developer switch. - return 0; -} - int __attribute__((weak)) clear_recovery_mode_switch(void) { // Weak implementation. Nothing to do. -- To view, visit https://review.coreboot.org/18980 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: vboot: Remove VBOOT_DYNAMIC_WORK_BUFFER Kconfig option
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/18979 ) Change subject: vboot: Remove VBOOT_DYNAMIC_WORK_BUFFER Kconfig option ...................................................................... vboot: Remove VBOOT_DYNAMIC_WORK_BUFFER Kconfig option VBOOT_DYNAMIC_WORK_BUFFER and VBOOT_STARTS_IN_ROMSTAGE are equivalent in practice. We can't have a dynamic work buffer unless we start in/after romstage, and there'd be no reason to go with a static buffer if we do. Let's get rid of one extra option and merge the two. Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18979 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/cyan/Kconfig M src/mainboard/intel/strago/Kconfig M src/soc/marvell/mvmap2315/Kconfig M src/vboot/Kconfig M src/vboot/common.c M src/vboot/vboot_handoff.c M src/vboot/vboot_loader.c 7 files changed, 8 insertions(+), 22 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index d236aa0..6b9d5a2 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -19,7 +19,6 @@ select EC_GOOGLE_CHROMEEC_SWITCHES select EC_SOFTWARE_SYNC select LID_SWITCH - select VBOOT_DYNAMIC_WORK_BUFFER select VBOOT_VBNV_CMOS select VIRTUAL_DEV_SWITCH diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 0d59371..8915323 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -19,7 +19,6 @@ select EC_GOOGLE_CHROMEEC_SWITCHES select EC_SOFTWARE_SYNC select LID_SWITCH - select VBOOT_DYNAMIC_WORK_BUFFER select VBOOT_VBNV_CMOS select VIRTUAL_DEV_SWITCH diff --git a/src/soc/marvell/mvmap2315/Kconfig b/src/soc/marvell/mvmap2315/Kconfig index d27f4c4..45e03c1 100644 --- a/src/soc/marvell/mvmap2315/Kconfig +++ b/src/soc/marvell/mvmap2315/Kconfig @@ -33,7 +33,6 @@ config CHROMEOS select VBOOT - select VBOOT_DYNAMIC_WORK_BUFFER select VBOOT_STARTS_IN_ROMSTAGE config CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index 2b6cde1..0c72d47 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -95,17 +95,6 @@ reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage. -config VBOOT_DYNAMIC_WORK_BUFFER - bool "Vboot's work buffer is dynamically allocated." - default y if ARCH_ROMSTAGE_X86_32 && !SEPARATE_VERSTAGE - default n - depends on VBOOT - help - This option is used when there isn't enough pre-main memory - RAM to allocate the vboot work buffer. That means vboot verification - is after memory init and requires main memory to back the work - buffer. - config VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT bool default n diff --git a/src/vboot/common.c b/src/vboot/common.c index cfdb82a..3e480ed 100644 --- a/src/vboot/common.c +++ b/src/vboot/common.c @@ -46,7 +46,7 @@ static struct vb2_working_data * const vboot_get_working_data(void) { - if (IS_ENABLED(CONFIG_VBOOT_DYNAMIC_WORK_BUFFER)) + if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) /* cbmem_add() does a cbmem_find() first. */ return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb_work_buf_size); else @@ -55,7 +55,7 @@ static size_t vb2_working_data_size(void) { - if (IS_ENABLED(CONFIG_VBOOT_DYNAMIC_WORK_BUFFER)) + if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) return vb_work_buf_size; else return _vboot2_work_size; @@ -168,12 +168,12 @@ } /* - * For platforms that employ VBOOT_DYNAMIC_WORK_BUFFER, the vboot + * For platforms that employ VBOOT_STARTS_IN_ROMSTAGE, the vboot * verification doesn't happen until after cbmem is brought online. * Therefore, the selected region contents would not be initialized * so don't automatically add results when cbmem comes online. */ -#if !IS_ENABLED(CONFIG_VBOOT_DYNAMIC_WORK_BUFFER) +#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) static void vb2_store_selected_region_cbmem(int unused) { vb2_store_selected_region(); diff --git a/src/vboot/vboot_handoff.c b/src/vboot/vboot_handoff.c index 2533a1d..2bd5c09 100644 --- a/src/vboot/vboot_handoff.c +++ b/src/vboot/vboot_handoff.c @@ -175,12 +175,12 @@ } /* - * For platforms that employ VBOOT_DYNAMIC_WORK_BUFFER, the vboot + * For platforms that employ VBOOT_STARTS_IN_ROMSTAGE, the vboot * verification doesn't happen until after cbmem is brought online. * Therefore, the vboot results would not be initialized so don't * automatically add results when cbmem comes online. */ -#if !IS_ENABLED(CONFIG_VBOOT_DYNAMIC_WORK_BUFFER) +#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) static void vb2_fill_handoff_cbmem(int unused) { vboot_fill_handoff(); diff --git a/src/vboot/vboot_loader.c b/src/vboot/vboot_loader.c index 207aada..9593358 100644 --- a/src/vboot/vboot_loader.c +++ b/src/vboot/vboot_loader.c @@ -145,12 +145,12 @@ /* * Fill in vboot cbmem objects before moving to ramstage so all * downstream users have access to vboot results. This path only - * applies to platforms employing VBOOT_DYNAMIC_WORK_BUFFER because + * applies to platforms employing VBOOT_STARTS_IN_ROMSTAGE because * cbmem comes online prior to vboot verification taking place. For * other platforms the vboot cbmem objects are initialized when * cbmem comes online. */ - if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_DYNAMIC_WORK_BUFFER)) { + if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { vb2_store_selected_region(); vboot_fill_handoff(); } -- To view, visit https://review.coreboot.org/18979 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig ...
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/18978 ) Change subject: vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig option ...................................................................... vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig option CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL allows the SoC directory to provide its own main() symbol that can execute code before the generic verstage code runs. We have now established in other places (e.g. T210 ramstage) a sort of convention that SoCs which need to run code in any stage before main() should just override stage_entry() instead. This patch aligns the verstage with that model and gets rid of the extra Kconfig option. This also removes the need for aliasing between main() and verstage(). Like other stages the main verstage code is now just in main() and can be called from stage_entry(). Change-Id: If42c9c4fbab51fbd474e1530023a30b69495d1d6 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18978 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) --- M src/arch/x86/verstage.c M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra124/verstage.c M src/vboot/Kconfig M src/vboot/vboot_common.h M src/vboot/verstage.c 6 files changed, 7 insertions(+), 21 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c index 7987e1c..d24866b 100644 --- a/src/arch/x86/verstage.c +++ b/src/arch/x86/verstage.c @@ -14,10 +14,10 @@ */ #include <arch/cpu.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <main_decl.h> /* Provide an entry point for verstage when it's a separate stage. */ asmlinkage void car_stage_entry(void) { - verstage(); + main(); } diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 227efca..fdbbc7f 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -20,7 +20,6 @@ select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK select SEPARATE_VERSTAGE - select CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL config TEGRA124_MODEL_TD570D bool "TD570D" diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 9eee064..526f14e 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -45,9 +45,9 @@ early_mainboard_init(); } -void main(void) +void stage_entry(void) { asm volatile ("bl arm_init_caches" : : : "r0", "r1", "r2", "r3", "r4", "r5", "ip"); - verstage(); + main(); } diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index e67c108..2b6cde1 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -95,13 +95,6 @@ reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage. -config CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL - bool "The chipset provides the main() entry point for verstage" - default n - depends on SEPARATE_VERSTAGE - help - The chipset code provides their own main() entry point. - config VBOOT_DYNAMIC_WORK_BUFFER bool "Vboot's work buffer is dynamically allocated." default y if ARCH_ROMSTAGE_X86_32 && !SEPARATE_VERSTAGE diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 956b54c..aa01f28 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -97,11 +97,10 @@ /* ============================= VERSTAGE ================================== */ /* - * Main logic for verified boot. verstage() is the stage entry point - * while the verstage_main() is just the core logic. + * Main logic for verified boot. verstage_main() is just the core vboot logic. + * If the verstage is a separate stage, it should be entered via main(). */ void verstage_main(void); -void verstage(void); void verstage_mainboard_init(void); /* Check boot modes */ diff --git a/src/vboot/verstage.c b/src/vboot/verstage.c index 0ec9ca6..64fadc7 100644 --- a/src/vboot/verstage.c +++ b/src/vboot/verstage.c @@ -24,7 +24,7 @@ /* Default empty implementation. */ } -void verstage(void) +void main(void) { console_init(); exception_init(); @@ -37,8 +37,3 @@ hlt(); } } - -#if !IS_ENABLED(CONFIG_CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL) -/* This is for boards that rely on main() for an entry point of a stage. */ -void main(void) __attribute__((alias ("verstage"))); -#endif -- To view, visit https://review.coreboot.org/18978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: If42c9c4fbab51fbd474e1530023a30b69495d1d6 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: vboot: Select SoC-specific configuration for all Chrome OS b...
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19022 ) Change subject: vboot: Select SoC-specific configuration for all Chrome OS boards ...................................................................... vboot: Select SoC-specific configuration for all Chrome OS boards Some Chrome OS boards previously didn't have a hardcoded vboot configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE, etc.) selected from their SoC and mainboard Kconfig files, and instead relied on the Chrome OS build system to pass in those options separately. Since there is usually only one "best" vboot configuration for a certain board and there is often board or SoC code specifically written with that configuration in mind (e.g. memlayout), these options should not be adjustable in menuconfig and instead always get selected by board and SoC Makefiles (as opposed to some external build system). (Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for Pistachio/MIPS was never finished. Trying to enable even post-romstage vboot leads to weird compiler errors that I don't want to track down now. Let's stop pretending this board has working Chrome OS support because it never did.) Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/urara/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/soc/broadcom/cygnus/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5420/Kconfig 12 files changed, 34 insertions(+), 1 deletion(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index e7b9e0e..06263d5 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -20,7 +20,6 @@ def_bool y select BOARD_ROMSIZE_KB_512 select BOOTBLOCK_CONSOLE - select MAINBOARD_HAS_CHROMEOS select SPI_FLASH_WINBOND select CPU_IMGTEC_PISTACHIO select COMMON_CBFS_SPI_WRAPPER diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e9a93ba..48a92b6 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -25,6 +25,9 @@ if NORTHBRIDGE_INTEL_HASWELL +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/haswell/bootblock.c" diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index c78b397..8b92077 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -32,6 +32,9 @@ if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config USE_NATIVE_RAMINIT bool "Use native raminit" default y diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig index 4610903..e5849f0 100644 --- a/src/soc/broadcom/cygnus/Kconfig +++ b/src/soc/broadcom/cygnus/Kconfig @@ -29,6 +29,7 @@ if SOC_BROADCOM_CYGNUS config CHROMEOS + select VBOOT_STARTS_IN_BOOTBLOCK select SEPARATE_VERSTAGE select RETURN_FROM_VERSTAGE diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 2d07c99..752e10a 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -39,6 +39,9 @@ select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config BOOTBLOCK_CPU_INIT string default "soc/intel/baytrail/bootblock/bootblock.c" diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ac4a2ae..61f41ed 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -46,6 +46,9 @@ select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config BOOTBLOCK_CPU_INIT string default "soc/intel/braswell/bootblock/bootblock.c" diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 0cbd9e4..34f515f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -46,6 +46,9 @@ select HAVE_SPI_CONSOLE_SUPPORT select CPU_INTEL_COMMON +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config BOOTBLOCK_CPU_INIT string default "soc/intel/broadwell/bootblock/cpu.c" diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 4e3becc..880f199 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -18,6 +18,8 @@ if SOC_NVIDIA_TEGRA210 config CHROMEOS + select VBOOT_STARTS_IN_BOOTBLOCK + select SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS config MAINBOARD_DO_DSI_INIT diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 05f29e4..d0c1fbd 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -13,6 +13,7 @@ if SOC_QC_IPQ40XX config CHROMEOS + select VBOOT_STARTS_IN_BOOTBLOCK select RETURN_FROM_VERSTAGE select SEPARATE_VERSTAGE select VBOOT_VBNV_FLASH diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 32b61bc..13977e5 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -12,6 +12,7 @@ if SOC_QC_IPQ806X config CHROMEOS + select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_FLASH select SEPARATE_VERSTAGE select RETURN_FROM_VERSTAGE diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 63b58e7..40c8065 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -10,3 +10,10 @@ select HAVE_HARD_RESET bool default n + +if CPU_SAMSUNG_EXYNOS5250 + +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + +endif diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 02c71c0..7fb2f8f 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -9,3 +9,10 @@ select RELOCATABLE_MODULES bool default n + +if CPU_SAMSUNG_EXYNOS5420 + +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + +endif -- To view, visit https://review.coreboot.org/19022 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: chromeos: Remove old MOCK_TPM references
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/18977 ) Change subject: chromeos: Remove old MOCK_TPM references ...................................................................... chromeos: Remove old MOCK_TPM references The correct way to mock out vboot TPM accesses these days is the CONFIG_VBOOT_MOCK_SECDATA Kconfig option. There are some remnants of older TPM-mocking infrastructure in our codebase that are as far as I can tell inert. Remove them. Change-Id: I3e00c94b71d53676e6c796e0bec0f3db67c78e34 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18977 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/lib/Makefile.inc D src/lib/mocked_tlcl.c M src/vendorcode/google/chromeos/Makefile.inc 3 files changed, 0 insertions(+), 153 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 977770f..1117076 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -50,10 +50,6 @@ verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c -ifeq ($(MOCK_TPM),1) -libverstage-y += mocked_tlcl.c -romstage-$(CONFIG_SEPARATE_VERSTAGE) += mocked_tlcl.c -else libverstage-$(CONFIG_TPM) += tlcl.c libverstage-$(CONFIG_TPM2) += tpm2_marshaling.c libverstage-$(CONFIG_TPM2) += tpm2_tlcl.c @@ -63,8 +59,6 @@ romstage-$(CONFIG_TPM2) += tpm2_marshaling.c romstage-$(CONFIG_TPM2) += tpm2_tlcl.c endif # CONFIG_SEPARATE_VERSTAGE - -endif verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/mocked_tlcl.c b/src/lib/mocked_tlcl.c deleted file mode 100644 index 2eec78d..0000000 --- a/src/lib/mocked_tlcl.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <tpm_lite/tlcl.h> - -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else -#include <console/console.h> -#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) -#endif - -uint32_t tlcl_lib_init(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_startup(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_resume(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_self_test_full(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_continue_self_test(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - - -uint32_t tlcl_assert_physical_presence(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_physical_presence_cmd_enable(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_finalize_physical_presence(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_set_nv_locked(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_force_clear(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_set_enable(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_set_deactivated(uint8_t flag) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_get_flags(uint8_t *disable, uint8_t *deactivated, - uint8_t *nvlocked) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_set_global_lock(void) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} - -uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, - uint8_t *out_digest) -{ - VBDEBUG("MOCK_TPM: %s\n", __func__); - return TPM_E_NO_DEVICE; -} diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index af5e178..3326ced 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -32,12 +32,6 @@ ramstage-y += watchdog.c endif -ifeq ($(MOCK_TPM),1) -CFLAGS_common += -DMOCK_TPM=1 -else -CFLAGS_common += -DMOCK_TPM=0 -endif - CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) CONFIG_VBOOT_KEYBLOCK := $(call strip_quotes,$(CONFIG_VBOOT_KEYBLOCK)) -- To view, visit https://review.coreboot.org/18977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I3e00c94b71d53676e6c796e0bec0f3db67c78e34 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: arm64: Fix verstage to use proper assembly versions of mem*()
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/18976 ) Change subject: arm64: Fix verstage to use proper assembly versions of mem*() ...................................................................... arm64: Fix verstage to use proper assembly versions of mem*() Due to an unfortunate race between adding verstage support and reverting an earlier hack that disabled the optimized assembly versions of memcpy(), memmove() and memset() on ARM64, it seems that we never enabled the optimized code for the verstage. This should be fixed so that all stages use the same architecture support code. Change-Id: I0bf3245e346105492030f4b133729c4d11bdb3ff Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18976 Tested-by: build bot (Jenkins) --- M src/arch/arm64/Makefile.inc 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 95bc58d..7f3ce3f 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -72,9 +72,9 @@ verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c -verstage-y += ../../lib/memset.c -verstage-y += ../../lib/memcpy.c -verstage-y += ../../lib/memmove.c +verstage-y += memset.S +verstage-y += memcpy.S +verstage-y += memmove.S verstage-y += transition.c transition_asm.S -- To view, visit https://review.coreboot.org/18976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I0bf3245e346105492030f4b133729c4d11bdb3ff Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in coreboot[master]: arm64: Fix verstage to use proper assembly versions of mem*()
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/18976 ) Change subject: arm64: Fix verstage to use proper assembly versions of mem*() ...................................................................... Patch Set 5: Code-Review+2 Just fixed a typo in the commit message there. -- To view, visit https://review.coreboot.org/18976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0bf3245e346105492030f4b133729c4d11bdb3ff Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: abuild: Treat command line for recursive invocations as bash...
by Julius Werner (Code Review) 28 Mar '17

28 Mar '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/18975 ) Change subject: abuild: Treat command line for recursive invocations as bash array ...................................................................... abuild: Treat command line for recursive invocations as bash array This fix changes the $cmdline variable that is used for recursive parallel abuild invocations through xargs from a string to a true bash array (like $@). This allows bash to properly preserve and pass on whitespace in parameters, like you get from invocations such as: util/abuild/abuild -c 32 -t "MY_FIRST_BOARD MY_SECOND_BOARD" Also add a mechanism to better spread CPUs across targets, since otherwise we can leave a lot of CPUs idle if we're trying to build only a few boards in parallel. Change-Id: I76a1c6456ef8ab21286fdc1636d659a3b76bc5d7 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/abuild/abuild 1 file changed, 9 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/abuild/abuild b/util/abuild/abuild index 93ceac5..95711a1 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -16,8 +16,8 @@ #set -x # Turn echo on.... -ABUILD_DATE="Dec 6, 2016" -ABUILD_VERSION="0.10.01" +ABUILD_DATE="Mar 28, 2017" +ABUILD_VERSION="0.10.02" TOP=$PWD @@ -581,8 +581,8 @@ export PATH=$PATH:util/abuild getopt - > /dev/null 2>/dev/null || gcc -o util/abuild/getopt util/abuild/getopt.c -# command line for xargs parallelization. Thus overwrite -c X -cmdline="$* -c 1" +# Save command line for xargs parallelization. +cmdline=("$@") # parse parameters.. try to find out whether we're running GNU getopt getoptbrand="$(getopt -V)" @@ -735,6 +735,8 @@ local ABSPATH local stime local etime + local num_targets + local cpus_per_target local targets=${*-$(get_mainboards)} # seed shared utils @@ -781,8 +783,9 @@ rmdir "${scanbuild_out}tmp" fi rm -rf "$TARGET/temp" "$TMPCFG" - # shellcheck disable=SC2086 - echo $targets | xargs -P ${cpus:-0} -n 1 "$0" $cmdline -I -t + num_targets=$(wc -w <<<"$targets") + cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets)) + echo "$targets" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "$cpus_per_target" -t } fi -- To view, visit https://review.coreboot.org/18975 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I76a1c6456ef8ab21286fdc1636d659a3b76bc5d7 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in coreboot[master]: util/futility/Makefile: Update clean target
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18998 ) Change subject: util/futility/Makefile: Update clean target ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50895/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6869/ : SUCCESS -- To view, visit https://review.coreboot.org/18998 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibcdb0e329084f58b27c3f53213a237d02c922a51 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

1 0

Change in coreboot[master]: Makefile: Update clean targets
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19000 ) Change subject: Makefile: Update clean targets ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50894/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6868/ : SUCCESS -- To view, visit https://review.coreboot.org/19000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7d25d8234528b19bf36df6845a4500dbe1cbf9a4 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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