coreboot-gerrit December 2017

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Change in coreboot[master]: mainboard/hp: Add Eliteboot Revolve 810 G1
by build bot (Jenkins) (Code Review) 22 Dec '17

22 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Eliteboot Revolve 810 G1 ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19681/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64916/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Dec 2017 06:34:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add Eliteboot Revolve 810 G1
by Bill XIE (Code Review) 22 Dec '17

22 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22972 to look at the new patch set (#2). Change subject: mainboard/hp: Add Eliteboot Revolve 810 G1 ...................................................................... mainboard/hp: Add Eliteboot Revolve 810 G1 The code is based on autoport and that for 8470p. Tested: - CPU i5-3437U - Slotted DIMM 8GiB - Soldered RAM 4GiB from Hynix (There may be more models here) - Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera) - Mini pci-e on wlan slot - USB3 ports - S3 - TPM1 on LPC Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- A src/mainboard/hp/revolve_810_g1/Kconfig A src/mainboard/hp/revolve_810_g1/Kconfig.name A src/mainboard/hp/revolve_810_g1/Makefile.inc A src/mainboard/hp/revolve_810_g1/acpi/ec.asl A src/mainboard/hp/revolve_810_g1/acpi/platform.asl A src/mainboard/hp/revolve_810_g1/acpi/superio.asl A src/mainboard/hp/revolve_810_g1/acpi_tables.c A src/mainboard/hp/revolve_810_g1/board_info.txt A src/mainboard/hp/revolve_810_g1/cmos.default A src/mainboard/hp/revolve_810_g1/cmos.layout A src/mainboard/hp/revolve_810_g1/devicetree.cb A src/mainboard/hp/revolve_810_g1/dsdt.asl A src/mainboard/hp/revolve_810_g1/gpio.c A src/mainboard/hp/revolve_810_g1/hda_verb.c A src/mainboard/hp/revolve_810_g1/mainboard.c A src/mainboard/hp/revolve_810_g1/romstage.c A src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex 17 files changed, 974 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/22972/2 -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/hp: Add CMOS support for all HP Elitebook models
by Bill XIE (Code Review) 22 Dec '17

22 Dec '17

Bill XIE has posted comments on this change. ( https://review.coreboot.org/22842 ) Change subject: mb/hp: Add CMOS support for all HP Elitebook models ...................................................................... Patch Set 1: diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index edd4202813..ccb7636d47 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -42,7 +42,7 @@ config KBC1126_FW1 config KBC1126_FW1_OFFSET string depends on KBC1126_FIRMWARE - default "0xffffe800" + default "0xfffee800" config KBC1126_FW2 string "KBC1126 filename #2 path and filename" @@ -56,6 +56,6 @@ config KBC1126_FW2 config KBC1126_FW2_OFFSET string depends on KBC1126_FIRMWARE - default "0xfffee000" + default "0xfffde000" endif -- To view, visit https://review.coreboot.org/22842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a50a25798fd31b7acccf9872c50dac2718ce895 Gerrit-Change-Number: 22842 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Dec 2017 05:56:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/hp: Add CMOS support for all HP Elitebook models
by Bill XIE (Code Review) 22 Dec '17

22 Dec '17

Bill XIE has posted comments on this change. ( https://review.coreboot.org/22842 ) Change subject: mb/hp: Add CMOS support for all HP Elitebook models ...................................................................... Patch Set 1: -Code-Review The offset of the two blobs for EC may have to be adjusted lower to fit the larger bootblock with CMOS support: -- To view, visit https://review.coreboot.org/22842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a50a25798fd31b7acccf9872c50dac2718ce895 Gerrit-Change-Number: 22842 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Dec 2017 05:56:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add Eliteboot Revolve 810 G1
by build bot (Jenkins) (Code Review) 22 Dec '17

22 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Eliteboot Revolve 810 G1 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19680/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64915/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Dec 2017 05:50:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add Eliteboot Revolve 810 G1
by Bill XIE (Code Review) 22 Dec '17

22 Dec '17

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/22972 Change subject: mainboard/hp: Add Eliteboot Revolve 810 G1 ...................................................................... mainboard/hp: Add Eliteboot Revolve 810 G1 The code is based on autoport and that for 8470p. Tested: - CPU i5-3437U - Slotted DIMM 8GiB - Soldered RAM 4GiB from Hynix (There may be more models here) - Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera) - Mini pci-e on wlan slot - USB3 ports - S3 Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- A src/mainboard/hp/revolve_810_g1/Kconfig A src/mainboard/hp/revolve_810_g1/Kconfig.name A src/mainboard/hp/revolve_810_g1/Makefile.inc A src/mainboard/hp/revolve_810_g1/acpi/ec.asl A src/mainboard/hp/revolve_810_g1/acpi/platform.asl A src/mainboard/hp/revolve_810_g1/acpi/superio.asl A src/mainboard/hp/revolve_810_g1/acpi_tables.c A src/mainboard/hp/revolve_810_g1/board_info.txt A src/mainboard/hp/revolve_810_g1/cmos.default A src/mainboard/hp/revolve_810_g1/cmos.layout A src/mainboard/hp/revolve_810_g1/devicetree.cb A src/mainboard/hp/revolve_810_g1/dsdt.asl A src/mainboard/hp/revolve_810_g1/gpio.c A src/mainboard/hp/revolve_810_g1/hda_verb.c A src/mainboard/hp/revolve_810_g1/mainboard.c A src/mainboard/hp/revolve_810_g1/romstage.c A src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex 17 files changed, 970 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/22972/1 diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig new file mode 100644 index 0000000..1d79ce4 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -0,0 +1,68 @@ +if BOARD_HP_REVOLVE_810_G1 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_SOCKET_RPGA989 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select GENERIC_SPD_BIN + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select ENABLE_VMX + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/revolve_810_g1 + +config MAINBOARD_PART_NUMBER + string + default "EliteBook Revolve 810 G1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x18f8 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig.name b/src/mainboard/hp/revolve_810_g1/Kconfig.name new file mode 100644 index 0000000..9a0c1ff --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_REVOLVE_810_G1 + bool "EliteBook Revolve 810 G1" diff --git a/src/mainboard/hp/revolve_810_g1/Makefile.inc b/src/mainboard/hp/revolve_810_g1/Makefile.inc new file mode 100644 index 0000000..7a211f4 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +# FIXME: Other varients with same size onboard ram may exist. +SPD_SOURCES = hynix_4g diff --git a/src/mainboard/hp/revolve_810_g1/acpi/ec.asl b/src/mainboard/hp/revolve_810_g1/acpi/ec.asl new file mode 100644 index 0000000..ac65fb3 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/acpi/ec.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/revolve_810_g1/acpi/platform.asl b/src/mainboard/hp/revolve_810_g1/acpi/platform.asl new file mode 100644 index 0000000..fe0f936 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/acpi/platform.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/revolve_810_g1/acpi/superio.asl b/src/mainboard/hp/revolve_810_g1/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/revolve_810_g1/acpi_tables.c b/src/mainboard/hp/revolve_810_g1/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/revolve_810_g1/board_info.txt b/src/mainboard/hp/revolve_810_g1/board_info.txt new file mode 100644 index 0000000..5f22183 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-revolve-810-g1-tablet/529… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/hp/revolve_810_g1/cmos.default b/src/mainboard/hp/revolve_810_g1/cmos.default new file mode 100644 index 0000000..7d4bb7b --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +gfx_uma_size=32M diff --git a/src/mainboard/hp/revolve_810_g1/cmos.layout b/src/mainboard/hp/revolve_810_g1/cmos.layout new file mode 100644 index 0000000..cc1fc55 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 12 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 5 r 0 unused +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb new file mode 100644 index 0000000..eee0eaf --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -0,0 +1,143 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Bill Xie <persmule(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000263" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x103c 0x18f8 + end + device pci 16.0 off # Management Engine Interface 1 + subsystemid 0x103c 0x18f8 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + subsystemid 0x103c 0x18f8 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x8086 0x18f8 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x18f8 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x18f8 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x18f8 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x18f8 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x18f8 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x18f8 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x18f8 + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x70" + device pnp ff.1 off end + end # kbc1126 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x18f8 + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x18f8 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x18f8 + end + end +end diff --git a/src/mainboard/hp/revolve_810_g1/dsdt.asl b/src/mainboard/hp/revolve_810_g1/dsdt.asl new file mode 100644 index 0000000..51934c7 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/hp/revolve_810_g1/gpio.c b/src/mainboard/hp/revolve_810_g1/gpio.c new file mode 100644 index 0000000..5a9d875 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/gpio.c @@ -0,0 +1,239 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio65 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/revolve_810_g1/hda_verb.c b/src/mainboard/hp/revolve_810_g1/hda_verb.c new file mode 100644 index 0000000..c7d5662 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/hda_verb.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e0, /* Codec Vendor / Device ID: IDT */ + 0x103c18f8, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c18f8), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + + 0x00000001, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x1, 0x103c3066), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/revolve_810_g1/mainboard.c b/src/mainboard/hp/revolve_810_g1/mainboard.c new file mode 100644 index 0000000..e9228c1 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Bill Xie <persmule(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c new file mode 100644 index 0000000..cf19789 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <cbfs.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <ec/hp/kbc1126/ec.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0201); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0101); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00fcfe01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000402e9); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x17f21feb; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 1, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ + size_t spd_file_len = 0; + void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + + if (!spd_file || spd_file_len < sizeof(spd_raw_data)) + die("SPD data for C1S0 not found."); + + read_spd(&spd[0], 0x50, id_only); + memcpy(&spd[2], spd_file, spd_file_len); +} diff --git a/src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex b/src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex new file mode 100644 index 0000000..544d576 --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex @@ -0,0 +1,16 @@ +92 11 0b 03 04 00 00 01 03 52 01 08 0a 00 80 00 +6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 b6 3b +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com>

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Change in coreboot[master]: libpayload/arch/x86: support read cpu speed from msr
by build bot (Jenkins) (Code Review) 22 Dec '17

22 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22943 ) Change subject: libpayload/arch/x86: support read cpu speed from msr ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19679/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64914/ : SUCCESS -- To view, visit https://review.coreboot.org/22943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69da73ab479785c7b5d8add15705c1cd42925a75 Gerrit-Change-Number: 22943 Gerrit-PatchSet: 5 Gerrit-Owner: JianfengX Zhou <jianfengx.zhou(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: JianfengX Zhou <jianfengx.zhou(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Dec 2017 05:01:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy: Set S0ix lazy wake mask
by build bot (Jenkins) (Code Review) 22 Dec '17

22 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21086 ) Change subject: mb/google/poppy: Set S0ix lazy wake mask ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19678/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64913/ : SUCCESS -- To view, visit https://review.coreboot.org/21086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab Gerrit-Change-Number: 21086 Gerrit-PatchSet: 5 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Dec 2017 03:51:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Add SoC API to make use SMM common code
by build bot (Jenkins) (Code Review) 22 Dec '17

22 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22870 ) Change subject: soc/intel/cannonlake: Add SoC API to make use SMM common code ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19677/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64912/ : SUCCESS -- To view, visit https://review.coreboot.org/22870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If526cbae9afee47fa272bdf74e04416aff100e88 Gerrit-Change-Number: 22870 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 22 Dec 2017 01:53:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in Normal mode
by build bot (Jenkins) (Code Review) 21 Dec '17

21 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22799 ) Change subject: soc/intel/cannonlake: Initialize DDI-A lane in Normal mode ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19668/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64911/ : SUCCESS -- To view, visit https://review.coreboot.org/22799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 6 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Dec 2017 23:14:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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