coreboot-gerrit December 2017

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Change in coreboot[master]: mb/google/poppy: Remove variant_cros_gpios from variants
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22705 ) Change subject: mb/google/poppy: Remove variant_cros_gpios from variants ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64178/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19008/ : SUCCESS -- To view, visit https://review.coreboot.org/22705 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b Gerrit-Change-Number: 22705 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:45:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Add config option for camera ACPI support
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22702 ) Change subject: mb/google/poppy: Add config option for camera ACPI support ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64177/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19007/ : SUCCESS -- To view, visit https://review.coreboot.org/22702 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06 Gerrit-Change-Number: 22702 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:42:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22701 ) Change subject: mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_* ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64176/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19006/ : SUCCESS -- To view, visit https://review.coreboot.org/22701 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61 Gerrit-Change-Number: 22701 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:40:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Remove dynamic disabling of TPM
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22704 ) Change subject: mb/google/poppy: Remove dynamic disabling of TPM ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64174/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19004/ : SUCCESS -- To view, visit https://review.coreboot.org/22704 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80 Gerrit-Change-Number: 22704 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:36:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/soraka: Disable SPI TPM
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22699 ) Change subject: mb/google/poppy/variants/soraka: Disable SPI TPM ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64172/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19002/ : SUCCESS -- To view, visit https://review.coreboot.org/22699 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3 Gerrit-Change-Number: 22699 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:34:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Disable SPI TPM
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22698 ) Change subject: mb/google/poppy: Disable SPI TPM ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64173/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/19003/ : SUCCESS -- To view, visit https://review.coreboot.org/22698 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Gerrit-Change-Number: 22698 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:33:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add support for nami board
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22703 ) Change subject: mb/google/poppy/variants/nami: Add support for nami board ...................................................................... Patch Set 7: No Builds Executed -- To view, visit https://review.coreboot.org/22703 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Gerrit-Change-Number: 22703 Gerrit-PatchSet: 7 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:31:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add support for nami board
by build bot (Jenkins) (Code Review) 06 Dec '17

06 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22703 ) Change subject: mb/google/poppy/variants/nami: Add support for nami board ...................................................................... Patch Set 6: No Builds Executed -- To view, visit https://review.coreboot.org/22703 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Gerrit-Change-Number: 22703 Gerrit-PatchSet: 6 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Dec 2017 08:29:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/kahlee: Update GPIOs
by Martin Roth (Code Review) 06 Dec '17

06 Dec '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22751 Change subject: mainboard/google/kahlee: Update GPIOs ...................................................................... mainboard/google/kahlee: Update GPIOs - The touchscreen interrupt was moved from the GPIO 3, as originally suggested to GPIO 11. This changes the gevent from 2 to 18. - Set device enables to high. - Remove Extra SCI comment from GPIO 130. - Set PCIe reset pins to high. BUG=b:70234300, b:69681660 TEST=build grunt Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/22751/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 34b5cee..9308d69 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -35,11 +35,11 @@ /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ { GPIO_2, Function0, FCH_GPIO_PULL_UP_ENABLE }, - /* GPIO_3 - TOUCHSCREEN_INT_3V3_ODL, SCI */ + /* GPIO_3 - MEM_VOLT_SEL */ { GPIO_3, Function0, FCH_GPIO_PULL_UP_ENABLE }, /* GPIO_4 - EN_PP3300_WLAN */ - { GPIO_4, Function0, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_4, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ { GPIO_5, Function0, FCH_GPIO_PULL_UP_ENABLE }, @@ -59,7 +59,7 @@ /* GPIO_10 - SLP_S0_L */ { GPIO_10, Function0, FCH_GPIO_PULL_UP_ENABLE }, - /* GPIO_11 - Unused (R166) */ + /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ { GPIO_11, Function0, FCH_GPIO_PULL_UP_ENABLE }, /* GPIO_12 - Unused (TP126) */ @@ -103,7 +103,7 @@ { GPIO_25, Function0, FCH_GPIO_PULL_UP_ENABLE }, /* GPIO_26 - APU_PCIE_RST_L */ - { GPIO_26, Function0, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_26, Function1, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, /* GPIO_40 - Unused */ { GPIO_40, Function0, FCH_GPIO_PULL_UP_ENABLE }, @@ -115,7 +115,7 @@ { GPIO_67, Function0, FCH_GPIO_OUTPUT_VALUE }, /* GPIO_70 - WLAN_PE_RST */ - { GPIO_70, Function0, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_70, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, /* GPIO_74 - LPC_CLK0_EC_R */ { GPIO_74, Function0, FCH_GPIO_PULL_DOWN_ENABLE }, @@ -124,7 +124,7 @@ { GPIO_75, Function0, FCH_GPIO_PULL_UP_ENABLE }, /* GPIO_76 - EN_PP3300_TOUCHSCREEN */ - { GPIO_76, Function0, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_76, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, /* GPIO_84 - HUB_RST */ { GPIO_84, Function1, FCH_GPIO_OUTPUT_VALUE }, @@ -142,10 +142,10 @@ { GPIO_88, Function0, }, /* GPIO_90 - EN_PP3300_CAMERA */ - { GPIO_90, Function0, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_90, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, /* GPIO_91 - EN_PP3300_TRACKPAD */ - { GPIO_91, Function1, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_91, Function1, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ { GPIO_92, Function0, FCH_GPIO_PULL_UP_ENABLE }, @@ -198,7 +198,7 @@ /* GPIO_129 - APU_KBRST_L */ { GPIO_129, Function0, FCH_GPIO_PULL_UP_ENABLE }, - /* GPIO_130 - Unused, SCI */ + /* GPIO_130 - Unused */ { GPIO_130, Function1, FCH_GPIO_PULL_UP_ENABLE }, /* GPIO_131 - CONFIG_STRAP3 */ @@ -266,14 +266,6 @@ */ static const struct sci_source gpe_table[] = { - /* TOUCHSCREEN_INT_3V3_ODL */ - { - .scimap = 2, - .gpe = 2, - .direction = SMI_SCI_LVL_HIGH, - .level = SMI_SCI_EDG, - }, - /* PCH_TRACKPAD_INT_3V3_ODL */ { .scimap = 7, @@ -298,6 +290,14 @@ .level = SMI_SCI_LVL, }, + /* TOUCHSCREEN_INT_3V3_ODL */ + { + .scimap = 18, + .gpe = 18, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG, + }, + /* APU_PEN_PDCT_ODL */ { .scimap = 21, -- To view, visit https://review.coreboot.org/22751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Gerrit-Change-Number: 22751 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mainboard/google/kahlee: Update PCIe port map
by Martin Roth (Code Review) 06 Dec '17

06 Dec '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22750 Change subject: mainboard/google/kahlee: Update PCIe port map ...................................................................... mainboard/google/kahlee: Update PCIe port map - Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on PCIe port 1, so move the OemCustomize file into the variant directory. - Add comments in baseboard version so it's easier to understand. - Update reset pins, put the definitions in gpio.h BUG=b:67309216 TEST=Build and boot Kahlee. Build Grunt. Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/Makefile.inc M src/mainboard/google/kahlee/variants/baseboard/Makefile.inc A src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/kahlee/variants/kahlee/Makefile.inc R src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h 7 files changed, 171 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/22750/1 diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 55c80a4..770a999 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock/bootblock.c bootblock-y += BiosCallOuts.c -bootblock-y += bootblock/OemCustomize.c bootblock-y += ec.c romstage-y += BiosCallOuts.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index 83eec96..fcaf365 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -14,6 +14,7 @@ # bootblock-y += gpio.c +bootblock-y += OemCustomize.c romstage-y += gpio.c romstage-y += memory.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c new file mode 100644 index 0000000..b46c2da --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <agesawrapper.h> +#include <variant/gpio.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 1, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + 0, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 2, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_0_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 3, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_1_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 4, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_2_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 5, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_3_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, +}; + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DDI0 - eDP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1) + }, + /* DDI1 - DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DDI2 - DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID __attribute__((weak)) OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; + InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; + InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; +} diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index c003673..0ad6740 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -28,6 +28,12 @@ #define CROS_WP_GPIO GPIO_122 #define GPIO_EC_IN_RW GPIO_15 +/* PCIe reset pins */ +#define PCIE_0_RST GPIO_70 +#define PCIE_1_RST 0 +#define PCIE_2_RST GPIO_26 +#define PCIE_3_RST 0 + #endif /* _ACPI__ */ #define EC_SCI_GPI 22 diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc index 83eec96..fcaf365 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc @@ -14,6 +14,7 @@ # bootblock-y += gpio.c +bootblock-y += OemCustomize.c romstage-y += gpio.c romstage-y += memory.c diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c similarity index 95% rename from src/mainboard/google/kahlee/bootblock/OemCustomize.c rename to src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c index 0551184..7451847 100644 --- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/kahlee/OemCustomize.c @@ -14,6 +14,7 @@ */ #include <agesawrapper.h> +#include <variant/gpio.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ @@ -25,7 +26,7 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmL0sL1, 0x04, 0) + AspmL0sL1, 0, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */ { @@ -36,7 +37,7 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmL0sL1, 0x2, 0) + AspmL0sL1, PCIE_0_RST, 0) }, /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */ { @@ -47,7 +48,7 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmL0sL1, 0x3, 0) + AspmL0sL1, PCIE_1_RST, 0) }, /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */ { @@ -58,7 +59,7 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmL0sL1, 0, 0) + AspmL0sL1, PCIE_2_RST, 0) }, /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */ { @@ -69,7 +70,7 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmL0sL1, 0, 0) + AspmL0sL1, PCIE_3_RST, 0) }, }; diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h index e7097c2..cf62138 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h @@ -32,6 +32,12 @@ #define CROS_WP_GPIO GPIO_142 #define GPIO_EC_IN_RW GPIO_15 +/* PCIe reset pins */ +#define PCIE_0_RST GPIO_26 +#define PCIE_1_RST GPIO_26 +#define PCIE_2_RST 0 +#define PCIE_3_RST 0 + #endif /* _ACPI__ */ /* AGPIO22 -> GPE3 */ -- To view, visit https://review.coreboot.org/22750 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Gerrit-Change-Number: 22750 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit December 2017