Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16332
-gerrit
commit 4958606148705e4bb2c9bb7326b623a3a84f6b03
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Aug 26 21:16:01 2016 +0530
soc/intel/skylake: Use postcar functions for setting up new stack
Setup stack and MTRRs using the postcar funtions provided
in postcar_loader.c.
Change-Id: Ia5771e70386dbae9fa181e3635021dd187345123
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/soc/intel/skylake/romstage/romstage_fsp20.c | 49 +++++++++++++++++++++++--
1 file changed, 46 insertions(+), 3 deletions(-)
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 57b2a52..4e88897 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -24,16 +24,24 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <fsp/util.h>
+#include <fsp/memmap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <timestamp.h>
#include <vboot/vboot_common.h>
+/*
+ * Romstage needs some stack for decompressing ramstage images, since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
asmlinkage void *car_stage_c_entry(void)
{
bool s3wake;
- void *top_of_stack;
+ struct postcar_frame pcf;
+ uintptr_t top_of_ram;
struct chipset_power_state *ps;
console_init();
@@ -46,8 +54,43 @@ asmlinkage void *car_stage_c_entry(void)
s3wake = ps->prev_sleep_state == ACPI_S3;
fsp_memory_init(s3wake);
- top_of_stack = setup_stack_and_mtrrs();
- return top_of_stack;
+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ die("Unable to initialize postcar frame.\n");
+
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ void *smm_base;
+ size_t smm_size;
+ uintptr_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uintptr_t)smm_base;
+ postcar_frame_add_mtrr(&pcf, tseg_base, smm_size,
+ MTRR_TYPE_WRBACK);
+ }
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
+ CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+ return postcar_commit_mtrrs(&pcf);
}
static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16513
-gerrit
commit 10aa200c2b781dab0b55d3b13de9e4e46a801505
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Tue Sep 6 23:53:32 2016 +0200
i945/gma.c: Only init LVDS if it is detected
Some devices have no LVDS output but if no VGA is connected or
no EDID can be found, it will try to init LVDS.
This patches detects the presence of an LVDS panel and
makes sure only that only VGA is initialised in the absence of an LVDS panel.
Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/northbridge/intel/i945/gma.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index abe7dd6..adaea13 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -555,18 +555,20 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
/* compare the header of the vga edid header */
/* if vga is not connected it should have a correct header */
-static int vga_connected(u8 *pmmio) {
+static int probe_edid(u8 *pmmio, u8 slave)
+{
u8 vga_edid[128];
u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
- intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128);
+ intel_gmbus_read_edid(pmmio + GMBUS0, slave, 0x50, vga_edid, 128);
intel_gmbus_stop(pmmio + GMBUS0);
for (int i = 0; i < 8; i++) {
if (vga_edid[i] != header[i]) {
- printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n");
+ printk(BIOS_DEBUG, "Slave %d is not connected\n",
+ slave);
return 0;
}
}
- printk(BIOS_SPEW, "VGA display connected\n");
+ printk(BIOS_SPEW, "Slave %d is connected\n", slave);
return 1;
}
@@ -611,7 +613,9 @@ static void gma_func0_init(struct device *dev)
);
int err;
- if (vga_connected(mmiobase))
+ /* probe if VGA is connected and alway run */
+ /* VGA init if no LVDS is connected */
+ if (!probe_edid(mmiobase, 3) || probe_edid(mmiobase, 2))
err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
iobase, mmiobase, graphics_base);
else