the following patch was just integrated into master:
commit e52592078e8e5b24b45197ab510236193656f68e
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com>
Date: Fri Sep 2 16:07:08 2016 -0700
mainboard/google/reef: Enable audio clock and power gate
Removes S0ix blocker. Sets audio clock gate and power gate
bits when audio not in use. Reduces power in S0.
Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com>
Reviewed-on: https://review.coreboot.org/16424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16424 for details.
-gerrit
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16509
-gerrit
commit dc19d31b0a0db06f2b4f073d0b901102c6e80e5c
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Sep 7 20:18:17 2016 +0530
arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.
To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.
Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/postcar_loader.c | 59 +++++++++++++++++++++++++++----------------
1 file changed, 37 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b5d8db0..d9719ff 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -59,29 +59,44 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type)
{
- size_t align;
-
- if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
- printk(BIOS_ERR, "No more variable MTRRs: %d\n",
- pcf->max_var_mttrs);
- return;
- }
-
- /* Determine address alignment by lowest bit set in address. */
- align = addr & (addr ^ (addr - 1));
-
- if (align < size) {
- printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n",
- addr, align, size);
- size = align;
+ /*
+ * Utilize additional MTRRs if the specified size is greater than the
+ * base address alignment.
+ */
+ while (size != 0) {
+ uint32_t addr_lsb;
+ uint32_t size_msb;
+ uint32_t mtrr_size;
+
+ if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
+ printk(BIOS_ERR, "No more variable MTRRs: %d\n",
+ pcf->max_var_mttrs);
+ return;
+ }
+
+ addr_lsb = fls(addr);
+ size_msb = fms(size);
+
+ /* All MTRR entries need to have their base aligned to the mask
+ * size. The maximum size is calculated by a function of the
+ * min base bit set and maximum size bit set. */
+ if (addr_lsb > size_msb)
+ mtrr_size = 1 << size_msb;
+ else
+ mtrr_size = 1 << addr_lsb;
+
+ printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %x)\n",
+ addr, addr + mtrr_size, mtrr_size);
+
+ stack_push(pcf, pcf->upper_mask);
+ stack_push(pcf, ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID);
+ stack_push(pcf, 0);
+ stack_push(pcf, addr | type);
+ pcf->num_var_mttrs++;
+
+ size -= mtrr_size;
+ addr += mtrr_size;
}
-
- /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */
- stack_push(pcf, pcf->upper_mask);
- stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID);
- stack_push(pcf, 0);
- stack_push(pcf, addr | type);
- pcf->num_var_mttrs++;
}
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301
-gerrit
commit b4bdb519d2faeed94fe2f03857f77d5fcd5bebd0
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 13:38:19 2016 +0530
kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.
Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/mainboard/intel/kunimitsu/Makefile.inc | 4 ++++
src/mainboard/intel/kunimitsu/ramstage.c | 2 +-
src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index cafa12c..86be420 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -34,3 +34,7 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
+endif
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..44fb9cd 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
new file mode 100644
index 0000000..10bdd21
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* TODO: Read and copy SPD and fill up Rcomp and DQ param */
+}
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 62d6fd4..0a9cb0f 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
-romstage-y += spd.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin
the following patch was just integrated into master:
commit 587f9cb6ce7ee71ce242d2df47f2cd51f4dac66b
Author: Antonello Dettori <dev(a)dettori.io>
Date: Fri Sep 2 12:50:16 2016 +0200
northbridge/amd/lx: remove unused function declaration
Remove an unusued function declaration that caused problems while
compiling the target.
Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16435
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16435 for details.
-gerrit
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16509
-gerrit
commit 1b8676537b44e81346546d44471090ec6f3b2945
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Sep 7 20:18:17 2016 +0530
arch/x86: Configure additional MTRRs to cover specified size
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.
To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.
Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/postcar_loader.c | 59 +++++++++++++++++++++++++++----------------
1 file changed, 37 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b5d8db0..d9719ff 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -59,29 +59,44 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type)
{
- size_t align;
-
- if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
- printk(BIOS_ERR, "No more variable MTRRs: %d\n",
- pcf->max_var_mttrs);
- return;
- }
-
- /* Determine address alignment by lowest bit set in address. */
- align = addr & (addr ^ (addr - 1));
-
- if (align < size) {
- printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n",
- addr, align, size);
- size = align;
+ /*
+ * Utilize additional MTRRs if the specified size is greater than the
+ * base address alignment.
+ */
+ while (size != 0) {
+ uint32_t addr_lsb;
+ uint32_t size_msb;
+ uint32_t mtrr_size;
+
+ if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
+ printk(BIOS_ERR, "No more variable MTRRs: %d\n",
+ pcf->max_var_mttrs);
+ return;
+ }
+
+ addr_lsb = fls(addr);
+ size_msb = fms(size);
+
+ /* All MTRR entries need to have their base aligned to the mask
+ * size. The maximum size is calculated by a function of the
+ * min base bit set and maximum size bit set. */
+ if (addr_lsb > size_msb)
+ mtrr_size = 1 << size_msb;
+ else
+ mtrr_size = 1 << addr_lsb;
+
+ printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %x)\n",
+ addr, addr + mtrr_size, mtrr_size);
+
+ stack_push(pcf, pcf->upper_mask);
+ stack_push(pcf, ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID);
+ stack_push(pcf, 0);
+ stack_push(pcf, addr | type);
+ pcf->num_var_mttrs++;
+
+ size -= mtrr_size;
+ addr += mtrr_size;
}
-
- /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */
- stack_push(pcf, pcf->upper_mask);
- stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID);
- stack_push(pcf, 0);
- stack_push(pcf, addr | type);
- pcf->num_var_mttrs++;
}
void *postcar_commit_mtrrs(struct postcar_frame *pcf)