Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit 510452cbfdc26e107fb5d9e7597e864c9a208b42
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 56 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 5 +++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..44838bc
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH, 0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store(PMC_BAR0,IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store(MCH_BASE_ADDR+MAILBOX_DATA,MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store(MCH_BASE_ADDR+MAILBOX_INTF,MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store(PMC_SRAM_BASE_0,SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..f31a086 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,11 @@
#include "xhci.asl"
+#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
+ /* PMC IPC */
+ #include "pmc_ipc.asl"
+#endif
+
/* LPC */
#include "lpc.asl"
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit b9e779de5fa0589ca0556bb379704c3ff34687a6
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 56 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 5 +++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..27a4bad
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, 0x480, 0x04, PMIO_LENGTH) //Fixed ACPI MMIO BASE
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store(PMC_BAR0,IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store(MCH_BASE_ADDR+MAILBOX_DATA,MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store(MCH_BASE_ADDR+MAILBOX_INTF,MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store(PMC_SRAM_BASE_0,SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..f31a086 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,11 @@
#include "xhci.asl"
+#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
+ /* PMC IPC */
+ #include "pmc_ipc.asl"
+#endif
+
/* LPC */
#include "lpc.asl"
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit d4860b7c64544bd113a94e45882881bd0a68ac24
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 56 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 5 +++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..27a4bad
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, 0x480, 0x04, PMIO_LENGTH) //Fixed ACPI MMIO BASE
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store(PMC_BAR0,IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store(MCH_BASE_ADDR+MAILBOX_DATA,MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store(MCH_BASE_ADDR+MAILBOX_INTF,MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store(PMC_SRAM_BASE_0,SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..f31a086 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,11 @@
#include "xhci.asl"
+#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
+ /* PMC IPC */
+ #include "pmc_ipc.asl"
+#endif
+
/* LPC */
#include "lpc.asl"
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit 8a8732f979a2ed1dde904c73a512a49c5b6a3bb9
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The ACPI
mode entry include resources for PMC_IPC, SRAM, ACPI IO and Punit Mailbox.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 56 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 5 +++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..27a4bad
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, 0x480, 0x04, PMIO_LENGTH) //Fixed ACPI MMIO BASE
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store(PMC_BAR0,IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store(MCH_BASE_ADDR+MAILBOX_DATA,MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store(MCH_BASE_ADDR+MAILBOX_INTF,MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store(PMC_SRAM_BASE_0,SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..f31a086 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,11 @@
#include "xhci.asl"
+#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
+ /* PMC IPC */
+ #include "pmc_ipc.asl"
+#endif
+
/* LPC */
#include "lpc.asl"
the following patch was just integrated into master:
commit 1c8491c3ab75cc54c5288552b3ffb8513a3488aa
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Aug 15 17:58:05 2016 -0700
gru: Add USB 2.0 PHY tuning for Kevin
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.
BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.
Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84
Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/370900
Original-Reviewed-by: Guenter Roeck <groeck(a)chromium.org>
Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16265 for details.
-gerrit
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16647
-gerrit
commit 3dd9f11e57b8b8bfabf290af7a831ca591ffb007
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Mon Sep 19 14:55:24 2016 -0700
soc/apollolake: Correct the comment section in gpio.asl
This patch corrects the comment section in gpio.asl for
GPE method.
Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/soc/intel/apollolake/acpi/gpio.asl | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 4f3bc3e..ffc5b75 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -191,7 +191,8 @@ scope (\_SB) {
Scope(\_GPE)
{
- /* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
+ /*
+ * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
* _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
* register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
* GPE0a_EN at 0x430 is reserved.