the following patch was just integrated into master:
commit a2d4062d427d18127707306dada5e79d69bd3691
Author: Naresh G Solanki <naresh.solanki(a)intel.com>
Date: Tue Aug 30 20:47:13 2016 +0530
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16592 for details.
-gerrit
the following patch was just integrated into master:
commit 21130c6508161ada1d28c90a4003c89afc3fd162
Author: Naresh G Solanki <naresh.solanki(a)intel.com>
Date: Thu Sep 15 18:14:28 2016 +0530
driver/intel/fsp1_1: Utilise soc/intel/common for adding vbt.bin
Remove fsp1.1 driver code that adds vbt.bin & use soc/intel/common
instead to add vbt.bin in cbfs.
Also, VBT blob is added to CBFS as RAW type hence when walking the
CBFS to find vbt.bin, search with type as RAW.
Change-Id: I08f2556a34f83a0ea2b67b003e51dcace994361b
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-on: https://review.coreboot.org/16610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16610 for details.
-gerrit
the following patch was just integrated into master:
commit 767009aeab7986faa2a86b7c33fdc2a303583139
Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com>
Date: Thu Sep 15 14:02:54 2016 -0700
mainboard/google/reef: Configure WLAN as wake source
This implements PRW method for WLAN and configures PCIe wake pin to
generate SCI.
BUG=chrome-os-partner:56483
TEST=Suspend the system into S3 or S0ix. System should resume through wake
event from wifi.
Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7
Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com>
Reviewed-on: https://review.coreboot.org/16611
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16611 for details.
-gerrit
the following patch was just integrated into master:
commit ec9168f52b734bb6ea116cdd28407dbabc784f5d
Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com>
Date: Fri Sep 16 14:20:53 2016 -0700
soc/intel/apollolake: Configure ACPI name for PCIe
This implements acpi name for PCIe root port.
BUG=chrome-os-partner:56483
Change-Id: Ifec1529c477f554d36f3932b66f62eea782fdcaa
Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com>
Reviewed-on: https://review.coreboot.org/16621
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16621 for details.
-gerrit
the following patch was just integrated into master:
commit c33f08b6724f8567c5ccea546f57775f264974a9
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Sep 16 19:45:08 2016 +0530
kunimitsu: Remove incorrect dereferencing of pointer
In spd_util.c function mainboard_get_spd_data(), spd_file can
either be NULL or will point to the first byte of the SPD data,
and should not be dereferenced.
Change-Id: I08677976792682cc744ec509dd183eadf5e570a5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-on: https://review.coreboot.org/16612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16612 for details.
-gerrit
the following patch was just integrated into master:
commit 0b1a5c259b92ce6685577af631c2b76134514eab
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Thu Sep 8 22:21:54 2016 +0200
gm45/gma.c: use correct id string for fake VBT
The correct id string for gm45 is "$VBT CANTIGA ".
This can be found in the gm45 option rom:
"strings vbios.bin | grep VBT".
Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16551
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16551 for details.
-gerrit
the following patch was just integrated into master:
commit c51522f516ac8a8ab094449446d94bb7006226b7
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Sat Aug 27 01:09:19 2016 +0200
nb/gm45/gma.c: enable VESA framebuffer mode on VGA output
This implements "Keep VESA framebuffer" behavior on VGA output of gm45.
This patch reuses Linux code to compute vga divisors.
Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16338
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16338 for details.
-gerrit