coreboot-gerrit June 2016

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Patch set updated for coreboot: soc/intel/apollolake: Add GPE routing code
by Shaunak Saha 30 Jun '16

30 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15324 -gerrit commit 215f9b58e761085d16fb1b3497d1dde16398b0ad Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 02:06:28 2016 -0700 soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.h | 6 ++ src/soc/intel/apollolake/gpio.c | 57 +++++++++++++ src/soc/intel/apollolake/include/soc/gpe.h | 102 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 12 +++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 21 +++++ src/soc/intel/apollolake/include/soc/pm.h | 18 +++- src/soc/intel/apollolake/pmc.c | 59 +++++++++++++ 7 files changed, 274 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..5571672 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/pm.h> + #define CLKREQ_DISABLED 0xf /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ @@ -79,6 +81,10 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d0ef648..4f2203f 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -19,6 +19,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/iosf.h> +#include <soc/pm.h> /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ static const struct pad_community { @@ -132,3 +133,59 @@ const char *gpio_acpi_path(gpio_t gpio_num) return NULL; } + +/* Helper function to map PMC register groups to tier1 sci groups */ +static int pmc_gpe_route_to_gpio(int route) +{ + switch(route) { + case PMC_GPE_SW_31_0: + return GPIO_GPE_SW_31_0; + case PMC_GPE_SW_63_32: + return GPIO_GPE_SW_63_32; + case PMC_GPE_NW_31_0: + return GPIO_GPE_NW_31_0; + case PMC_GPE_NW_63_32: + return GPIO_GPE_NW_63_32; + case PMC_GPE_NW_95_64: + return GPIO_GPE_NW_95_64; + case PMC_GPE_N_31_0: + return GPIO_GPE_N_31_0; + case PMC_GPE_N_63_32: + return GPIO_GPE_N_63_32; + case PMC_GPE_W_31_0: + return GPIO_GPE_W_31_0; + default: + return -1; + } +} + +void gpio_route_gpe(int gpe0b, int gpe0c, int gpe0d) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + uint32_t value; + + /* Get the group here for community specific MISCCFG register */ + gpe0b = pmc_gpe_route_to_gpio(gpe0b); + gpe0c = pmc_gpe_route_to_gpio(gpe0c); + gpe0d = pmc_gpe_route_to_gpio(gpe0d); + + misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; + misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; + misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; + + /* Program GPIO_MISCCFG */ + misccfg_mask = ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + + for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { + const struct pad_community *comm = &gpio_communities[i]; + + value = iosf_read(comm->port, GPIO_MISCCFG); + value &= misccfg_mask; + value |= misccfg_value; + iosf_write(comm->port, GPIO_MISCCFG, value); + } +} diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 8abbad8..5482ed3 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -34,4 +34,106 @@ #define GPE0A_SMB_WAK_STS 16 #define GPE0A_SATA_PME_STS 17 +/* Group DW0 is reserved in Apollolake */ + +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_127_96 */ +#define GPE0_DW3_00 96 +#define GPE0_DW3_01 97 +#define GPE0_DW3_02 98 +#define GPE0_DW3_03 99 +#define GPE0_DW3_04 100 +#define GPE0_DW3_05 101 +#define GPE0_DW3_06 102 +#define GPE0_DW3_07 103 +#define GPE0_DW3_08 104 +#define GPE0_DW3_09 105 +#define GPE0_DW3_10 106 +#define GPE0_DW3_11 107 +#define GPE0_DW3_12 108 +#define GPE0_DW3_13 109 +#define GPE0_DW3_14 110 +#define GPE0_DW3_15 111 +#define GPE0_DW3_16 112 +#define GPE0_DW3_17 113 +#define GPE0_DW3_18 114 +#define GPE0_DW3_19 115 +#define GPE0_DW3_20 116 +#define GPE0_DW3_21 117 +#define GPE0_DW3_22 118 +#define GPE0_DW3_23 119 +#define GPE0_DW3_24 120 +#define GPE0_DW3_25 121 +#define GPE0_DW3_26 122 +#define GPE0_DW3_27 123 +#define GPE0_DW3_28 124 +#define GPE0_DW3_29 125 +#define GPE0_DW3_30 126 +#define GPE0_DW3_31 127 + #endif diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index c9d32cc..a829a2a 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -99,5 +99,17 @@ struct pad_config { void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +/* + * Set the GPIO groups for the GPE blocks. We pass the values from PMC register + * GPE_CFG which is then mapped to proper groups for MISCCFG. The gpe0_route is + * interpreted as the packed configuration for GPE0_DW[2:0]. This basically + * sets the MISCCFG register bits: + * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. + * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. + * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. + */ +void gpio_route_gpe(int gpe0b, int gpe0c, int gpe0d); + #endif /* __ACPI__ */ + #endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 30c4bdb..e64783f 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,27 @@ #ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ #define _SOC_APOLLOLAKE_GPIO_DEFS_H_ +/* + * There are 8 GPIO groups. GPP_0 -> GPP_8 (Group 3 is not present) + */ +#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */ +#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */ +#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */ +#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */ +#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */ +#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */ +#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */ +#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */ + +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration */ + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 72f74a6..9628323 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_PM_H_ #include <stdint.h> +#include <soc/gpio_defs.h> /* ACPI_BASE_ADDRESS */ @@ -129,10 +130,25 @@ # define RPS (1 << 2) #define GEN_PMCON3 0x1028 #define ETR 0x1048 +#define GPIO_GPE_CFG 0x1050 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 +#define GPE0_DW3_SHIFT 12 + +/* GPE_CFG */ +#define PMC_GPE_SW_31_0 0 +#define PMC_GPE_SW_63_32 1 +#define PMC_GPE_NW_31_0 3 +#define PMC_GPE_NW_63_32 4 +#define PMC_GPE_NW_95_64 5 +#define PMC_GPE_N_31_0 6 +#define PMC_GPE_N_63_32 7 +#define PMC_GPE_W_31_0 9 + # define CF9_LOCK (1 << 31) # define CF9_GLB_RST (1 << 20) - /* Generic sleep state types */ #define SLEEP_STATE_S0 0 #define SLEEP_STATE_S3 3 diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index c88e14c..5fe3a7c 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -18,8 +18,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <console/console.h> #include <soc/iomap.h> #include <soc/pci_ids.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include "chip.h" /* * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases @@ -58,10 +63,64 @@ static void set_resources(device_t dev) report_resource_stored(dev, res, " ACPI BAR"); } +static void pmc_gpe_init(void) +{ + uint32_t gpio_cfg = 0; + uint32_t gpio_cfg_reg; + struct soc_intel_apollolake_config *config; + + struct device *dev = NB_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + uintptr_t pmc_bar = get_pmc_mmio_bar(); + + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW3_SHIFT); + + /* Making sure that bad values don't bleed into the other fields */ + config->gpe0_dw1 &= GPE0_DWX_MASK; + config->gpe0_dw2 &= GPE0_DWX_MASK; + config->gpe0_dw3 &= GPE0_DWX_MASK; + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. + * DW0 is reserved/unused */ + if (config->gpe0_dw1 == config->gpe0_dw2 || + config->gpe0_dw2 == config->gpe0_dw3) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw3 << GPE0_DW3_SHIFT; + } + + gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + + write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(config->gpe0_dw1, config->gpe0_dw2, config->gpe0_dw3); +} + +static void pmc_init(struct device *dev) +{ + /* Set up GPE configuration */ + pmc_gpe_init(); +} + static const struct device_operations device_ops = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, + .init = &pmc_init, }; static const struct pci_driver pmc __pci_driver = {

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Patch set updated for coreboot: skylake: Generate ACPI timing values for I2C devices
by Duncan Laurie 30 Jun '16

30 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15291 -gerrit commit 1652442731d81186e44fe2e82e6dac6787e1f3b5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 21 10:41:19 2016 -0700 skylake: Generate ACPI timing values for I2C devices Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/common/lpss_i2c.c | 44 +++++++++++++++++++++++++++++- src/soc/intel/common/lpss_i2c.h | 13 +++------ src/soc/intel/skylake/acpi/serialio.asl | 19 ------------- src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/i2c.c | 47 ++++++++++++++++++++++++++------- src/soc/intel/skylake/romstage/i2c.c | 14 +++++++++- 6 files changed, 100 insertions(+), 40 deletions(-) diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c index bb684e2..a9bbbb3 100644 --- a/src/soc/intel/common/lpss_i2c.c +++ b/src/soc/intel/common/lpss_i2c.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <device/device.h> #include <device/i2c.h> +#include <string.h> #include <timer.h> #include "lpss_i2c.h" @@ -305,7 +306,17 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) return 0; } -void lpss_i2c_acpi_write_speed_config( +/* + * Write ACPI object to describe speed configuration. + * + * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold } + * + * SSCN: I2C_SPEED_STANDARD + * FMCN: I2C_SPEED_FAST + * FPCN: I2C_SPEED_FAST_PLUS + * HSCN: I2C_SPEED_HIGH + */ +static void lpss_i2c_acpi_write_speed_config( const struct lpss_i2c_speed_config *config) { if (!config) @@ -330,6 +341,37 @@ void lpss_i2c_acpi_write_speed_config( acpigen_pop_len(); } +void lpss_i2c_acpi_fill_ssdt(const struct lpss_i2c_speed_config *override) +{ + const struct lpss_i2c_speed_config *sptr; + struct lpss_i2c_speed_config sgen; + enum i2c_speed speeds[LPSS_I2C_SPEED_CONFIG_COUNT] = { + I2C_SPEED_STANDARD, + I2C_SPEED_FAST, + I2C_SPEED_FAST_PLUS, + I2C_SPEED_HIGH, + }; + int i; + + /* Report timing values for the OS driver */ + for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { + /* Generate speed config for default case */ + if (lpss_i2c_gen_speed_config(speeds[i], &sgen) < 0) + continue; + + /* Apply board specific override for this speed if found */ + for (sptr = override; sptr && sptr->speed; sptr++) { + if (sptr->speed == speeds[i]) { + memcpy(&sgen, sptr, sizeof(sgen)); + break; + } + } + + /* Generate ACPI based on selected speed config */ + lpss_i2c_acpi_write_speed_config(&sgen); + } +} + int lpss_i2c_set_speed_config(unsigned bus, const struct lpss_i2c_speed_config *config) { diff --git a/src/soc/intel/common/lpss_i2c.h b/src/soc/intel/common/lpss_i2c.h index 1ca23b5..3ec9213 100644 --- a/src/soc/intel/common/lpss_i2c.h +++ b/src/soc/intel/common/lpss_i2c.h @@ -85,17 +85,10 @@ int lpss_i2c_set_speed_config(unsigned bus, const struct lpss_i2c_speed_config *config); /* - * Write ACPI object to describe speed configuration. - * - * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold } - * - * SSCN: I2C_SPEED_STANDARD - * FMCN: I2C_SPEED_FAST - * FPCN: I2C_SPEED_FAST_PLUS - * HSCN: I2C_SPEED_HIGH + * Generate I2C timing information into the SSDT for the OS driver to consume, + * optionally applying override values provided by the caller. */ -void lpss_i2c_acpi_write_speed_config( - const struct lpss_i2c_speed_config *config); +void lpss_i2c_acpi_fill_ssdt(const struct lpss_i2c_speed_config *override); /* * Set I2C bus speed for this controller. diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index f274be8..849679b 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -20,55 +20,36 @@ Device (I2C0) { Name (_ADR, 0x00150000) Name (_DDN, "Serial IO I2C Controller 0") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) } Device (I2C1) { Name (_ADR, 0x00150001) Name (_DDN, "Serial IO I2C Controller 1") - - Name (SSCN, Package () { 528, 640, 30 }) - Name (FMCN, Package () { 128, 160, 30 }) - Name (FPCN, Package () { 48, 64, 30}) } Device (I2C2) { Name (_ADR, 0x00150002) Name (_DDN, "Serial IO I2C Controller 2") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) } Device (I2C3) { Name (_ADR, 0x00150003) Name (_DDN, "Serial IO I2C Controller 3") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) } Device (I2C4) { Name (_ADR, 0x00190002) Name (_DDN, "Serial IO I2C Controller 4") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) } Device (I2C5) { Name (_ADR, 0x00190002) Name (_DDN, "Serial IO I2C Controller 5") - - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) } Device (SPI0) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fe03e59..eec6f1e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -24,6 +24,7 @@ #include <stdint.h> #include <soc/gpio_defs.h> #include <soc/gpe.h> +#include <soc/intel/common/lpss_i2c.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/serialio.h> @@ -44,6 +45,8 @@ struct skylake_i2c_config { enum i2c_speed speed; /* Bus should be enabled prior to ramstage with temporary base */ int early_init; + /* Custom bus speed configuration { scl_lcnt, scl_hcnt, sda_hold } */ + struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; }; struct soc_intel_skylake_config { diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 64d39cd..eebe665 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -13,9 +13,11 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> #include <device/device.h> #include <device/i2c.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <soc/intel/common/lpss_i2c.h> #include <soc/ramstage.h> @@ -54,26 +56,53 @@ static int i2c_dev_to_bus(struct device *dev) static void i2c_dev_init(struct device *dev) { struct soc_intel_skylake_config *config = dev->chip_info; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; + int i, bus = i2c_dev_to_bus(dev); + + if (!config || bus < 0) + return; + + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { + sptr = &config->i2c[bus].speed_config[i]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } +} + +/* Generate ACPI I2C device objects */ +static void i2c_fill_ssdt(struct device *dev) +{ + struct soc_intel_skylake_config *config = dev->chip_info; int bus = i2c_dev_to_bus(dev); if (!config || bus < 0) return; - lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); + acpigen_write_scope(acpi_device_path(dev)); + lpss_i2c_acpi_fill_ssdt(config->i2c[bus].speed_config); + acpigen_pop_len(); } static struct i2c_bus_operations i2c_bus_ops = { - .dev_to_bus = &i2c_dev_to_bus, + .dev_to_bus = &i2c_dev_to_bus, }; static struct device_operations i2c_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_smbus, - .ops_pci = &soc_pci_ops, - .ops_i2c_bus = &i2c_bus_ops, - .init = &i2c_dev_init, + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_smbus, + .ops_pci = &soc_pci_ops, + .ops_i2c_bus = &i2c_bus_ops, + .init = &i2c_dev_init, + .acpi_fill_ssdt_generator = &i2c_fill_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c index 64e6924..3d2e994 100644 --- a/src/soc/intel/skylake/romstage/i2c.c +++ b/src/soc/intel/skylake/romstage/i2c.c @@ -46,6 +46,8 @@ static void i2c_early_init_bus(unsigned bus) { ROMSTAGE_CONST struct soc_intel_skylake_config *config; ROMSTAGE_CONST struct device *tree_dev; + const struct lpss_i2c_speed_config *sptr; + enum i2c_speed speed; pci_devfn_t dev; unsigned devfn; uintptr_t base; @@ -84,7 +86,17 @@ static void i2c_early_init_bus(unsigned bus) write32(reg, value); /* Initialize the controller */ - lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); + speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; + lpss_i2c_init(bus, speed); + + /* Apply custom speed config if it has been set by the board */ + for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) { + sptr = &config->i2c[bus].speed_config[value]; + if (sptr->speed == speed) { + lpss_i2c_set_speed_config(bus, sptr); + break; + } + } } void i2c_early_init(void)

1 0

Patch set updated for coreboot: util/crossgcc: Implement buildgcc script checksum verification
by Philipp Deppenwiese 30 Jun '16

30 Jun '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15170 -gerrit commit d4bed779caeb2a97f6c1070287513ddc9a736d9a Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Mon Jun 13 17:01:07 2016 -0700 util/crossgcc: Implement buildgcc script checksum verification In order to build a secure toolchain https and checksum verification should be used for the sources. The hash alogrithm has changed from SHA1 to SHA384 for security reasons. Add gpg verification for file hash upgrades by developers. Change-Id: Id45097fc7e8435fadce4bda75769592af2730b0c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/crossgcc/buildgcc | 134 ++++++++++++++++----- util/crossgcc/gpg.keyring | Bin 0 -> 222182 bytes util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 2 +- .../sum/acpica-unix2-20160318.tar.gz.cksum | 2 +- util/crossgcc/sum/binutils-2.26.tar.bz2.cksum | 2 +- util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum | 2 +- .../sum/clang-tools-extra-3.8.0.src.tar.xz.cksum | 2 +- .../sum/compiler-rt-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum | 2 +- util/crossgcc/sum/gdb-7.11.tar.xz.cksum | 2 +- util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum | 2 +- util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum | 2 +- util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/make-4.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum | 2 +- util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum | 2 +- util/lint/lint-stable-003-whitespace | 2 +- 18 files changed, 118 insertions(+), 48 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 1e761da..2285b27 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -47,26 +47,28 @@ EXPAT_VERSION=2.1.1 CLANG_VERSION=3.8.0 MAKE_VERSION=4.1 +GPG_KEYRING=$(pwd)/gpg.keyring + # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if # a completely new URL is added here, it probably needs to be added # to the jenkins build as well, or the builder won't download it. -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" -MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" -MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" +GMP_ARCHIVE="https://ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz" +MPFR_ARCHIVE="https://ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz" +MPC_ARCHIVE="https://ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" -GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" -BINUTILS_ARCHIVE="http://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" -GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz" +GCC_ARCHIVE="https://ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" +BINUTILS_ARCHIVE="https://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" +GDB_ARCHIVE="https://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.xz" IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz" -PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}…" -EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.t…" +PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION…" +EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.…" # CLANG toolchain archive locations LLVM_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" CFE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.…" CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" -MAKE_ARCHIVE="http://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" +MAKE_ARCHIVE="https://ftp.gnu.org/gnu/make/make-${MAKE_VERSION}.tar.bz2" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ @@ -202,50 +204,114 @@ check_for_library() { rm -rf "${LIBTEST_FILE}.c" "${LIBTEST_FILE}" } -check_sum() { - test -z "$CHECKSUM" || \ - test "$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" = \ - "$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" +verify_signature() { + if [ -f "sum/${2}.cksum" ] ; then + return + fi + + if [ -z "${CHECKSUM}" ] ; then + printf "\n${RED}Checksum tool not found.${NC}\n" + exit 1 + fi + + if [ -z "${GPG}" ] ; then + printf "\n${RED}GPG tool not found.${NC}\n" + exit 1 + fi + + if [ ! -f "${GPG_KEYRING}" ] ; then + printf "\n${RED}The gpg keyring can't be found not found.${NC}\n" + exit 1 + fi + + if [ ! -f "tarballs/${1}" ] ; then + printf "\n${RED}No signature found for package: ${2} !! PLEASE CHECK MANUALLY WHAT YOU DOWNLOADED.${NC}\n" + return + fi + + if [ ! -f "tarballs/${2}" ] ; then + printf "\n${RED}Source file couldn't be downloaded.${NC}\n" + exit 1 + fi + + ${GPG} --no-default-keyring --keyring ${GPG_KEYRING} --status-fd 1 --verify "tarballs/${1}" "tarballs/${2}" &>/dev/null + if [ "${?}" == "0" ] ; then + return + fi + + printf "\n${RED}Failed to verify signature of package.${NC}\n" + exit 1 } -compute_sum() { +calculate_checksum() { test ! -f sum/$1.cksum && test -f tarballs/$1 && \ (test -z "$CHECKSUM" || $CHECKSUM tarballs/$1 > sum/$1.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" + printf "\n(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.${NC})" +} + +verify_checksum() { + if [ -z "${CHECKSUM}" ] ; then + printf "\n${RED}Checksum tool not found.${NC}\n" + exit 1 + fi + + local static_hash=$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@') + local file_hash=$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@') + + if [ "${static_hash}" != "${file_hash}" ] ; then + printf "\n${RED}Failed to verify checksum of package ${1}.${NC}\n" + exit 1 + fi +} + +validate_url() { + if [[ `wget -S --spider $1 2>&1 | grep 'HTTP/1.1 200 OK'` ]]; then return 1; else return 0; fi } download_showing_percentage() { url=$1 - printf " ..${red} 0%%" - wget --no-check-certificate $url 2>&1 | while read line; do - printf "${red}" - echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' - printf "${NC}" - done + printf " ..${red} 0%%${NC}" + + validate_url ${url} + if [ "${?}" == "1" ] ; then + wget $url 2>&1 | while read line; do + printf "${red}" + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + printf "${NC}" + done + fi } download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" + signature="${archive}.sig" - FILE=$(basename $archive) - printf " * $FILE " + SOURCE_FILE=$(basename ${archive}) + SIGNATURE_FILE=$(basename ${signature}) + printf " * ${SOURCE_FILE} " - if test -f tarballs/$FILE && check_sum $FILE ; then + if test -f tarballs/${SOURCE_FILE} ; then printf "(cached)" else printf "(downloading from $archive)" - rm -f tarballs/$FILE + rm -f tarballs/${SOURCE_FILE} cd tarballs - download_showing_percentage $archive + download_showing_percentage ${archive} + download_showing_percentage ${signature} cd .. - compute_sum $FILE + + verify_signature ${SIGNATURE_FILE} ${SOURCE_FILE} + calculate_checksum ${SOURCE_FILE} fi - if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE.${NC}\n" + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED}Failed to download ${SOURCE_FILE}.${NC}\n" exit 1 fi + + verify_checksum ${SOURCE_FILE} ${archive} + printf "\n" } @@ -253,6 +319,10 @@ unpack_and_patch() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" dir="$(eval echo \$$package"_DIR")" + FILE="$(basename $archive)" + + verify_checksum ${FILE} ${archive} + test -d ${dir} && test -f ${dir}/.unpack_success || ( printf " * $(basename $archive)\n" FLAGS=zxf @@ -723,11 +793,11 @@ esac TAR=$(searchtool tar) || exit $? PATCH=$(searchtool patch) || exit $? MAKE=$(searchtool make) || exit $? -SHA1SUM=$(searchtool sha1sum) -SHA512SUM=$(searchtool sha512sum) -CHECKSUM=$SHA1SUM +SHA384SUM=$(searchtool sha384sum) +CHECKSUM=$SHA384SUM LBZIP2=$(searchtool lbzip2 "" nofail) PIGZ=$(searchtool pigz "" nofail) +GPG=$(searchtool gpg "GnuPG" nofail) searchtool m4 > /dev/null searchtool bison > /dev/null diff --git a/util/crossgcc/gpg.keyring b/util/crossgcc/gpg.keyring new file mode 100644 index 0000000..8cbce7e Binary files /dev/null and b/util/crossgcc/gpg.keyring differ diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum index 58affb0..5093e22 100644 --- a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum +++ b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum @@ -1 +1 @@ -0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz +9aca49d2cde4760035f4fff23e8a446f6451e8effb6e6fab3f259645a631593acb2ce3412aadf810f103f3f6b561abe7 tarballs/Python-3.5.1.tar.xz diff --git a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum index 2f9b331..793a794 100644 --- a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum +++ b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum @@ -1 +1 @@ -786811c1501b9cc90c988293a1c3afefa33b60cc tarballs/acpica-unix2-20160318.tar.gz +73305954ec571a19fd1ced884f5ce951b9a6c183faf111408fefddb1628ccc5aabcc9200d5f0619eb248f3d803e6ae98 tarballs/acpica-unix2-20160318.tar.gz diff --git a/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum index ac0a3c3..4d99d04 100644 --- a/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum +++ b/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum @@ -1 +1 @@ -a637508cffeb2323b14bc8dd65378819768ad4ff tarballs/binutils-2.26.tar.bz2 +ff22e865d7f4ac6fb5d408f92cbc0dcc749a36ee8c5f19a0292fc3d6f08e00f852e04734c47c9a578f092c6963b46878 tarballs/binutils-2.26.tar.bz2 diff --git a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum index 7ba8c8c..b278aac 100644 --- a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -2230ef962f2df3c13ec93f5b04b0e3cdff94b2ce tarballs/cfe-3.8.0.src.tar.xz +3edbe3cafc58ad6fc3d3a133156a656ea7756e8a36176b29bba63434d6f073cef63241cc6df8337fcab3832dd5b5c485 tarballs/cfe-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum index e9d8d72..dd5c566 100644 --- a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -a99d8b6fc5e593c4671424b327779318a1856acf tarballs/clang-tools-extra-3.8.0.src.tar.xz +abd447239f09295f8592225bb7e07ba57cedc3d19a4972b45cd7d70a2db82106d1874a5be03656f8209a0e8a1308fb31 tarballs/clang-tools-extra-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum index 081705d..9239365 100644 --- a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -480ea09e369dac6de1f3759b27fa19417b26b69e tarballs/compiler-rt-3.8.0.src.tar.xz +4560d512f3c3a0dbcc5c29ab7754b07d91ffa1ddc1c06a5215f3d325bc3f138ebf483e2a37abb10fc36cd125e6bf559e tarballs/compiler-rt-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum index 882e501..11800c1 100644 --- a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum +++ b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum @@ -1 +1 @@ -ff91419882ac52151050dad0ee8190645fbeee08 tarballs/expat-2.1.1.tar.bz2 +816e8ca9ac57b6aac76e9979d11714313246492a49c228bb0a16d349174be45cd780d760524eb45acf12ff371e8b96a3 tarballs/expat-2.1.1.tar.bz2 diff --git a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum index bb05e39..2b81f5e 100644 --- a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum +++ b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum @@ -1 +1 @@ -0612270b103941da08376df4d0ef4e5662a2e9eb tarballs/gcc-5.3.0.tar.bz2 +4184972f66dc929686c30936cf8f5085829d8584118ebc3e2ec53a40754afbefc351cfd2c211c09dd3b6eb4ab4759820 tarballs/gcc-5.3.0.tar.bz2 diff --git a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum index ffe5a1c..9cc5d91 100644 --- a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum +++ b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum @@ -1 +1 @@ -466208d771d97d3dfcf965d5c835a669cff8d847 tarballs/gdb-7.11.tar.xz +82f89ef35ea1916d5faa67b7fefa2ac3627894d245c43fb4e20828274566cbbb5d7f83899baad77a3cf7fe9fec6f8c7b tarballs/gdb-7.11.tar.xz diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum index 348b80f..7e00489 100644 --- a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum +++ b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum @@ -1 +1 @@ -99d691607613e749aa5d7c0c2a89aeab38fec070 tarballs/gmp-6.1.0.tar.xz +ec69b394cbcf887ab0717473b04bb70ce30102abf24869eca5acb781de405d3a5670fabb776ba68cfe6e117631522d9f tarballs/gmp-6.1.0.tar.xz diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum index daa27c6..0d3f568 100644 --- a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum +++ b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum @@ -1 +1 @@ -c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz +07fc0b1a40ba3d2b003899df199d1043bb5d44cf7d913e6460c985582e5275b634edb6af6779255d770010fd7d09580e tarballs/libelf-0.8.13.tar.gz diff --git a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum index 2f0af53..547ad8f 100644 --- a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -723ac918979255706434a05f5af34b71c49c9971 tarballs/llvm-3.8.0.src.tar.xz +5d5a012e4d494a4534fcec7643ad28bab7467b96029b6d497e1d523357ae7c9e8bd86400dc90e261d791d6391a369b30 tarballs/llvm-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/make-4.1.tar.bz2.cksum b/util/crossgcc/sum/make-4.1.tar.bz2.cksum index 02807c6..455d779 100644 --- a/util/crossgcc/sum/make-4.1.tar.bz2.cksum +++ b/util/crossgcc/sum/make-4.1.tar.bz2.cksum @@ -1 +1 @@ -0d701882fd6fd61a9652cb8d866ad7fc7de54d58 tarballs/make-4.1.tar.bz2 +8a3adbc49c19db130bfd3c2b7df061d9419b77019d21d23765cf1c961bc6a35d611dbda4241316e98cecc09adccecd90 tarballs/make-4.1.tar.bz2 diff --git a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum index c7ca1ac..70ee62f 100644 --- a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum +++ b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum @@ -1 +1 @@ -b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 tarballs/mpc-1.0.3.tar.gz +dceeb2566d6145fa771641d22de3bef866fa601fe1fa964bc680a275919080bd12bc1abab4f68cecdbaef71d295b7397 tarballs/mpc-1.0.3.tar.gz diff --git a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum index 90f90eb..54cd485 100644 --- a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum +++ b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum @@ -1 +1 @@ -cedc0055d55b6ee4cd17e1e6119ed412520ff81a tarballs/mpfr-3.1.4.tar.xz +30a2807378f578544538810b24bb65d44268015e5d2390d8ae6383fe3939b3bba1e85279789400a226b365010de4bbcd tarballs/mpfr-3.1.4.tar.xz diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 3dbd473..144cda1 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,5 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.keyring$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

New patch to review for coreboot: marvell/mvmap2315: add A2BUS driver
by hakim giydan 30 Jun '16

30 Jun '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15523 -gerrit commit 8d0be84cc232b0eabfff4cd59ab7607b374c901f Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Thu Jun 30 15:28:08 2016 -0700 marvell/mvmap2315: add A2BUS driver Change-Id: If6e61f5aa30217eb601ac460d9306166b8433569 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/a2bus.c | 332 ++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/a2bus.h | 345 +++++++++++++++++++++ src/soc/marvell/mvmap2315/include/soc/addressmap.h | 5 + src/soc/marvell/mvmap2315/power.c | 4 + 5 files changed, 687 insertions(+) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index ca32b76..0e10a94 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -26,6 +26,7 @@ ramstage-y += soc.c ramstage-y += stage_entry.S ramstage-y += uart.c +romstage-y += a2bus.c romstage-y += apmu.c romstage-y += assert.c romstage-y += bootrom.c diff --git a/src/soc/marvell/mvmap2315/a2bus.c b/src/soc/marvell/mvmap2315/a2bus.c new file mode 100644 index 0000000..c2627a0 --- /dev/null +++ b/src/soc/marvell/mvmap2315/a2bus.c @@ -0,0 +1,332 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/a2bus.h> + +const u32 NUM_SIO = 11; +const u32 SIO_UIDS[] = {15, 14, 13, 12, 10, 8, 7, 5, 3, 1, 0}; +const u32 SP_UID = 4; + +static void a2bus_enable_and_check(void) +{ + u32 reg; + u32 checkval; + + printk(BIOS_DEBUG, "Entering a2bus_enable_and_check\n"); + + /* FIXME - remove once default fixed */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0); + reg |= MVMAP2315_CCU_RGF_WIN0_AHR << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win0, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win0, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN0_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN0_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN0_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0) == checkval) + printk(BIOS_DEBUG, " win0 checks\n"); + else + printk(BIOS_DEBUG, " win0 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win0), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win1); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win1, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN1_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN1_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN1_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win1) == checkval) + printk(BIOS_DEBUG, " win1 checks\n"); + else + printk(BIOS_DEBUG, " win1 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win1), checkval); + + /* FIXME - remove once default fixed */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2); + reg |= MVMAP2315_CCU_RGF_WIN2_UID << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win2, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win2, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN2_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN2_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN2_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2) == checkval) + printk(BIOS_DEBUG, " win2 checks\n"); + else + printk(BIOS_DEBUG, " win2 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win2), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win3); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win3, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN3_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN3_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN3_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win3) == checkval) + printk(BIOS_DEBUG, " win3 checks\n"); + else + printk(BIOS_DEBUG, " win3 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win3), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win4); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win4, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN4_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN4_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN4_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win4) == checkval) + printk(BIOS_DEBUG, " win4 checks\n"); + else + printk(BIOS_DEBUG, " win4 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win4), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win5); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win5, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN5_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN5_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN5_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win5) == checkval) + printk(BIOS_DEBUG, " win5 checks\n"); + else + printk(BIOS_DEBUG, " win5 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win5), checkval); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win6); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win6, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN6_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN6_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN6_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win6) == checkval) + printk(BIOS_DEBUG, " win6 checks\n"); + else + printk(BIOS_DEBUG, " win6 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win6), checkval); + + /* FIXME - remove once default fixed */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7); + reg |= MVMAP2315_CCU_RGF_WIN7_UID << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win7, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7); + reg |= MVMAP2315_CCU_RGF_WIN_RGFWINEN; + write32(&mvmap2315_a2bus_ccu->ccu_rgf_win7, reg); + + checkval = ((MVMAP2315_CCU_RGF_WIN7_AHR) << + MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN7_ALR) << + MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT) + | ((MVMAP2315_CCU_RGF_WIN7_UID) << + MVMAP2315_CCU_RGF_WIN_UID_SHIFT) + | MVMAP2315_CCU_RGF_WIN_RGFWINEN; + + if (read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7) == checkval) + printk(BIOS_DEBUG, " win7 checks\n"); + else + printk(BIOS_DEBUG, " win7 no go: 0x%08x != 0x%08x\n", + read32(&mvmap2315_a2bus_ccu->ccu_rgf_win7), checkval); + + printk(BIOS_DEBUG, "Exiting a2bus_enable_and_check\n"); +} + +static void a2bus_open_map(void) +{ + u32 reg; + + printk(BIOS_DEBUG, "Entering a2bus_open_map\n"); + + /* send traffic by defaul to AON (smc0) */ + reg = read32(&mvmap2315_a2bus_ccu->ccu_win_gcr); + reg |= 2 << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win_gcr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN_GCR\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_alr); + reg |= MVMAP2315_CCU_WIN1_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win1_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_ahr); + reg |= MVMAP2315_CCU_WIN1_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win1_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_cr); + reg |= MVMAP2315_CCU_WIN1_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win1_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win1_cr); + reg |= MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win1_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN1\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_alr); + reg |= MVMAP2315_CCU_WIN2_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win2_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_ahr); + reg |= MVMAP2315_CCU_WIN2_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win2_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_cr); + reg |= MVMAP2315_CCU_WIN2_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win2_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win2_cr); + reg &= ~MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win2_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN2\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_alr); + reg |= MVMAP2315_CCU_WIN3_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win3_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_ahr); + reg |= MVMAP2315_CCU_WIN3_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win3_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_cr); + reg |= MVMAP2315_CCU_WIN3_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win3_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win3_cr); + reg |= MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win3_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN3\n"); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_alr); + reg |= MVMAP2315_CCU_WIN4_ALR << MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win4_alr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_ahr); + reg |= MVMAP2315_CCU_WIN4_AHR << MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win4_ahr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_cr); + reg |= MVMAP2315_CCU_WIN4_UID << MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT; + write32(&mvmap2315_a2bus_ccu->ccu_win4_cr, reg); + + reg = read32(&mvmap2315_a2bus_ccu->ccu_win4_cr); + reg |= MVMAP2315_CCU_CR_WINEN; + write32(&mvmap2315_a2bus_ccu->ccu_win4_cr, reg); + + printk(BIOS_DEBUG, "after CCU_WIN4\n"); + + /* open all register space */ + a2bus_enable_and_check(); + + printk(BIOS_DEBUG, "Exiting a2bus_open_map\n"); +} + +void init_a2bus_config(void) +{ + u32 reg; + u32 i; + + /* Open up the A2 address map */ + a2bus_open_map(); + + /* set the bit to enable long non-modifiable */ + for (i = 0; i < NUM_SIO; i++) { + printk(BIOS_DEBUG, "Writing LTC_ForceModifiable to SIO %d\n", + SIO_UIDS[i]); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_idacr); + reg |= SIO_UIDS[i] << MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT; + write32(&mvmap2315_a2bus_banked->ccu_b_idacr, reg); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr); + reg |= MVMAP2315_CCU_B_LTC_CR_USERDMODROB; + write32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr, reg); + } + + printk(BIOS_DEBUG, "Writing LTC_ForceModifiable to SP\n"); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_idacr); + reg |= SP_UID << MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT; + write32(&mvmap2315_a2bus_banked->ccu_b_idacr, reg); + + reg = read32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr); + reg |= MVMAP2315_CCU_B_LTC_CR_USERDMODROB; + write32(&mvmap2315_a2bus_banked->ccu_b_ltc_cr, reg); + + printk(BIOS_DEBUG, "FIXME - DISABLING MVN\n"); + + reg = read32(&mvmap2315_a2bus_alias6->ccu_b_smc_mvn); + reg &= ~MVMAP2315_CCU_B_SMC_MVN_MVNENABLE; + write32(&mvmap2315_a2bus_alias6->ccu_b_smc_mvn, reg); + + reg = read32(&mvmap2315_a2bus_alias9->ccu_b_smc_mvn); + reg &= ~MVMAP2315_CCU_B_SMC_MVN_MVNENABLE; + write32(&mvmap2315_a2bus_alias9->ccu_b_smc_mvn, reg); + + reg = read32(&mvmap2315_a2bus_alias11->ccu_b_smc_mvn); + reg &= ~MVMAP2315_CCU_B_SMC_MVN_MVNENABLE; + write32(&mvmap2315_a2bus_alias11->ccu_b_smc_mvn, reg); +} diff --git a/src/soc/marvell/mvmap2315/include/soc/a2bus.h b/src/soc/marvell/mvmap2315/include/soc/a2bus.h new file mode 100644 index 0000000..5fe4e7a --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/a2bus.h @@ -0,0 +1,345 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __A2BUS_H__ +#define __A2BUS_H__ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT 4 +#define MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT 4 +#define MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT 8 +#define MVMAP2315_CCU_CR_WINEN BIT(0) +#define MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT 19 +#define MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT 6 +#define MVMAP2315_CCU_RGF_WIN_UID_SHIFT 2 +#define MVMAP2315_CCU_RGF_WIN_RGFWINEN BIT(0) +struct mvmap2315_a2bus_ccu_regs { + u32 ccu_win0_cr; + u32 ccu_win0_scr; + u32 ccu_win0_alr; + u32 ccu_win0_ahr; + u32 ccu_win1_cr; + u32 ccu_win1_scr; + u32 ccu_win1_alr; + u32 ccu_win1_ahr; + u32 ccu_win2_cr; + u32 ccu_win2_scr; + u32 ccu_win2_alr; + u32 ccu_win2_ahr; + u32 ccu_win3_cr; + u32 ccu_win3_scr; + u32 ccu_win3_alr; + u32 ccu_win3_ahr; + u32 ccu_win4_cr; + u32 ccu_win4_scr; + u32 ccu_win4_alr; + u32 ccu_win4_ahr; + u32 ccu_win5_cr; + u32 ccu_win5_scr; + u32 ccu_win5_alr; + u32 ccu_win5_ahr; + u32 ccu_win6_cr; + u32 ccu_win6_scr; + u32 ccu_win6_alr; + u32 ccu_win6_ahr; + u32 ccu_win7_cr; + u32 ccu_win7_scr; + u32 ccu_win7_alr; + u32 ccu_win7_ahr; + u8 _reserved0[0x10]; + u32 ccu_rgf_win0; + u32 ccu_rgf_win1; + u32 ccu_rgf_win2; + u32 ccu_rgf_win3; + u32 ccu_rgf_win4; + u32 ccu_rgf_win5; + u32 ccu_rgf_win6; + u32 ccu_rgf_win7; + u32 ccu_rgf_win8; + u32 ccu_rgf_win9; + u32 ccu_rgf_win10; + u32 ccu_rgf_win11; + u32 ccu_rgf_win12; + u32 ccu_rgf_win13; + u32 ccu_rgf_win14; + u32 ccu_rgf_win15; + u32 ccu_win_gcr; + u32 ccu_rgf_sidr0; + u32 ccu_rgf_sidr1; + u8 _reserved1[0x04]; + u32 ccu_rar0; + u32 ccu_rar1; + u8 _reserved2[0x18]; + u32 ccu_sl_hmr; + u32 ccu_sl_mimr0; + u32 ccu_sl_mimr1; + u32 ccu_sl_revid; + u32 ccu_sl_dtpr0; + u32 ccu_sl_dtpr1; + u32 ccu_sl_dtpr2; + u32 ccu_sl_dtpr3; + u32 ccu_sl_dtpr4; + u32 ccu_sl_dtpr5; + u32 ccu_sl_dtpr6; + u32 ccu_sl_dtpr7; + u32 ccu_sl_dtpr8; + u32 ccu_sl_dtpr9; + u32 ccu_sl_dtpr10; + u32 ccu_sl_dtpr11; + u32 ccu_sl_dtpr12; + u32 ccu_sl_dtpr13; + u32 ccu_sl_dtpr14; + u32 ccu_sl_dtpr15; + u8 _reserved3[0xb0]; + u32 ccu_htc_cr; + u32 ccu_htc_sr; + u32 ccu_htc_mnt_cr; + u8 _reserved4[0x04]; + u32 ccu_htc_acr0; + u32 ccu_htc_acr1; + u32 ccu_htc_acr2; + u32 ccu_htc_acr3; + u32 ccu_htc_acr4; + u32 ccu_htc_acr5; + u32 ccu_htc_acr6; + u32 ccu_htc_acr7; + u32 ccu_htc_acr8; + u32 ccu_htc_acr9; + u32 ccu_htc_acr10; + u32 ccu_htc_acr11; + u32 ccu_htc_acr12; + u32 ccu_htc_acr13; + u32 ccu_htc_acr14; + u32 ccu_htc_acr15; + u8 _reserved5[0x10]; + u32 ccu_htc_aasr; + u32 ccu_htc_aset; + u32 ccu_htc_aclr; + u32 ccu_sft_eir0; + u32 ccu_sft_eir1; + u8 _reserved6[0x8c]; + u32 ccu_ltc_cr; + u32 ccu_ltc_sr; + u32 ccu_ltc_hhr; + u32 ccu_ltc_cr1; + u8 _reserved7[0xe0]; + u32 ccu_gspmu_cr; + u32 ccu_gspmu_sr; + u8 _reserved8[0x18]; + u32 ccu_mc_cr; + u8 _reserved9[0x3ec]; + u32 ccu_rgf_cr; + u32 ccu_rgf_scr; +}; + +check_member(mvmap2315_a2bus_ccu_regs, ccu_rgf_scr, 0x804); +static struct mvmap2315_a2bus_ccu_regs * const mvmap2315_a2bus_ccu + = (void *)MVMAP2315_A2BUS_CCU_REGS_BASE; + +#define MVMAP2315_CCU_B_LTC_CR_USERDMODROB BIT(0) +#define MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT 0 +#define MVMAP2315_CCU_B_SMC_MVN_MVNENABLE BIT(0) +struct mvmap2315_a2bus_regs { + u32 ccu_b_uid; + u32 ccu_b_urd; + u32 ccu_b_sfwd; + u8 _reserved0[0x04]; + u32 ccu_b_rapc; + u32 ccu_b_dlapc; + u8 _reserved1[0x08]; + u32 ccu_b_rsc; + u32 ccu_b_rsu; + u8 _reserved2[0x08]; + u32 ccu_b_idacr; + u8 _reserved3[0x0c]; + u32 ccu_b_rsrv0; + u8 _reserved4[0x0c]; + u32 ccu_dbg_ltc_cr; + u32 ccu_dbg_ltc_sr; + u8 _reserved5[0x08]; + u32 ccu_dbg_htc_cr; + u32 ccu_dbg_htc_sr; + u8 _reserved6[0x08]; + u32 ccu_dbg_rsu_cr; + u32 ccu_dbg_rsu_sr; + u8 _reserved7[0x08]; + u32 ccu_dbg_smc_cr; + u32 ccu_dbg_smc_sr; + u8 _reserved8[0x98]; + u32 ccu_b_reicr; + u32 ccu_b_reimr; + u32 ccu_b_seicr; + u32 ccu_b_seimr; + u8 _reserved9[0xd0]; + u32 ccu_b_mpccr; + u32 ccu_b_pcr; + u32 ccu_b_drar; + u32 ccu_b_mpidr; + u32 ccu_b_pdcr; + u32 ccu_b_evar; + u32 ccu_b_l2efr; + u8 _reserved10[0x04]; + u32 ccu_b_psr; + u32 ccu_b_mpsr; + u32 ccu_b_adb_cr; + u32 ccu_b_adb_sr; + u32 ccu_b_pdr_sr; + u32 ccu_b_pdr_cr; + u32 ccu_b_l2dr_sr; + u32 ccu_b_l2dr_cr; + u32 ccu_b_rvbar0; + u32 ccu_b_rvbar1; + u32 ccu_b_rvbar2; + u32 ccu_b_rvbar3; + u32 ccu_b_prcr0; + u32 ccu_b_prcr1; + u32 ccu_b_prcr2; + u32 ccu_b_prcr3; + u32 ccu_b_wrcr0; + u32 ccu_b_wrcr1; + u32 ccu_b_wrcr2; + u32 ccu_b_wrcr3; + u32 ccu_b_drcr0; + u32 ccu_b_drcr1; + u32 ccu_b_drcr2; + u32 ccu_b_drcr3; + u32 ccu_b_crcr; + u32 ccu_b_rcr; + u8 _reserved11[0x78]; + u32 ccu_mc_rcr; + u32 ccu_mc_rsbr; + u32 ccu_mc_rtbr; + u32 ccu_b_smc; + u32 ccu_b_smc_mvn; + u8 _reserved12[0x2c]; + u32 ccu_b_ltc_sr; + u32 ccu_b_ltc_cr; + u32 ccu_b_ltc_qos_ovrd; + u32 qos_time_seg_cr; + u32 qos_bw_guarantee_th; + u32 qos_bw_peak_th; + u32 qos_bw_jam_th; + u32 qos_regulator_out_trans_block_cr0; + u32 qos_prio_cr; + u32 qos_critical_path_cr; + u32 qos_regulator_out_trans_block_cr1; + u32 ccu_b_ltc_tc_ovrd; + u8 _reserved13[0x30]; + u32 ccu_b_htc_sr; + u32 ccu_b_htc_prio_dl; + u32 ccu_b_sp_prio_mesh_lo; + u32 ccu_b_sp_prio_mesh_hi; + u32 ccu_b_sft_far_lo; + u32 ccu_b_sft_far_hi; + u32 ccu_b_htc_mnt_sr; +}; + +check_member(mvmap2315_a2bus_regs, ccu_b_htc_mnt_sr, 0x3b8); +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_banked + = (void *)MVMAP2315_A2BUS_BANKED_REGS_BASE; +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias6 + = (void *)MVMAP2315_A2BUS_ALIAS6_REGS_BASE; +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias9 + = (void *)MVMAP2315_A2BUS_ALIAS9_REGS_BASE; +static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias11 + = (void *)MVMAP2315_A2BUS_ALIAS11_REGS_BASE; + +/* LPDDR "Low Window" */ +#define MVMAP2315_CCU_WIN1_ALR 0x00000000 +#define MVMAP2315_CCU_WIN1_AHR 0x000007FF +#define MVMAP2315_CCU_WIN1_UID 0x0000000B + +/* FLC */ +#define MVMAP2315_CCU_WIN2_ALR 0x00000000 +#define MVMAP2315_CCU_WIN2_AHR 0x000007FF +#define MVMAP2315_CCU_WIN2_UID 0x00000020 + +/* AON and Display Access */ +#define MVMAP2315_CCU_WIN3_ALR 0x00000800 +#define MVMAP2315_CCU_WIN3_AHR 0x00000EFF +#define MVMAP2315_CCU_WIN3_UID 0x00000002 + +/* LPDDR "High Window" */ +#define MVMAP2315_CCU_WIN4_ALR 0x00008000 +#define MVMAP2315_CCU_WIN4_AHR 0x0000BFFF +#define MVMAP2315_CCU_WIN4_UID 0x0000000B + +/* Smc1 - MC + * range: 0xF001_0000 - 0xF01F_FFFF + */ +#define MVMAP2315_CCU_RGF_WIN0_ALR 0x00000010 +#define MVMAP2315_CCU_RGF_WIN0_AHR 0x000001FF +#define MVMAP2315_CCU_RGF_WIN0_UID 0x00000006 + +/* Sio2 - MMU, GIC400 & A72_Config + * range: 0xF020_0000 - 0xF04F_FFFF + */ +#define MVMAP2315_CCU_RGF_WIN1_ALR 0x00000200 +#define MVMAP2315_CCU_RGF_WIN1_AHR 0x000004ff +#define MVMAP2315_CCU_RGF_WIN1_UID 0x00000003 + +/* sio7 - eDisp & ZFBD + * range: 0xF050_0000 - 0xF060_FFFF + */ +#define MVMAP2315_CCU_RGF_WIN2_ALR 0x00000500 +#define MVMAP2315_CCU_RGF_WIN2_AHR 0x0000060F +#define MVMAP2315_CCU_RGF_WIN2_UID 0x0000000C + +/* Sio1 - ZRAM + * range: 0xF068_XXXX + */ +#define MVMAP2315_CCU_RGF_WIN3_ALR 0x00000680 +#define MVMAP2315_CCU_RGF_WIN3_AHR 0x0000068F +#define MVMAP2315_CCU_RGF_WIN3_UID 0x00000001 + +/* Sio1 - GC520 + * range: 0xF070_0000 - 0xF073_FFFF + */ +#define MVMAP2315_CCU_RGF_WIN4_ALR 0x00000700 +#define MVMAP2315_CCU_RGF_WIN4_AHR 0x0000073F +#define MVMAP2315_CCU_RGF_WIN4_UID 0x00000000 + +/* Sio3 - GC7400 + * range: 0xF08X_XXXX + */ +#define MVMAP2315_CCU_RGF_WIN5_ALR 0x00000800 +#define MVMAP2315_CCU_RGF_WIN5_AHR 0x000008FF +#define MVMAP2315_CCU_RGF_WIN5_UID 0x00000005 + +/* sio10 - VPU EnDec & JPEG + * range: 0xF0A0_0000 - 0xF0FF_FFFF + */ +#define MVMAP2315_CCU_RGF_WIN6_ALR 0x00000A00 +#define MVMAP2315_CCU_RGF_WIN6_AHR 0x00000FFF +#define MVMAP2315_CCU_RGF_WIN6_UID 0x0000000F + +/* sio8 - Disp + * range: 0xF010_0000 - 0xF017_FFFF + */ +#define MVMAP2315_CCU_RGF_WIN7_ALR 0x00001000 +#define MVMAP2315_CCU_RGF_WIN7_AHR 0x000017FF +#define MVMAP2315_CCU_RGF_WIN7_UID 0x0000000D + +/* brief Configures the A2 windows to allow access to the + * peripheral registers + */ +void init_a2bus_config(void); + +#endif /* __A2BUS_H__ */ diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index 0de4222..a54403e 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -37,6 +37,11 @@ enum { MVMAP2315_WDT0_BASE = 0XE1010000, MVMAP2315_TIMER0_BASE = 0xE1020000, MVMAP2315_MPMU_CLK_BASE = 0xEF000800, + MVMAP2315_A2BUS_BANKED_REGS_BASE = 0xF0000000, + MVMAP2315_A2BUS_ALIAS6_REGS_BASE = 0xF0002000, + MVMAP2315_A2BUS_ALIAS9_REGS_BASE = 0xF0002C00, + MVMAP2315_A2BUS_ALIAS11_REGS_BASE = 0xF0003400, + MVMAP2315_A2BUS_CCU_REGS_BASE = 0xF0004000, MVMAP2315_AP_GICD_BASE = 0xF0401000, MVMAP2315_AP_GICC_BASE = 0xF0402000, MVMAP2315_FLASH_BASE = 0xFE000000, diff --git a/src/soc/marvell/mvmap2315/power.c b/src/soc/marvell/mvmap2315/power.c index bf7ffda..772715d 100644 --- a/src/soc/marvell/mvmap2315/power.c +++ b/src/soc/marvell/mvmap2315/power.c @@ -15,6 +15,7 @@ #include <arch/io.h> #include <console/console.h> +#include <soc/a2bus.h> #include <soc/apmu.h> #include <soc/assert.h> #include <soc/clock.h> @@ -118,6 +119,9 @@ void full_boot(void) { printk(BIOS_INFO, "Powering up the system.\n"); enable_sys_power(); + + printk(BIOS_INFO, "initializing A2 bus.\n"); + init_a2bus_config(); } u32 get_boot_path(void)

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New patch to review for coreboot: Kconfig: Show DEBUG_BOOT_STATE in the Debug menu
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15522 -gerrit commit 30dfee7dca46dd35f6fb8295f68a05bafa1261a8 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:32 2016 +0200 Kconfig: Show DEBUG_BOOT_STATE in the Debug menu Change-Id: I22441ee0d19aa1b2e2f40278ce30092c86e0adc9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/Kconfig | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7043851..daba05a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1094,6 +1094,13 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_BOOT_STATE + bool "Debug boot state machine" + default n + help + Control debugging of the boot state machine. When selected displays + the state boundaries in ramstage. + endmenu # These probably belong somewhere else, but they are needed somewhere. @@ -1179,13 +1186,6 @@ config CBFS_SIZE equal to the full rom size if that hasn't been overridden by the chipset or mainboard. -config DEBUG_BOOT_STATE - bool - default n - help - Control debugging of the boot state machine. When selected displays - the state boundaries in ramstage. - config CREATE_BOARD_CHECKLIST bool default n

1 0

Patch set updated for coreboot: spike-riscv: Look for the CBFS in RAM
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15285 -gerrit commit 4a6231dc60f9c37b66da567f25ff22f7ad658ff0 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:53 2016 +0200 spike-riscv: Look for the CBFS in RAM Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 3 --- src/arch/riscv/rom_media.c | 26 -------------------- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/qemu-riscv/rom_media.c | 26 ++++++++++++++++++++ src/mainboard/emulation/spike-riscv/Makefile.inc | 3 +++ src/mainboard/emulation/spike-riscv/rom_media.c | 30 ++++++++++++++++++++++++ 6 files changed, 62 insertions(+), 29 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 243fa53..c1c62ef 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -33,7 +33,6 @@ bootblock-y += trap_util.S bootblock-y += trap_handler.c bootblock-y += virtual_memory.c bootblock-y += boot.c -bootblock-y += rom_media.c bootblock-y += misc.c bootblock-y += \ $(top)/src/lib/memchr.c \ @@ -60,7 +59,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c romstage-y += stages.c -romstage-y += rom_media.c romstage-y += misc.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -90,7 +88,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = ramstage-y += trap_handler.c ramstage-y += virtual_memory.c -ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c deleted file mode 100644 index c171307..0000000 --- a/src/arch/riscv/rom_media.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <boot_device.h> - -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ -static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &boot_dev.rdev; -} diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 87bc39a..b8a62f7 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += qemu_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += qemu_util.c romstage-y += uart.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += qemu_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c new file mode 100644 index 0000000..c171307 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* This assumes that the CBFS resides at 0x0, which is true for the default + * configuration. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index dff4758..91c1369 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -15,11 +15,14 @@ bootblock-y += bootblock.c bootblock-y += uart.c bootblock-y += spike_util.c +bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c romstage-y += spike_util.c +romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += spike_util.c +ramstage-y += rom_media.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/rom_media.c b/src/mainboard/emulation/spike-riscv/rom_media.c new file mode 100644 index 0000000..10952a3 --- /dev/null +++ b/src/mainboard/emulation/spike-riscv/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* + * 0x80000000 is this start of RAM. We currently need to load coreboot.rom into + * RAM on SPIKE, because SPIKE doesn't support loading custom code into the + * boot ROM. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +}

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Patch set updated for coreboot: util/riscvtools: Provide a tohost symbol so Spike doesn't hang
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15288 -gerrit commit 310adbca37d8d66f944b23096f609798657ed3e2 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:52 2016 +0200 util/riscvtools: Provide a tohost symbol so Spike doesn't hang See https://github.com/riscv/riscv-isa-sim/issues/54 for more information. Change-Id: I8cda8dc07866d395eb3ce5d94df8232840fa8b82 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/spike-elf.ld | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld index 341a16f..44114f7 100644 --- a/util/riscvtools/spike-elf.ld +++ b/util/riscvtools/spike-elf.ld @@ -8,4 +8,8 @@ SECTIONS .data : { *(.data) } + + tohost = .; + . = . + 8; + fromhost = .; }

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Patch set updated for coreboot: spike-riscv: Remove HTIF related code
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15289 -gerrit commit 847339e6fcbf40295624990bd0c0b391e4ef0297 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:51 2016 +0200 spike-riscv: Remove HTIF related code The HTIF is deprecated and the newest RISC-V binutils don't know the mtohost/mfromhost CSRs anymore. The SBI implementation still needs to be restructured. Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/spike_util.c | 110 ++--------------------- 1 file changed, 7 insertions(+), 103 deletions(-) diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..358cb44 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -55,14 +55,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) uintptr_t mcall_send_ipi(uintptr_t recipient) { - //if (recipient >= num_harts) - //return -1; - - if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { - mb(); - write_csr(send_ipi, recipient); - } - + die("mcall_send_ipi is currently not implemented"); return 0; } @@ -79,50 +72,26 @@ uintptr_t mcall_clear_ipi(void) uintptr_t mcall_shutdown(void) { - while (1) write_csr(mtohost, 1); + die("mcall_shutdown is currently not implemented"); return 0; } uintptr_t mcall_set_timer(unsigned long long when) { - write_csr(mtimecmp, when); - clear_csr(mip, MIP_STIP); - set_csr(mie, MIP_MTIP); + die("mcall_set_timer is currently not implemented"); return 0; } uintptr_t mcall_dev_req(sbi_device_message *m) { - if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; - - while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); - - m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; - HLS()->device_request_queue_head = m; - HLS()->device_request_queue_size++; - + die("mcall_dev_req is currently not implemented"); return 0; } uintptr_t mcall_dev_resp(void) { - htif_interrupt(0, 0); - - sbi_device_message* m = HLS()->device_response_queue_head; - if (m) { - //printm("resp %p\n", m); - sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); - HLS()->device_response_queue_head = next; - if (!next) { - HLS()->device_response_queue_tail = 0; - - // only clear SSIP if no other events are pending - clear_csr(mip, MIP_SSIP); - mb(); - if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); - } - } - return (uintptr_t)m; + die("mcall_dev_resp is currently not implemented"); + return 0; } uintptr_t mcall_hart_id(void) @@ -136,74 +105,9 @@ void hls_init(uint32_t hart_id) HLS()->hart_id = hart_id; } -uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { - uintptr_t fromhost = swap_csr(mfromhost, 0); - if (!fromhost) - return 0; - - uintptr_t dev = FROMHOST_DEV(fromhost); - uintptr_t cmd = FROMHOST_CMD(fromhost); - uintptr_t data = FROMHOST_DATA(fromhost); - - sbi_device_message* m = HLS()->device_request_queue_head; - sbi_device_message* prev = 0x0; - unsigned long i, n; - for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) { - /* - if (!supervisor_paddr_valid(m, sizeof(*m)) - && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M) - panic("htif: page fault"); - */ - - sbi_device_message* next = (void*)m->sbi_private_data; - if (m->dev == dev && m->cmd == cmd) { - m->data = data; - - // dequeue from request queue - if (prev) - prev->sbi_private_data = (uintptr_t)next; - else - HLS()->device_request_queue_head = next; - HLS()->device_request_queue_size = n-1; - m->sbi_private_data = 0; - - // enqueue to response queue - if (HLS()->device_response_queue_tail) - { - HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m; - } - else - { - HLS()->device_response_queue_head = m; - } - HLS()->device_response_queue_tail = m; - - // signal software interrupt - set_csr(mip, MIP_SSIP); - return 0; - } - - prev = m; - m = (void*)atomic_read(&m->sbi_private_data); - } - //HLT(); - return 0; - //panic("htif: no record"); -} - uintptr_t mcall_console_putchar(uint8_t ch) { - while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0); - while (1) { - uintptr_t fromhost = read_csr(mfromhost); - if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) { - if (fromhost) - htif_interrupt(0, 0); - continue; - } - write_csr(mfromhost, 0); - break; - } + do_putchar(ch); return 0; }

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Patch set updated for coreboot: [WIP] arch/riscv: Make SBI support optional
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15510 -gerrit commit 6417d8d426d976730fa03b502dcfa431d837e9d9 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:53 2016 +0200 [WIP] arch/riscv: Make SBI support optional I'm posting this patch early so I can link to it from the wiki. Change-Id: I5cbfc90afd3febab33835935f08005136a3f47e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- payloads/Kconfig | 12 ++++++++++++ src/arch/riscv/boot.c | 4 ++++ src/arch/riscv/virtual_memory.c | 1 + 3 files changed, 17 insertions(+) diff --git a/payloads/Kconfig b/payloads/Kconfig index 8cce778..69d2e41 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -47,6 +47,18 @@ config COMPRESSED_PAYLOAD_LZMA In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. +config PAYLOAD_RISCV_SMODE + bool "Run payload in S-mode and provide SBI" + depends on ARCH_RISCV + default y + help + If Y is selected, coreboot will start the payload in supervisor mode + (S-mode) and provide a an implementation of the System Binary + Interface (SBI). + + Otherwise, the payload will be run in M-mode and will have to provide + its own SBI implementation, if it needs one. + config PAYLOAD_OPTIONS string default "" diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 96526bf..5830ac4 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -22,6 +22,7 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); +#if IS_ENABLED(CONFIG_PAYLOAD_RISCV_SMODE) if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); write_csr(mepc, doit); @@ -29,6 +30,9 @@ void arch_prog_run(struct prog *prog) } else { doit(prog_entry_arg(prog)); } +#else + doit(prog_entry_arg(prog)); +#endif } int arch_supports_bounce_buffer(void) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 64ea2b1..dce0887 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -101,6 +101,7 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable void initVirtualMemory(void) { printk(BIOS_DEBUG, "Initializing virtual memory...\n"); + return; uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs uintptr_t virtualStart = 0xffffffff81000000; uintptr_t pageTableStart = 0x1400000;

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Patch set updated for coreboot: arch/riscv: Change all eret instructions to mret
by Jonathan Neuschäfer 30 Jun '16

30 Jun '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15290 -gerrit commit 452714cdd4ad31158beb1f46365a36b365eae3bd Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:53 2016 +0200 arch/riscv: Change all eret instructions to mret Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/boot.c | 2 +- src/arch/riscv/trap_util.S | 4 ++-- src/arch/riscv/virtual_memory.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 5830ac4..01bb0ac 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -26,7 +26,7 @@ void arch_prog_run(struct prog *prog) if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); write_csr(mepc, doit); - asm volatile("eret"); + asm volatile("mret"); } else { doit(prog_entry_arg(prog)); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 0118ffc..6608328 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -124,9 +124,9 @@ trap_entry: supervisor_call_return: csrr a0, mscratch restore_regs - eret # go back into supervisor call + mret # go back into supervisor call .global machine_call_return machine_call_return: csrr a0, mscratch restore_regs - eret # go back into machine call + mret # go back into machine call diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index dce0887..3edd5cf 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -31,7 +31,7 @@ void walk_page_table(void) { void enter_supervisor(void) { // enter supervisor mode - asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0"); + asm volatile("la t0, 1f; csrw mepc, t0; mret; 1:" ::: "t0"); } void flush_tlb(void)

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coreboot-gerrit June 2016