coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: [NOTFORMERGE] payloads: Set default to GRUB2 and add grub.cfg
by Paul Menzel 09 Mar '16

09 Mar '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14013 -gerrit commit bb5905e7f4cc8d31d6d07692fc9bfe30dcf46514 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Mar 9 20:00:37 2016 +0100 [NOTFORMERGE] payloads: Set default to GRUB2 and add grub.cfg This is just for build testing. Change-Id: I74eb389442412bbe6336f3c637b23fd127a2e98a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- grub.cfg | 1 + payloads/Kconfig | 2 +- payloads/external/GRUB2/Kconfig | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/grub.cfg b/grub.cfg new file mode 100644 index 0000000..9daeafb --- /dev/null +++ b/grub.cfg @@ -0,0 +1 @@ +test diff --git a/payloads/Kconfig b/payloads/Kconfig index c7b9e2a..40559aa 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -3,7 +3,7 @@ menu "Payload" choice prompt "Add a payload" default PAYLOAD_NONE if !ARCH_X86 - default PAYLOAD_SEABIOS if ARCH_X86 + default PAYLOAD_GRUB2 if ARCH_X86 config PAYLOAD_NONE bool "None" diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig index 7a4562c..cf533c5 100644 --- a/payloads/external/GRUB2/Kconfig +++ b/payloads/external/GRUB2/Kconfig @@ -27,7 +27,7 @@ config PAYLOAD_FILE config GRUB2_INCLUDE_RUNTIME_CONFIG_FILE bool "Include GRUB2 runtime config file into ROM image" depends on PAYLOAD_GRUB2 - default n + default y help The GRUB2 payload reads the runtime configuration file from the image stored on the flash ROM chip. Without that, it’ll just drop into a

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New patch to review for coreboot: [NOTFORMERGE] payloads: Set default to GRUB2
by Paul Menzel 09 Mar '16

09 Mar '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14013 -gerrit commit 20b6444b0dad405f1788e464769a91be8b86119e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Mar 9 20:00:37 2016 +0100 [NOTFORMERGE] payloads: Set default to GRUB2 This is just for build testing. Change-Id: I74eb389442412bbe6336f3c637b23fd127a2e98a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/Kconfig b/payloads/Kconfig index c7b9e2a..40559aa 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -3,7 +3,7 @@ menu "Payload" choice prompt "Add a payload" default PAYLOAD_NONE if !ARCH_X86 - default PAYLOAD_SEABIOS if ARCH_X86 + default PAYLOAD_GRUB2 if ARCH_X86 config PAYLOAD_NONE bool "None"

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Patch set updated for coreboot: payloads/GRUB2: Add Kconfig option for grub.cfg
by Paul Menzel 09 Mar '16

09 Mar '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5109 -gerrit commit 6d2a1a3f8d7676abbc3b11ce56c3e520161a4617 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Feb 3 23:09:30 2014 +0100 payloads/GRUB2: Add Kconfig option for grub.cfg Change-Id: I5480d6a5f2a6bbae4222e05bbe92eb717e1aff65 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/GRUB2/Kconfig | 23 +++++++++++++++++++++++ payloads/external/Makefile.inc | 4 ++++ 2 files changed, 27 insertions(+) diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig index 04f0fa9..7a4562c 100644 --- a/payloads/external/GRUB2/Kconfig +++ b/payloads/external/GRUB2/Kconfig @@ -24,4 +24,27 @@ config GRUB2_EXTRA_MODULES config PAYLOAD_FILE default "payloads/external/GRUB2/grub2/build/default_payload.elf" +config GRUB2_INCLUDE_RUNTIME_CONFIG_FILE + bool "Include GRUB2 runtime config file into ROM image" + depends on PAYLOAD_GRUB2 + default n + help + The GRUB2 payload reads the runtime configuration file from the image + stored on the flash ROM chip. Without that, it’ll just drop into a + rescue shell. + . + This configuration may need to be coreboot specific. + . + Select this option, if you want to include the GRUB2 runtime + configuration file into the image as `etc/grub.cfg`. + . + You can add this file manually too. + +config GRUB2_RUNTIME_CONFIG_FILE + string "Path of grub.cfg" + depends on GRUB2_INCLUDE_RUNTIME_CONFIG_FILE + default "grub.cfg" + help + The path of the GRUB2 runtime configuration file to be added to CBFS. + endif diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 557de2a..a26762a 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -34,6 +34,10 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_revision payload_revision-file := $(PAYLOAD_VERSION) payload_revision-type := raw +cbfs-files-$(CONFIG_GRUB2_INCLUDE_RUNTIME_CONFIG_FILE) += etc/grub.cfg +etc/grub.cfg-file := $(CONFIG_GRUB2_RUNTIME_CONFIG_FILE) +etc/grub.cfg-type := raw + SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \

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Patch set updated for coreboot: northbridge/intel: move mrccache.c of sandybridge + haswell to common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14007 -gerrit commit 17ce8c849cd5bb120580389dfe3bd1ed9a4c19fa Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 14:36:46 2016 +0100 northbridge/intel: move mrccache.c of sandybridge + haswell to common The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also renaming mrccache.c -> mrc_cache.c Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/common/Kconfig | 2 + src/northbridge/intel/common/Makefile.inc | 17 ++ src/northbridge/intel/common/mrc_cache.c | 251 +++++++++++++++++++++++ src/northbridge/intel/common/mrc_cache.h | 6 +- src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/haswell/Makefile.inc | 2 - src/northbridge/intel/haswell/haswell.h | 2 - src/northbridge/intel/haswell/mrccache.c | 247 ----------------------- src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/Makefile.inc | 2 - src/northbridge/intel/nehalem/nehalem.h | 2 - src/northbridge/intel/sandybridge/Kconfig | 2 + src/northbridge/intel/sandybridge/Makefile.inc | 2 - src/northbridge/intel/sandybridge/mrccache.c | 253 ------------------------ src/northbridge/intel/sandybridge/sandybridge.h | 2 - 15 files changed, 278 insertions(+), 514 deletions(-) diff --git a/src/northbridge/intel/common/Kconfig b/src/northbridge/intel/common/Kconfig new file mode 100644 index 0000000..80593d6 --- /dev/null +++ b/src/northbridge/intel/common/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + def_bool n diff --git a/src/northbridge/intel/common/Makefile.inc b/src/northbridge/intel/common/Makefile.inc new file mode 100644 index 0000000..73427cb --- /dev/null +++ b/src/northbridge/intel/common/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c +ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c new file mode 100644 index 0000000..72098ce --- /dev/null +++ b/src/northbridge/intel/common/mrc_cache.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <bootstate.h> +#include <console/console.h> +#include <cbfs.h> +#include <fmap.h> +#include <ip_checksum.h> +#include <device/device.h> +#include <cbmem.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include "mrc_cache.h" + +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); +} + +static struct mrc_data_container *next_mrc_block( + struct mrc_data_container *mrc_cache) +{ + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + u8 *region_ptr = (u8*)mrc_cache; + region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; +} + +static int is_mrc_cache(struct mrc_data_container *mrc_cache) +{ + return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); +} + +/* Right now, the offsets for the MRC cache area are hard-coded in the + * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make + * this more flexible, there are two of options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - Use CBFS + */ +static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) +{ + size_t region_size = 0; + *mrc_region_ptr = NULL; + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { + region_size = region_device_sz(&rdev); + *mrc_region_ptr = rdev_mmap_full(&rdev); + } + } else { + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", + CBFS_TYPE_MRC_CACHE, + &region_size); + } + return region_size; +} + +/* + * Find the largest index block in the MRC cache. Return NULL if non is + * found. + */ +static struct mrc_data_container *find_current_mrc_cache_local + (struct mrc_data_container *mrc_cache, u32 region_size) +{ + u32 region_end; + u32 entry_id = 0; + struct mrc_data_container *mrc_next = mrc_cache; + + region_end = (u32) mrc_cache + region_size; + + /* Search for the last filled entry in the region */ + while (is_mrc_cache(mrc_next)) { + entry_id++; + mrc_cache = mrc_next; + mrc_next = next_mrc_block(mrc_next); + if ((u32)mrc_next >= region_end) { + /* Stay in the MRC data region */ + break; + } + } + + if (entry_id == 0) { + printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); + return NULL; + } + + /* Verify checksum */ + if (mrc_cache->mrc_checksum != + compute_ip_checksum(mrc_cache->mrc_data, + mrc_cache->mrc_data_size)) { + printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + return NULL; + } + + printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, + entry_id - 1); + + return mrc_cache; +} + +/* SPI code needs malloc/free. + * Also unknown if writing flash from XIP-flash code is a good idea + */ + +/* find the first empty block in the MRC cache area. + * If there's none, return NULL. + * + * @mrc_cache_base - base address of the MRC cache area + * @mrc_cache - current entry (for which we need to find next) + * @region_size - total size of the MRC cache area + */ +static struct mrc_data_container *find_next_mrc_cache + (struct mrc_data_container *mrc_cache_base, + struct mrc_data_container *mrc_cache, + u32 region_size) +{ + u32 region_end = (u32) mrc_cache_base + region_size; + + mrc_cache = next_mrc_block(mrc_cache); + if ((u32)mrc_cache >= region_end) { + /* Crossed the boundary */ + mrc_cache = NULL; + printk(BIOS_DEBUG, "%s: no available entries found\n", + __func__); + } else { + printk(BIOS_DEBUG, + "%s: picked next entry from cache block at %p\n", + __func__, mrc_cache); + } + + return mrc_cache; +} + +static void update_mrc_cache(void *unused) +{ + printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); + struct mrc_data_container *cache, *cache_base; + u32 cache_size; + int ret; + + if (!current) { + printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); + return; + } + if (current->mrc_data_size == -1) { + printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); + return; + } + + cache_size = get_mrc_cache_region(&cache_base); + if (cache_base == NULL) { + printk(BIOS_ERR, "%s: could not find MRC cache area\n", + __func__); + return; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + cache = find_current_mrc_cache_local(cache_base, cache_size); + + if (cache && (cache->mrc_data_size == current->mrc_data_size) && + (memcmp(cache, current, cache->mrc_data_size) == 0)) { + printk(BIOS_DEBUG, + "MRC data in flash is up to date. No update.\n"); + return; + } + + // 1. use spi_flash_probe() to find the flash, then + spi_init(); + struct spi_flash *flash = spi_flash_probe(0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } + + // 2. look up the first unused block + if (cache) + cache = find_next_mrc_cache(cache_base, cache, cache_size); + + /* + * 3. if no such place exists, erase entire mrc-cache range & use + * block 0. First time around the erase is not needed, but this is a + * small overhead for simpler code. + */ + if (!cache) { + printk(BIOS_DEBUG, + "Need to erase the MRC cache region of %d bytes at %p\n", + cache_size, cache_base); + + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); + + /* we will start at the beginning again */ + cache = cache_base; + } + // 4. write mrc data with flash->write() + printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", + cache); + ret = flash->write(flash, to_flash_offset(flash, cache), + current->mrc_data_size + sizeof(*current), current); + if (ret) + printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", + ret); + else + printk(BIOS_DEBUG, "Successful written MRC cache\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); + +struct mrc_data_container *find_current_mrc_cache(void) +{ + struct mrc_data_container *cache_base; + u32 cache_size; + + cache_size = get_mrc_cache_region(&cache_base); + if (cache_base == NULL) { + printk(BIOS_ERR, "%s: could not find MRC cache area\n", + __func__); + return NULL; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + return find_current_mrc_cache_local(cache_base, cache_size); +} diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index b6ccdb9..20c8a0f 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -1,5 +1,5 @@ -#ifndef MRCDATA_H -#define MRCDATA_H +#ifndef __NORTHBRIDGE_COMMON_MRCDATA_H +#define __NORTHBRIDGE_COMMON_MRCDATA_H #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -12,4 +12,6 @@ struct mrc_data_container { u8 mrc_data[0]; // Variable size, platform/run time dependent. } __attribute__ ((packed)); +struct mrc_data_container *find_current_mrc_cache(void); + #endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 69550ff..5e59233 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CPU_INTEL_HASWELL select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 1dd7f76..f198b7c 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -20,12 +20,10 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += mrccache.c ramstage-y += minihd.c romstage-y += ram_calc.c romstage-y += raminit.c -romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index c560428..6e587f8 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,8 +213,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c deleted file mode 100644 index 09bf73f..0000000 --- a/src/northbridge/intel/haswell/mrccache.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <northbridge/intel/common/mrc_cache.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "haswell.h" -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - *mrc_region_ptr = NULL; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3658bd8..b05bf44 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 5d49f5c..17bbaff 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -21,12 +21,10 @@ ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += ../sandybridge/mrccache.c romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c -romstage-y += ../sandybridge/mrccache.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index a2536cc..381bfbd 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,8 +593,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 9b90f36..64f4a14 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -26,6 +27,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 4a7a854..b1bc2ac 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c -ramstage-y += mrccache.c romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -36,7 +35,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += mrccache.c romstage-y += iommu.c romstage-y += early_init.c romstage-y += report_platform.c diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c deleted file mode 100644 index 79f1981..0000000 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "sandybridge.h" -#include <northbridge/intel/common/mrc_cache.h> -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } else - *mrc_region_ptr = NULL; - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - int ret; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - ret = flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); - if (ret) - printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", - ret); - else - printk(BIOS_DEBUG, "Successful written MRC cache\n"); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 116e0a8..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,8 +235,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion);

1 0

Patch set updated for coreboot: northbridge/intel: move mrc_cache definition into a common header
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13998 -gerrit commit d75e4276cfec4e7be42d73bad27d00da8f2a9293 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 northbridge/intel: move mrc_cache definition into a common header The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/common/mrc_cache.h | 15 +++++++++++++++ src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ---- src/northbridge/intel/haswell/haswell.h | 13 +------------ src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/haswell/raminit.c | 1 + src/northbridge/intel/nehalem/nehalem.h | 13 +------------ src/northbridge/intel/nehalem/raminit.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/sandybridge.h | 13 +------------ 11 files changed, 24 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h new file mode 100644 index 0000000..b6ccdb9 --- /dev/null +++ b/src/northbridge/intel/common/mrc_cache.h @@ -0,0 +1,15 @@ +#ifndef MRCDATA_H +#define MRCDATA_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +#endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index ab428c3..a41b2ca 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 8a01edc..c560428 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 7139930..09bf73f 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -20,6 +20,7 @@ #include <cbfs.h> #include <fmap.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_cache.h> #include <device/device.h> #include <cbmem.h> #include "pei_data.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 92a4532..4644f05 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,6 +22,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_cache.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index d15c7ef..a2536cc 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4bc95ba..a5a6276 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,6 +40,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <northbridge/intel/common/mrc_cache.h> #endif #if !REAL diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index b5b87ab..79f1981 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" +#include <northbridge/intel/common/mrc_cache.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1527ec3..0b27fe5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -26,6 +26,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/common/mrc_cache.h> #include <device/pci_def.h> #include <memory_info.h> #include <smbios.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 162caf6..c26f012 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -24,6 +24,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mrc_cache.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ba8f8d9..116e0a8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,18 +235,7 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h"

1 0

Patch set updated for coreboot: northbridge/intel: move mrccache.c of sandybridge + haswell to common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14007 -gerrit commit 698b8a15bc751b0d1110aea32bf63a61a95b6ca0 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 14:36:46 2016 +0100 northbridge/intel: move mrccache.c of sandybridge + haswell to common The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also renaming mrccache.c -> mrc_cache.c Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/common/Kconfig | 2 + src/northbridge/intel/common/Makefile.inc | 17 ++ src/northbridge/intel/common/mrc_cache.c | 251 +++++++++++++++++++++++ src/northbridge/intel/common/mrc_cache.h | 6 +- src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/haswell/Makefile.inc | 2 - src/northbridge/intel/haswell/haswell.h | 2 - src/northbridge/intel/haswell/mrccache.c | 247 ----------------------- src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/Makefile.inc | 2 - src/northbridge/intel/sandybridge/Kconfig | 2 + src/northbridge/intel/sandybridge/Makefile.inc | 2 - src/northbridge/intel/sandybridge/mrccache.c | 253 ------------------------ src/northbridge/intel/sandybridge/sandybridge.h | 2 - 14 files changed, 278 insertions(+), 512 deletions(-) diff --git a/src/northbridge/intel/common/Kconfig b/src/northbridge/intel/common/Kconfig new file mode 100644 index 0000000..80593d6 --- /dev/null +++ b/src/northbridge/intel/common/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + def_bool n diff --git a/src/northbridge/intel/common/Makefile.inc b/src/northbridge/intel/common/Makefile.inc new file mode 100644 index 0000000..73427cb --- /dev/null +++ b/src/northbridge/intel/common/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c +ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c new file mode 100644 index 0000000..72098ce --- /dev/null +++ b/src/northbridge/intel/common/mrc_cache.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <bootstate.h> +#include <console/console.h> +#include <cbfs.h> +#include <fmap.h> +#include <ip_checksum.h> +#include <device/device.h> +#include <cbmem.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include "mrc_cache.h" + +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); +} + +static struct mrc_data_container *next_mrc_block( + struct mrc_data_container *mrc_cache) +{ + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + u8 *region_ptr = (u8*)mrc_cache; + region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; +} + +static int is_mrc_cache(struct mrc_data_container *mrc_cache) +{ + return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); +} + +/* Right now, the offsets for the MRC cache area are hard-coded in the + * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make + * this more flexible, there are two of options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - Use CBFS + */ +static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) +{ + size_t region_size = 0; + *mrc_region_ptr = NULL; + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { + region_size = region_device_sz(&rdev); + *mrc_region_ptr = rdev_mmap_full(&rdev); + } + } else { + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", + CBFS_TYPE_MRC_CACHE, + &region_size); + } + return region_size; +} + +/* + * Find the largest index block in the MRC cache. Return NULL if non is + * found. + */ +static struct mrc_data_container *find_current_mrc_cache_local + (struct mrc_data_container *mrc_cache, u32 region_size) +{ + u32 region_end; + u32 entry_id = 0; + struct mrc_data_container *mrc_next = mrc_cache; + + region_end = (u32) mrc_cache + region_size; + + /* Search for the last filled entry in the region */ + while (is_mrc_cache(mrc_next)) { + entry_id++; + mrc_cache = mrc_next; + mrc_next = next_mrc_block(mrc_next); + if ((u32)mrc_next >= region_end) { + /* Stay in the MRC data region */ + break; + } + } + + if (entry_id == 0) { + printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); + return NULL; + } + + /* Verify checksum */ + if (mrc_cache->mrc_checksum != + compute_ip_checksum(mrc_cache->mrc_data, + mrc_cache->mrc_data_size)) { + printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + return NULL; + } + + printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, + entry_id - 1); + + return mrc_cache; +} + +/* SPI code needs malloc/free. + * Also unknown if writing flash from XIP-flash code is a good idea + */ + +/* find the first empty block in the MRC cache area. + * If there's none, return NULL. + * + * @mrc_cache_base - base address of the MRC cache area + * @mrc_cache - current entry (for which we need to find next) + * @region_size - total size of the MRC cache area + */ +static struct mrc_data_container *find_next_mrc_cache + (struct mrc_data_container *mrc_cache_base, + struct mrc_data_container *mrc_cache, + u32 region_size) +{ + u32 region_end = (u32) mrc_cache_base + region_size; + + mrc_cache = next_mrc_block(mrc_cache); + if ((u32)mrc_cache >= region_end) { + /* Crossed the boundary */ + mrc_cache = NULL; + printk(BIOS_DEBUG, "%s: no available entries found\n", + __func__); + } else { + printk(BIOS_DEBUG, + "%s: picked next entry from cache block at %p\n", + __func__, mrc_cache); + } + + return mrc_cache; +} + +static void update_mrc_cache(void *unused) +{ + printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); + struct mrc_data_container *cache, *cache_base; + u32 cache_size; + int ret; + + if (!current) { + printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); + return; + } + if (current->mrc_data_size == -1) { + printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); + return; + } + + cache_size = get_mrc_cache_region(&cache_base); + if (cache_base == NULL) { + printk(BIOS_ERR, "%s: could not find MRC cache area\n", + __func__); + return; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + cache = find_current_mrc_cache_local(cache_base, cache_size); + + if (cache && (cache->mrc_data_size == current->mrc_data_size) && + (memcmp(cache, current, cache->mrc_data_size) == 0)) { + printk(BIOS_DEBUG, + "MRC data in flash is up to date. No update.\n"); + return; + } + + // 1. use spi_flash_probe() to find the flash, then + spi_init(); + struct spi_flash *flash = spi_flash_probe(0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } + + // 2. look up the first unused block + if (cache) + cache = find_next_mrc_cache(cache_base, cache, cache_size); + + /* + * 3. if no such place exists, erase entire mrc-cache range & use + * block 0. First time around the erase is not needed, but this is a + * small overhead for simpler code. + */ + if (!cache) { + printk(BIOS_DEBUG, + "Need to erase the MRC cache region of %d bytes at %p\n", + cache_size, cache_base); + + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); + + /* we will start at the beginning again */ + cache = cache_base; + } + // 4. write mrc data with flash->write() + printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", + cache); + ret = flash->write(flash, to_flash_offset(flash, cache), + current->mrc_data_size + sizeof(*current), current); + if (ret) + printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", + ret); + else + printk(BIOS_DEBUG, "Successful written MRC cache\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); + +struct mrc_data_container *find_current_mrc_cache(void) +{ + struct mrc_data_container *cache_base; + u32 cache_size; + + cache_size = get_mrc_cache_region(&cache_base); + if (cache_base == NULL) { + printk(BIOS_ERR, "%s: could not find MRC cache area\n", + __func__); + return NULL; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + return find_current_mrc_cache_local(cache_base, cache_size); +} diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index b6ccdb9..20c8a0f 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -1,5 +1,5 @@ -#ifndef MRCDATA_H -#define MRCDATA_H +#ifndef __NORTHBRIDGE_COMMON_MRCDATA_H +#define __NORTHBRIDGE_COMMON_MRCDATA_H #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -12,4 +12,6 @@ struct mrc_data_container { u8 mrc_data[0]; // Variable size, platform/run time dependent. } __attribute__ ((packed)); +struct mrc_data_container *find_current_mrc_cache(void); + #endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 69550ff..5e59233 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CPU_INTEL_HASWELL select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 1dd7f76..f198b7c 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -20,12 +20,10 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += mrccache.c ramstage-y += minihd.c romstage-y += ram_calc.c romstage-y += raminit.c -romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index c560428..6e587f8 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,8 +213,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c deleted file mode 100644 index 09bf73f..0000000 --- a/src/northbridge/intel/haswell/mrccache.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <northbridge/intel/common/mrc_cache.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "haswell.h" -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - *mrc_region_ptr = NULL; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3658bd8..b05bf44 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 5d49f5c..17bbaff 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -21,12 +21,10 @@ ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += ../sandybridge/mrccache.c romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c -romstage-y += ../sandybridge/mrccache.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 9b90f36..64f4a14 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -26,6 +27,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 4a7a854..b1bc2ac 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c -ramstage-y += mrccache.c romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -36,7 +35,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += mrccache.c romstage-y += iommu.c romstage-y += early_init.c romstage-y += report_platform.c diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c deleted file mode 100644 index 79f1981..0000000 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "sandybridge.h" -#include <northbridge/intel/common/mrc_cache.h> -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } else - *mrc_region_ptr = NULL; - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - int ret; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - ret = flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); - if (ret) - printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", - ret); - else - printk(BIOS_DEBUG, "Successful written MRC cache\n"); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 116e0a8..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,8 +235,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion);

1 0

Patch set updated for coreboot: northbridge/intel: move mrc_data definition into a common header
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13998 -gerrit commit 45147893f58b84972750831f72ac34a563f26d26 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 northbridge/intel: move mrc_data definition into a common header The mrc_data definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/common/mrc_cache.h | 15 +++++++++++++++ src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ---- src/northbridge/intel/haswell/haswell.h | 13 +------------ src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/haswell/raminit.c | 1 + src/northbridge/intel/nehalem/nehalem.h | 13 +------------ src/northbridge/intel/nehalem/raminit.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/sandybridge/raminit_mrc.c | 1 + src/northbridge/intel/sandybridge/sandybridge.h | 13 +------------ 11 files changed, 24 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h new file mode 100644 index 0000000..b6ccdb9 --- /dev/null +++ b/src/northbridge/intel/common/mrc_cache.h @@ -0,0 +1,15 @@ +#ifndef MRCDATA_H +#define MRCDATA_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +#endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index ab428c3..a41b2ca 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 8a01edc..c560428 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 7139930..09bf73f 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -20,6 +20,7 @@ #include <cbfs.h> #include <fmap.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_cache.h> #include <device/device.h> #include <cbmem.h> #include "pei_data.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 92a4532..4644f05 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,6 +22,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <northbridge/intel/common/mrc_cache.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit.h" diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index d15c7ef..a2536cc 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4bc95ba..a5a6276 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,6 +40,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <northbridge/intel/common/mrc_cache.h> #endif #if !REAL diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index b5b87ab..79f1981 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" +#include <northbridge/intel/common/mrc_cache.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1527ec3..0b27fe5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -26,6 +26,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <pc80/mc146818rtc.h> +#include <northbridge/intel/common/mrc_cache.h> #include <device/pci_def.h> #include <memory_info.h> #include <smbios.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 162caf6..c26f012 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -24,6 +24,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mrc_cache.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ba8f8d9..116e0a8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,18 +235,7 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - +struct mrc_data_container; struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h"

1 0

Patch set updated for coreboot: northbridge/intel: move mrccache.c of sandybridge + haswell to common
by Alexander Couzens 09 Mar '16

09 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14007 -gerrit commit cfecae28596e9c158521347456a7f2fbb8715822 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 14:36:46 2016 +0100 northbridge/intel: move mrccache.c of sandybridge + haswell to common The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also renaming mrccache.c -> mrc_cache.c Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/common/Kconfig | 2 + src/northbridge/intel/common/Makefile.inc | 17 ++ src/northbridge/intel/common/mrc_cache.c | 251 +++++++++++++++++++++++ src/northbridge/intel/common/mrc_cache.h | 6 +- src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/haswell/Makefile.inc | 2 - src/northbridge/intel/haswell/haswell.h | 2 - src/northbridge/intel/haswell/mrccache.c | 247 ----------------------- src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/Makefile.inc | 2 - src/northbridge/intel/sandybridge/Kconfig | 2 + src/northbridge/intel/sandybridge/Makefile.inc | 2 - src/northbridge/intel/sandybridge/mrccache.c | 253 ------------------------ src/northbridge/intel/sandybridge/sandybridge.h | 2 - 14 files changed, 278 insertions(+), 512 deletions(-) diff --git a/src/northbridge/intel/common/Kconfig b/src/northbridge/intel/common/Kconfig new file mode 100644 index 0000000..80593d6 --- /dev/null +++ b/src/northbridge/intel/common/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + def_bool n diff --git a/src/northbridge/intel/common/Makefile.inc b/src/northbridge/intel/common/Makefile.inc new file mode 100644 index 0000000..73427cb --- /dev/null +++ b/src/northbridge/intel/common/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c +ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c new file mode 100644 index 0000000..72098ce --- /dev/null +++ b/src/northbridge/intel/common/mrc_cache.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <bootstate.h> +#include <console/console.h> +#include <cbfs.h> +#include <fmap.h> +#include <ip_checksum.h> +#include <device/device.h> +#include <cbmem.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include "mrc_cache.h" + +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); +} + +static struct mrc_data_container *next_mrc_block( + struct mrc_data_container *mrc_cache) +{ + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + u8 *region_ptr = (u8*)mrc_cache; + region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; +} + +static int is_mrc_cache(struct mrc_data_container *mrc_cache) +{ + return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); +} + +/* Right now, the offsets for the MRC cache area are hard-coded in the + * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make + * this more flexible, there are two of options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - Use CBFS + */ +static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) +{ + size_t region_size = 0; + *mrc_region_ptr = NULL; + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { + region_size = region_device_sz(&rdev); + *mrc_region_ptr = rdev_mmap_full(&rdev); + } + } else { + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", + CBFS_TYPE_MRC_CACHE, + &region_size); + } + return region_size; +} + +/* + * Find the largest index block in the MRC cache. Return NULL if non is + * found. + */ +static struct mrc_data_container *find_current_mrc_cache_local + (struct mrc_data_container *mrc_cache, u32 region_size) +{ + u32 region_end; + u32 entry_id = 0; + struct mrc_data_container *mrc_next = mrc_cache; + + region_end = (u32) mrc_cache + region_size; + + /* Search for the last filled entry in the region */ + while (is_mrc_cache(mrc_next)) { + entry_id++; + mrc_cache = mrc_next; + mrc_next = next_mrc_block(mrc_next); + if ((u32)mrc_next >= region_end) { + /* Stay in the MRC data region */ + break; + } + } + + if (entry_id == 0) { + printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); + return NULL; + } + + /* Verify checksum */ + if (mrc_cache->mrc_checksum != + compute_ip_checksum(mrc_cache->mrc_data, + mrc_cache->mrc_data_size)) { + printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + return NULL; + } + + printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, + entry_id - 1); + + return mrc_cache; +} + +/* SPI code needs malloc/free. + * Also unknown if writing flash from XIP-flash code is a good idea + */ + +/* find the first empty block in the MRC cache area. + * If there's none, return NULL. + * + * @mrc_cache_base - base address of the MRC cache area + * @mrc_cache - current entry (for which we need to find next) + * @region_size - total size of the MRC cache area + */ +static struct mrc_data_container *find_next_mrc_cache + (struct mrc_data_container *mrc_cache_base, + struct mrc_data_container *mrc_cache, + u32 region_size) +{ + u32 region_end = (u32) mrc_cache_base + region_size; + + mrc_cache = next_mrc_block(mrc_cache); + if ((u32)mrc_cache >= region_end) { + /* Crossed the boundary */ + mrc_cache = NULL; + printk(BIOS_DEBUG, "%s: no available entries found\n", + __func__); + } else { + printk(BIOS_DEBUG, + "%s: picked next entry from cache block at %p\n", + __func__, mrc_cache); + } + + return mrc_cache; +} + +static void update_mrc_cache(void *unused) +{ + printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); + struct mrc_data_container *cache, *cache_base; + u32 cache_size; + int ret; + + if (!current) { + printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); + return; + } + if (current->mrc_data_size == -1) { + printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); + return; + } + + cache_size = get_mrc_cache_region(&cache_base); + if (cache_base == NULL) { + printk(BIOS_ERR, "%s: could not find MRC cache area\n", + __func__); + return; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + cache = find_current_mrc_cache_local(cache_base, cache_size); + + if (cache && (cache->mrc_data_size == current->mrc_data_size) && + (memcmp(cache, current, cache->mrc_data_size) == 0)) { + printk(BIOS_DEBUG, + "MRC data in flash is up to date. No update.\n"); + return; + } + + // 1. use spi_flash_probe() to find the flash, then + spi_init(); + struct spi_flash *flash = spi_flash_probe(0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } + + // 2. look up the first unused block + if (cache) + cache = find_next_mrc_cache(cache_base, cache, cache_size); + + /* + * 3. if no such place exists, erase entire mrc-cache range & use + * block 0. First time around the erase is not needed, but this is a + * small overhead for simpler code. + */ + if (!cache) { + printk(BIOS_DEBUG, + "Need to erase the MRC cache region of %d bytes at %p\n", + cache_size, cache_base); + + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); + + /* we will start at the beginning again */ + cache = cache_base; + } + // 4. write mrc data with flash->write() + printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", + cache); + ret = flash->write(flash, to_flash_offset(flash, cache), + current->mrc_data_size + sizeof(*current), current); + if (ret) + printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", + ret); + else + printk(BIOS_DEBUG, "Successful written MRC cache\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); + +struct mrc_data_container *find_current_mrc_cache(void) +{ + struct mrc_data_container *cache_base; + u32 cache_size; + + cache_size = get_mrc_cache_region(&cache_base); + if (cache_base == NULL) { + printk(BIOS_ERR, "%s: could not find MRC cache area\n", + __func__); + return NULL; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + return find_current_mrc_cache_local(cache_base, cache_size); +} diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index b6ccdb9..20c8a0f 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -1,5 +1,5 @@ -#ifndef MRCDATA_H -#define MRCDATA_H +#ifndef __NORTHBRIDGE_COMMON_MRCDATA_H +#define __NORTHBRIDGE_COMMON_MRCDATA_H #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -12,4 +12,6 @@ struct mrc_data_container { u8 mrc_data[0]; // Variable size, platform/run time dependent. } __attribute__ ((packed)); +struct mrc_data_container *find_current_mrc_cache(void); + #endif /* MRCDATA_H */ diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 69550ff..5e59233 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CPU_INTEL_HASWELL select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 1dd7f76..f198b7c 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -20,12 +20,10 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += mrccache.c ramstage-y += minihd.c romstage-y += ram_calc.c romstage-y += raminit.c -romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index c560428..6e587f8 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -213,8 +213,6 @@ void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c deleted file mode 100644 index 09bf73f..0000000 --- a/src/northbridge/intel/haswell/mrccache.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <northbridge/intel/common/mrc_cache.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "haswell.h" -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - *mrc_region_ptr = NULL; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3658bd8..b05bf44 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 5d49f5c..17bbaff 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -21,12 +21,10 @@ ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += ../sandybridge/mrccache.c romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c -romstage-y += ../sandybridge/mrccache.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 9b90f36..64f4a14 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -26,6 +27,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 4a7a854..b1bc2ac 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c -ramstage-y += mrccache.c romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -36,7 +35,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += mrccache.c romstage-y += iommu.c romstage-y += early_init.c romstage-y += report_platform.c diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c deleted file mode 100644 index 79f1981..0000000 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <ip_checksum.h> -#include <device/device.h> -#include <cbmem.h> -#include "pei_data.h" -#include "sandybridge.h" -#include <northbridge/intel/common/mrc_cache.h> -#include <spi-generic.h> -#include <spi_flash.h> - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } else - *mrc_region_ptr = NULL; - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - int ret; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - struct spi_flash *flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - ret = flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); - if (ret) - printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", - ret); - else - printk(BIOS_DEBUG, "Successful written MRC cache\n"); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 116e0a8..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -235,8 +235,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif -struct mrc_data_container; -struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion);

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
by Timothy Pearson 09 Mar '16

09 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13934 -gerrit commit 59d0441998a08ae9835e3dfc7efb5edca104b7d9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 7 14:30:47 2016 -0600 nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks A couple of arrays were not properly initialized. This did not appear to affect operation of the codebase however it led to some ugly values being displayed when debugging was turned on. Also bounds check an array index; as before this did not appear to affect operation but was a potential point of failure. Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 8597bda..c65e48c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1714,6 +1714,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 */ Receiver = mct_InitReceiver_D(pDCTstat, dct); + /* Indicate success unless training the DCT explicitly fails */ dct_training_success = 1; /* There are four receiver pairs, loosely associated with chipselects. @@ -1726,8 +1727,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, continue; } - for (lane = 0; lane < MAX_BYTE_LANES; lane++) - lane_training_success[lane] = 0; + /* Initialize variables */ + memset(lane_training_success, 0, sizeof(lane_training_success)); + memset(current_phy_phase_delay, 0, sizeof(current_phy_phase_delay)); /* 2.10.5.8.3 (2) */ read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg); @@ -1794,14 +1796,17 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, #endif /* 2.10.5.8.3 (5) */ - prev = 0; - for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) { + prev = dqs_results_array[rx_en_offset]; + for (current_phy_phase_delay[lane] = rx_en_offset + ren_step; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) { if ((dqs_results_array[current_phy_phase_delay[lane]] == 0) && (prev == 1)) { /* Restore last known good delay */ current_phy_phase_delay[lane] -= ren_step; /* 2.10.5.8.3 (5 A B) */ - current_phy_phase_delay[lane] -= 0x10; + if (current_phy_phase_delay[lane] < 0x10) + current_phy_phase_delay[lane] = 0x0; + else + current_phy_phase_delay[lane] -= 0x10; /* Update hardware registers with final values */ write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg);

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Consolidate duplicated code
by Timothy Pearson 09 Mar '16

09 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13994 -gerrit commit e7413cbbeeae903d007ca6755e60c300badff078 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 18:25:15 2016 -0600 nb/amd/mct_ddr3: Consolidate duplicated code read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consoldiate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 95 ++++------------------- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 100 ++++++++++++++++++------- 2 files changed, 86 insertions(+), 109 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 1f71b2c..0ca634d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -17,8 +17,11 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); +static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); + +static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -383,76 +386,6 @@ static void write_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x3 | (dimm << 8), dword); } -static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0x3e; - else - mask = 0x3f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - delay[3] = (dword >> 24) & mask; - delay[2] = (dword >> 16) & mask; - delay[1] = (dword >> 8) & mask; - delay[0] = dword & mask; - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - delay[7] = (dword >> 24) & mask; - delay[6] = (dword >> 16) & mask; - delay[5] = (dword >> 8) & mask; - delay[4] = dword & mask; - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - delay[8] = dword & mask; -} - -static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0x3e; - else - mask = 0x3f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[3] & mask) << 24; - dword |= (delay[2] & mask) << 16; - dword |= (delay[1] & mask) << 8; - dword |= delay[0] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[7] & mask) << 24; - dword |= (delay[6] & mask) << 16; - dword |= (delay[5] & mask) << 8; - dword |= delay[4] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - dword &= ~mask; - dword |= delay[8] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); -} - /* DQS Position Training * Algorithm detailed in the Fam10h BKDG Rev. 3.62 section 2.8.9.9.3 */ @@ -982,7 +915,7 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, continue; read_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - read_read_dqs_timing_control_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); + read_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); for (lane = 0; lane < MAX_BYTE_LANES; lane++) if ((current_phy_phase_delay[lane] + current_read_dqs_delay[lane]) > max_delay) max_delay = (current_phy_phase_delay[lane] + current_read_dqs_delay[lane]); @@ -1407,10 +1340,10 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.4 (2 C) * For each Read DQS Delay value from 0 to 1 UI */ - for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x40; current_read_dqs_delay[lane] += 2) { + for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x20; current_read_dqs_delay[lane]++) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 161 current_read_dqs_delay[lane] ", current_read_dqs_delay[lane], 6); - if ((current_read_dqs_delay[lane] >> 1) >= (32 - 16)) { + if (current_read_dqs_delay[lane] >= (32 - 16)) { check_antiphase = 1; } else { check_antiphase = 0; @@ -1431,7 +1364,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x264); if ((dword & 0x1ffffff) != 0) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 162 early abort: F2x264 ", dword, 6); - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ continue; } } @@ -1442,16 +1375,16 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x268) & 0x3ffff; print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 163 read results: F2x268 ", dword, 6); if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 1; /* Pass */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 1; /* Pass */ if (check_antiphase == 1) { /* Check antiphase results */ dword = Get_NB32_DCT(dev, dct, 0x26c) & 0x3ffff; if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - (current_read_dqs_delay[lane] >> 1))] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 0; /* Fail */ else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - (current_read_dqs_delay[lane] >> 1))] = 1; /* Pass */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 1; /* Pass */ } } } @@ -1509,7 +1442,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay)); /* Program the Read DQS Timing Control register with the center of the passing window */ - current_read_dqs_delay[lane] = region_center << 1; + current_read_dqs_delay[lane] = region_center; passing_dqs_delay_found[lane] = 1; /* Commit the current Read DQS Timing Control settings to the hardware registers */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index b8d89fe..549c869 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -475,40 +475,84 @@ static void write_dram_phase_recovery_control_registers(uint16_t* current_total_ } } -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { - uint8_t lane; + uint8_t shift; uint32_t dword; + uint32_t mask; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t rdt_reg; + if (is_fam15h()) { + mask = 0x3e; + shift = 1; + } + else { + mask = 0x3f; + shift = 0; + } - /* Calculate DRAM Read DQS Timing register location */ - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - rdt_reg = 0x5; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - rdt_reg = 0x6; - if (lane == 8) - rdt_reg = 0x7; - rdt_reg |= (dimm << 8); + /* Lanes 0 - 3 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); + delay[3] = ((dword >> 24) & mask) >> shift; + delay[2] = ((dword >> 16) & mask) >> shift; + delay[1] = ((dword >> 8) & mask) >> shift; + delay[0] = (dword & mask) >> shift; + + /* Lanes 4 - 7 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); + delay[7] = ((dword >> 24) & mask) >> shift; + delay[6] = ((dword >> 16) & mask) >> shift; + delay[5] = ((dword >> 8) & mask) >> shift; + delay[4] = (dword & mask) >> shift; + + /* Lane 8 (ECC) */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); + delay[8] = (dword & mask) >> shift; +} - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, rdt_reg); - if ((lane == 7) || (lane == 3)) { - current_total_delay[lane] = (dword >> 24) & 0x3f; - } - if ((lane == 6) || (lane == 2)) { - current_total_delay[lane] = (dword >> 16) & 0x3f; - } - if ((lane == 5) || (lane == 1)) { - current_total_delay[lane] = (dword >> 8) & 0x3f; - } - if ((lane == 8) || (lane == 4) || (lane == 0)) { - current_total_delay[lane] = dword & 0x3f; - } +static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +{ + uint8_t shift; + uint32_t dword; + uint32_t mask; - if (is_fam15h()) - current_total_delay[lane] >>= 1; + if (is_fam15h()) { + mask = 0x3e; + shift = 1; + } + else { + mask = 0x3f; + shift = 0; } + + /* Lanes 0 - 3 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); + dword &= ~(mask << 24); + dword &= ~(mask << 16); + dword &= ~(mask << 8); + dword &= ~mask; + dword |= ((delay[3] << shift) & mask) << 24; + dword |= ((delay[2] << shift) & mask) << 16; + dword |= ((delay[1] << shift) & mask) << 8; + dword |= (delay[0] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); + + /* Lanes 4 - 7 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); + dword &= ~(mask << 24); + dword &= ~(mask << 16); + dword &= ~(mask << 8); + dword &= ~mask; + dword |= ((delay[7] << shift) & mask) << 24; + dword |= ((delay[6] << shift) & mask) << 16; + dword |= ((delay[5] << shift) & mask) << 8; + dword |= (delay[4] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); + + /* Lane 8 (ECC) */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); + dword &= ~mask; + dword |= (delay[8] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); } static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDCTstat, uint32_t testaddr, uint8_t channel) @@ -1593,7 +1637,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - read_read_dqs_timing_control_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); + read_dqs_read_data_timing_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); for (lane = 0; lane < 8; lane++) { current_total_delay[lane] += current_rdqs_total_delay[lane];

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coreboot-gerrit March 2016