coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: northbridge/i945/gma: Re-enable NVRAM tft_brightness
by Alexander Couzens 10 Mar '16

10 Mar '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14002 -gerrit commit d0cdee89d8477a89d769b981e66bef1566947373 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 10:42:58 2016 +0100 northbridge/i945/gma: Re-enable NVRAM tft_brightness Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init) unintentionally changed the code to ignore the NVRAM setting `tft_brightness`. Revert that hunk to restore the original behavior. Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/i945/gma.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index bd0a178..df13ef4 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -465,14 +465,17 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ - pci_write_config8(dev, 0xf4, 0xff); + if (get_option(&val, "tft_brightness") == CB_SUCCESS) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch set updated for coreboot: northbridge/intel/i440bx: Unify UDELAY selection
by Stefan Reinauer 10 Mar '16

10 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13781 -gerrit commit 54ee2e2668514202fcbad712fc7630ab84416388 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 11:01:54 2016 -0800 northbridge/intel/i440bx: Unify UDELAY selection Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/intel/socket_PGA370/Kconfig | 1 - src/drivers/pc80/Makefile.inc | 1 + src/mainboard/a-trend/atc-6220/Kconfig | 1 - src/mainboard/a-trend/atc-6220/romstage.c | 1 - src/mainboard/a-trend/atc-6240/Kconfig | 1 - src/mainboard/a-trend/atc-6240/romstage.c | 1 - src/mainboard/abit/be6-ii_v2_0/Kconfig | 1 - src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 - src/mainboard/asus/p2b-d/Kconfig | 1 - src/mainboard/asus/p2b-d/romstage.c | 1 - src/mainboard/asus/p2b-ds/Kconfig | 1 - src/mainboard/asus/p2b-ds/romstage.c | 1 - src/mainboard/asus/p2b-f/Kconfig | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/asus/p2b-ls/Kconfig | 1 - src/mainboard/asus/p2b-ls/romstage.c | 1 - src/mainboard/asus/p2b/Kconfig | 1 - src/mainboard/asus/p2b/romstage.c | 1 - src/mainboard/asus/p3b-f/Kconfig | 1 - src/mainboard/asus/p3b-f/romstage.c | 1 - src/mainboard/azza/pt-6ibd/Kconfig | 1 - src/mainboard/azza/pt-6ibd/romstage.c | 1 - src/mainboard/biostar/m6tba/Kconfig | 1 - src/mainboard/biostar/m6tba/romstage.c | 1 - src/mainboard/compaq/deskpro_en_sff_p600/Kconfig | 1 - src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 1 - src/mainboard/emulation/qemu-i440fx/romstage.c | 1 - src/mainboard/emulation/qemu-q35/romstage.c | 1 - src/mainboard/gigabyte/ga-6bxc/Kconfig | 1 - src/mainboard/gigabyte/ga-6bxc/romstage.c | 1 - src/mainboard/gigabyte/ga-6bxe/Kconfig | 1 - src/mainboard/gigabyte/ga-6bxe/romstage.c | 1 - src/mainboard/lanner/em8510/romstage.c | 1 - src/mainboard/msi/ms6119/Kconfig | 1 - src/mainboard/msi/ms6119/romstage.c | 1 - src/mainboard/msi/ms6147/Kconfig | 1 - src/mainboard/msi/ms6147/romstage.c | 1 - src/mainboard/msi/ms6156/Kconfig | 1 - src/mainboard/msi/ms6156/romstage.c | 1 - src/mainboard/msi/ms6178/romstage.c | 1 - src/mainboard/nokia/ip530/Kconfig | 1 - src/mainboard/nokia/ip530/romstage.c | 1 - src/mainboard/soyo/sy-6ba-plus-iii/Kconfig | 1 - src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 1 - src/mainboard/tyan/s1846/Kconfig | 1 - src/mainboard/tyan/s1846/romstage.c | 1 - src/northbridge/intel/i440bx/Kconfig | 1 + 47 files changed, 2 insertions(+), 45 deletions(-) diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 9e7bdae..b23308c 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -17,7 +17,6 @@ config CPU_INTEL_SOCKET_PGA370 bool select CPU_INTEL_MODEL_6XX select MMX - select UDELAY_TSC if CPU_INTEL_SOCKET_PGA370 diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 0788cc7..f468318 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -5,6 +5,7 @@ ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c +romstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/mainboard/a-trend/atc-6220/Kconfig b/src/mainboard/a-trend/atc-6220/Kconfig index 4f1966b..626f743 100644 --- a/src/mainboard/a-trend/atc-6220/Kconfig +++ b/src/mainboard/a-trend/atc-6220/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 35ee9bf..f075b4e 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/a-trend/atc-6240/Kconfig b/src/mainboard/a-trend/atc-6240/Kconfig index 6051b76..5d0d4f6 100644 --- a/src/mainboard/a-trend/atc-6240/Kconfig +++ b/src/mainboard/a-trend/atc-6240/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 1de647e..8c73824 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/abit/be6-ii_v2_0/Kconfig b/src/mainboard/abit/be6-ii_v2_0/Kconfig index b5eaff6..acb5f3a 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Kconfig +++ b/src/mainboard/abit/be6-ii_v2_0/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 08c4b4d..e38d846 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig index 7a13a45..ba2e7e0 100644 --- a/src/mainboard/asus/p2b-d/Kconfig +++ b/src/mainboard/asus/p2b-d/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SMP select IOAPIC - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index c83ca6d..b46646d 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index 53e4bdb..7d69d1f 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SMP select IOAPIC - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 65f8cea..4464f29 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig index 2c78ba7..b702c1b 100644 --- a/src/mainboard/asus/p2b-f/Kconfig +++ b/src/mainboard/asus/p2b-f/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index aa350f0..521ddbd 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index 9045f61..967ebd9 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index e5f66e9..5808bb8 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 46bff7c..6b934a5 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select HAVE_ACPI_TABLES diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 35ee9bf..f075b4e 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig index e6fab97..212aa93 100644 --- a/src/mainboard/asus/p3b-f/Kconfig +++ b/src/mainboard/asus/p3b-f/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 7a4108d..89e3795 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/azza/pt-6ibd/Kconfig b/src/mainboard/azza/pt-6ibd/Kconfig index 24809cc..67c9fa4 100644 --- a/src/mainboard/azza/pt-6ibd/Kconfig +++ b/src/mainboard/azza/pt-6ibd/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index eeb8a8c..8ed2fb1 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/biostar/m6tba/Kconfig b/src/mainboard/biostar/m6tba/Kconfig index 66e270c..6cb07e2 100644 --- a/src/mainboard/biostar/m6tba/Kconfig +++ b/src/mainboard/biostar/m6tba/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index d2900c1..eb7ef25 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig index 61fbb7d..bdb2157 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # should be SUPERIO_NSC_PC97307! select SUPERIO_NSC_PC97317 select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 89578b3..bf12a34 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index f16f8dd..d03c8ab 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index d54d8b0..fb0bccf 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -23,7 +23,6 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/gigabyte/ga-6bxc/Kconfig b/src/mainboard/gigabyte/ga-6bxc/Kconfig index 239e704..7e57819 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Kconfig +++ b/src/mainboard/gigabyte/ga-6bxc/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 8c36f6f..4128d30 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/Kconfig b/src/mainboard/gigabyte/ga-6bxe/Kconfig index 4e12b93..b225ed0 100644 --- a/src/mainboard/gigabyte/ga-6bxe/Kconfig +++ b/src/mainboard/gigabyte/ga-6bxe/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 58360c6..fac7416 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 76d9b94..0a8c4d7 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -23,7 +23,6 @@ #include <stdlib.h> #include <lib.h> #include <spd.h> -#include "drivers/pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801dx/i82801dx.h> diff --git a/src/mainboard/msi/ms6119/Kconfig b/src/mainboard/msi/ms6119/Kconfig index 0a25e80..c64e40b 100644 --- a/src/mainboard/msi/ms6119/Kconfig +++ b/src/mainboard/msi/ms6119/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 3031149..55e2eee 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6147/Kconfig b/src/mainboard/msi/ms6147/Kconfig index 6697c50..814855b 100644 --- a/src/mainboard/msi/ms6147/Kconfig +++ b/src/mainboard/msi/ms6147/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 53e14b3..00ad38c 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6156/Kconfig b/src/mainboard/msi/ms6156/Kconfig index e48505d..892d45c 100644 --- a/src/mainboard/msi/ms6156/Kconfig +++ b/src/mainboard/msi/ms6156/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 0a289d3..4ad2c50 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index d83bc02..aaad2ea 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index d5bc669..8d86257 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select PIRQ_ROUTE select HAVE_PIRQ_TABLE - select UDELAY_TSC select SDRAMPWR_4DIMM config MAINBOARD_DIR diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 9d9b680..42a5ac2 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig index d09a6ea..1b5931a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 9a8f0f8..1e25602 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/tyan/s1846/Kconfig b/src/mainboard/tyan/s1846/Kconfig index 9d2ad1e..2d6eeb7 100644 --- a/src/mainboard/tyan/s1846/Kconfig +++ b/src/mainboard/tyan/s1846/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 2783dbe..5cdc56d 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 828c693..3f574a4 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_INTEL_I440BX bool select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT + select UDELAY_IO config SDRAMPWR_4DIMM bool

1 0

Patch set updated for coreboot: SeaBIOS: Update SeaBIOS from repo when using master branch
by Martin Roth 10 Mar '16

10 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13947 -gerrit commit 7ab3f609b10995d850386194edca10933c9b2adb Author: Martin Roth <martinroth(a)google.com> Date: Mon Mar 7 21:56:24 2016 -0700 SeaBIOS: Update SeaBIOS from repo when using master branch Previously the SeaBIOS directory would never get updated after the initial clone because the tag would always match. This can be shown by noticing that the text 'Fetching new commits from the SeaBIOS git repo' is never seen. This change will always try to pull the latest code if 'Master' is selected. Change-Id: I460e2fb0c6f683a0f85343d164880c2d9e6d95cc Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/SeaBIOS/Makefile.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index c9d9199..4b134c8 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -15,8 +15,10 @@ seabios: git clone http://review.coreboot.org/p/seabios.git seabios fetch: seabios - cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ - then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ] || \ + [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the SeaBIOS git repo"; \ + git fetch; fi checkout: fetch echo " Checking out SeaBIOS revision $(TAG-y)"

1 0

Patch set updated for coreboot: crossgcc/Makefile.inc: Add target for jenkins toolchain test build
by Martin Roth 10 Mar '16

10 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13954 -gerrit commit 2a8eacc2316410de8f061df011f62b6ab3ff8733 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 09:27:45 2016 -0700 crossgcc/Makefile.inc: Add target for jenkins toolchain test build We've recently added a jenkins test builder for the coreboot toolchain. This patch allows what it builds to be controlled from the makefiles checked into git instead of by a rule on the builder itself. Change-Id: I65f70bac5ab97ecb27aae93ee370b26a2ab1f9c0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 0f27208..dfa1ec8 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -38,7 +38,8 @@ crossgcc: clean-for-update .PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ - crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 + crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ + jenkins-build-toolchain $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) build_iasl SKIP_GDB=1 @@ -65,3 +66,8 @@ ifeq ($(COMPILER_OUT_OF_DATE),1) else echo "The coreboot toolchain is the current version." endif # ifeq ($(COMPILER_OUT_OF_DATE),1) + +# This target controls what the jenkins builder tests +jenkins-build-toolchain: + $(MAKE) crosstools clang \ + BUILDGCC_OPTIONS='-y --nocolor'

1 0

Patch set updated for coreboot: nvramcui: Add distclean target
by Martin Roth 10 Mar '16

10 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13939 -gerrit commit c28ef3c7aa4678dd1b62c189a0d50d1508ff79a7 Author: Martin Roth <martinroth(a)google.com> Date: Mon Mar 7 16:40:14 2016 -0700 nvramcui: Add distclean target This doesn't do anything more than the clean target, but having both clean and distclean targets in all makefiles makes standardizing the cleaning routines easier. Change-Id: I41578de371a8f767ee23266c30e65e928f0985c4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/nvramcui/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index 73bcf78..10dc362 100755 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -8,3 +8,5 @@ all: nvramcui.elf .PHONY: clean: rm -f nvramcui.elf + +distclean: clean

1 0

Patch set updated for coreboot: src/lib/trace.c: Make address size generic
by Martin Roth 10 Mar '16

10 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13962 -gerrit commit 319c5f8c38c153def56a9fa5b5f5b88a52be4b89 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 12:17:44 2016 -0700 src/lib/trace.c: Make address size generic On platforms that didn't use 32-bit addresses, enabling the CONFIG_TRACE option (Trace function calls) would break the build due to a cast from a pointer of a different size. This fixes this warning: src/lib/trace.c:29:58: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] Change-Id: Iaab13c1891b6af7559ea6982ecc6e74c09dd0395 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/lib/trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/trace.c b/src/lib/trace.c index 8c29ab3..8f52331 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -26,7 +26,7 @@ void __cyg_profile_func_enter( void *func, void *callsite) return; DISABLE_TRACE - printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (uint32_t) func, (uint32_t) callsite); + printk(BIOS_INFO, "~0x%p(0x%p)\n", func, callsite); ENABLE_TRACE }

1 0

Patch set updated for coreboot: crosgcc/buildgcc: Update for recent arch additions
by Martin Roth 10 Mar '16

10 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13961 -gerrit commit 10ac7a593ce096fcb205a511bebdc25c9f718d08 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 12:07:04 2016 -0700 crosgcc/buildgcc: Update for recent arch additions - Add powerpc64le-linux-gnu & nds32le-elf to the instructions as supported architectures - Add nds32le-elf as a supported architecture so it will stop warning when you build it. Change-Id: Ifcdbc3d082eae5b9b5f8828914e7d2b7ed1f13a4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index df9ac4a..9266597 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -340,7 +340,8 @@ myhelp() printf " (defaults to $TARGETARCH)\n" printf " [-S|--scripting] build scripting support for GDB\n\n" printf "Platforms for GCC & GDB:\n" - printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n\n" + printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" + printf " powerpc64le-linux-gnu nds32le-elf\n\n } printversion() { @@ -624,6 +625,7 @@ case "$TARGETARCH" in i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=arm-eabi;; aarch64*) TARGETARCH=aarch64-elf;; + nds32le-elf) ;; *) printf "${red}WARNING: Unsupported architecture $TARGETARCH.${NC}\n\n"; ;; esac

1 0

Patch set updated for coreboot: cbmem: Add utility to get memory region occupied by cbmem
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13363 -gerrit commit f19b39f377a0b491ae3121108c4449a647420d56 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Nov 16 13:26:33 2015 -0800 cbmem: Add utility to get memory region occupied by cbmem Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/include/cbmem.h | 2 ++ src/lib/imd_cbmem.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efaa44f..2e947a1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -109,6 +109,8 @@ int cbmem_recovery(int s3resume); void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +/* Get location and size of CBMEM region in memory */ +void cbmem_region_used(uintptr_t *base, size_t *size); /* Indicate to each hook if cbmem is being recovered or not. */ typedef void (* const cbmem_init_hook_t)(int is_recovery); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 49faad9..e75c538 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -263,12 +263,19 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } +void cbmem_region_used(uintptr_t *base, size_t *size) +{ + void *baseptr; + imd_region_used(cbmem_get_imd(), &baseptr, size); + *base = (uintptr_t)baseptr; +} + void cbmem_add_bootmem(void) { void *base = NULL; size_t size = 0; - imd_region_used(cbmem_get_imd(), &base, &size); + cbmem_region_used(base, &size); bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE); }

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Patch set updated for coreboot: soc/apollolake: Add memory and reserve MMIO resources
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13360 -gerrit commit 0f08b36e65d5510f228935c3d6b249534c67ad3e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jan 15 18:05:12 2016 -0800 soc/apollolake: Add memory and reserve MMIO resources This adds most important MMIO reserved memory resources, real DRAM memory resources, and some DRAM resources that can not be used as RAM for whatever reason. Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/northbridge.c | 115 +++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 8581607..4e05726 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -33,6 +33,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c +ramstage-y += northbridge.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c new file mode 100644 index 0000000..0881525 --- /dev/null +++ b/src/soc/intel/apollolake/northbridge.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <soc/iomap.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/northbridge.h> +#include <soc/pci_ids.h> + +static uint32_t get_bar(device_t dev, unsigned int index) +{ + uint32_t bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled return 0 else strip enabled bit */ + return (bar & 1) ? (bar & ~1) : 0; +} + +static int mc_add_fixed_mmio_resources(device_t dev, int index) +{ + /* PCI extended config region */ + mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB), + PCIEX_SIZE / KiB); + + /* Memory Controller Hub */ + mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB), + MCH_BASE_SIZE / KiB); + + return index; +} + + +static int mc_add_dram_resources(device_t dev, int index) +{ + unsigned long base_k, size_k; + uint32_t bgsm, bdsm, tolud, tseg; + uint64_t touud; + + bgsm = ALIGN_DOWN(pci_read_config32(dev, BGSM), MiB); + bdsm = ALIGN_DOWN(pci_read_config32(dev, BDSM), MiB); + tolud = ALIGN_DOWN(pci_read_config32(dev, TOLUD), MiB); + tseg = ALIGN_DOWN(pci_read_config32(dev, TSEG), MiB); + + /* TOUUD is naturally a 64 bit integer */ + touud = pci_read_config32(dev, TOUUD + sizeof(uint32_t)); + touud <<= 32; + touud |= ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB); + + /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ + ram_resource(dev, index++, 0, 640); + + /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */ + base_k = 768; + size_k = (tseg / KiB) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG -> BGSM */ + reserved_ram_resource(dev, index++, tseg / KiB, (bgsm - tseg) / KiB); + + /* BGSM -> BDSM */ + mmio_resource(dev, index++, bgsm / KiB, (bdsm - bgsm) / KiB); + + /* BDSM -> TOLUD */ + mmio_resource(dev, index++, tolud / KiB, (tolud - bdsm) / KiB); + + /* 4G -> TOUUD */ + base_k = 4ULL*GiB / KiB; + size_k = (touud / KiB) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, index++, 640, 128); + + return index; +} + +static void northbridge_read_resources(device_t dev) +{ + + int index = 0; + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources. */ + index = mc_add_fixed_mmio_resources(dev, index); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, index); +} + +static struct device_operations northbridge_ops = { + .read_resources = northbridge_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = DEVICE_NOOP, + .enable = DEVICE_NOOP +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEV_ID_APOLLOLAKE_NB +};

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Populate static devicetree
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13926 -gerrit commit 6bf7b466313e3025b60cc3690f7017da8c56acdf Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Sun Mar 6 22:19:31 2016 -0800 mainboard/intel/apollolake_rvp: Populate static devicetree Add configuration in accordance to "PCI Configuration Matrix". Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/devicetree.cb | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index d624bc0..746aaf3 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -1,9 +1,56 @@ chip soc/intel/apollolake + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + device cpu_cluster 0 on device lapic 0 on end end device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS end end

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