coreboot-gerrit March 2016

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Patch set updated for coreboot: soc/intel/apollolake: Update platform-specific FSP headers
by Andrey Petrov 31 Mar '16

31 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14217 -gerrit commit ffcb70fd794dbe757337a9cb0bf262133445f8ff Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 18 14:43:00 2016 -0700 soc/intel/apollolake: Update platform-specific FSP headers This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/chip.c | 6 + src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 149 +-- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 1241 ++++++++++++++++---- 3 files changed, 1113 insertions(+), 283 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 2374a88..3c90e4a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -19,6 +19,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <memrange.h> +#include <soc/iomap.h> #include <soc/cpu.h> #include <soc/pci_devs.h> @@ -88,6 +89,11 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + + /* Our defaults may not match FSP defaults, so we set explicitly */ + silconfig->AcpiBase = ACPI_PMIO_BASE; + silconfig->PmcBase = PMC_BAR0 + 0x1000; + silconfig->P2sbBase = P2SB_BAR; } struct chip_operations soc_intel_apollolake_ops = { diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index e55b42b..9d3f8f6 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -81,6 +81,7 @@ struct BL_GPIO_PAD_INIT { wchar_t *PadName; } __attribute__((packed)); + /** Fsp M Architectural UPD **/ struct FSP_M_ARCH_UPD { @@ -119,349 +120,349 @@ struct FSP_M_ARCH_UPD { /** Offset 0x0038 **/ - uint8_t ReservedFspmArchUpd[8]; + uint8_t Reserved1[8]; } __attribute__((packed)); /** Fsp M Configuration **/ struct FSP_M_CONFIG { -/** Offset 0x0040 - Debug Serial Port Base - Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. +/** Offset 0x0040 - Debug Serial Port Base address + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. 0x00000000(Default). **/ uint32_t SerialDebugPortAddress; /** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. + 16550 compatible debug serial port resource type. NONE means no serial port support. 0x02:MMIO(Default). 0:NONE, 1:I/O, 2:MMIO **/ uint8_t SerialDebugPortType; /** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. 0x02:SOC UART2(Default). 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device **/ uint8_t SerialDebugPortDevice; /** Offset 0x0046 - Debug Serial Port Stride Size - Debug serial port register map stride size in bytes. + Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). 0:1, 2:4 **/ uint8_t SerialDebugPortStrideSize; /** Offset 0x0047 - Memory Fast Boot - Enable/Disable MRC fast boot support. + Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t MrcFastBoot; /** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t Igd; /** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. 0x02:64 MB(Default). 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB **/ uint8_t IgdDvmt50PreAlloc; /** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. + Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), 0x2:256 MB, 0x3:512 MB. 0x1:128 MB, 0x2:256 MB, 0x3:512 MB **/ uint8_t IgdApertureSize; /** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. + Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 MB(Default). 0x1:2 MB, 0x2:4 MB, 0x3:8 MB **/ uint8_t GttSize; /** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. + Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), 0x2:IGD, 0x3:PCI 0x0:AUTO, 0x2:IGD, 0x3:PCI **/ uint8_t PrimaryVideoAdaptor; /** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. 0x00(Default). 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD **/ uint8_t Package; /** Offset 0x004E - Profile - Profile list + Profile list. 0x19(Default). 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 **/ uint8_t Profile; /** Offset 0x004F - MemoryDown - Memory Down. + Memory Down. 0x0(Default). 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 **/ uint8_t MemoryDown; /** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. + NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB, 0x02:2KB, 0x00(Default). 0x1:1KB, 0x2:2KB **/ uint8_t DDR3LPageSize; /** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. + NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. 0x0:Not Supported, 0x1:Supported **/ uint8_t DDR3LASR; /** Offset 0x0052 - ScramblerSupport - Scrambler Support. + Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). $EN_DIS **/ uint8_t ScramblerSupport; /** Offset 0x0053 - ChannelHashMask - Channel Hash Mask. + Channel Hash Mask. 0x00(Default). **/ uint16_t ChannelHashMask; /** Offset 0x0055 - SliceHashMask - Slice Hash Mask. + Slice Hash Mask. 0x00(Default). **/ uint16_t SliceHashMask; /** Offset 0x0057 - InterleavedMode - Interleaved Mode. + Interleaved Mode. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ uint8_t InterleavedMode; /** Offset 0x0058 - ChannelsSlicesEnable - Channels Slices Enable. + Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ uint8_t ChannelsSlicesEnable; /** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. + Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ uint8_t MinRefRate2xEnable; /** Offset 0x005A - DualRankSupportEnable - Dual Rank Support Enable. + Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t DualRankSupportEnable; /** Offset 0x005B - RmtMode - Rank Margin Tool Mode. + Rank Margin Tool Mode. 0x00(Default). $EN_DIS **/ uint8_t RmtMode; /** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) **/ uint16_t MemorySizeLimit; /** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). **/ uint16_t LowMemoryMaxValue; /** Offset 0x0060 - DisableFastBoot - 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. + 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train of memory. $EN_DIS **/ uint8_t DisableFastBoot; /** Offset 0x0061 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). **/ uint16_t HighMemoryMaxValue; /** Offset 0x0063 - DIMM0SPDAddress - DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). **/ uint8_t DIMM0SPDAddress; /** Offset 0x0064 - DIMM1SPDAddress - DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). **/ uint8_t DIMM1SPDAddress; /** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). **/ uint8_t Ch0_RankEnable; /** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch0_DeviceWidth; /** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch0_DramDensity; /** Offset 0x0068 - Ch0_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). 0x03(Default). **/ uint8_t Ch0_Option; /** Offset 0x0069 - Ch0_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ uint8_t Ch0_OdtConfig; /** Offset 0x006A - Ch0_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\n Boolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch0_TristateClk1; /** Offset 0x006B - Ch0_Mode2N - [0] 2N Mode.\n Boolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch0_Mode2N; /** Offset 0x006C - Ch0_OdtLevels - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). **/ uint8_t Ch0_OdtLevels; /** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch1 rank. **/ uint8_t Ch1_RankEnable; /** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch1_DeviceWidth; /** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch1_DramDensity; /** Offset 0x0070 - Ch1_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B), 0x03(Default). **/ uint8_t Ch1_Option; /** Offset 0x0071 - Ch1_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ uint8_t Ch1_OdtConfig; /** Offset 0x0072 - Ch1_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch1_TristateClk1; /** Offset 0x0073 - Ch1_Mode2N - [0] 2N Mode.\nBoolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch1_Mode2N; /** Offset 0x0074 - Ch1_OdtLevels - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch1_OdtLevels; /** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch2 rank. **/ uint8_t Ch2_RankEnable; /** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch2_DeviceWidth; /** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch2_DramDensity; /** Offset 0x0078 - Ch2_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description.. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description.. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). 01:2KB (B). **/ uint8_t Ch2_Option; /** Offset 0x0079 - Ch2_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ uint8_t Ch2_OdtConfig; /** Offset 0x007A - Ch2_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch2_TristateClk1; /** Offset 0x007B - Ch2_Mode2N - [0] 2N Mode.\nBoolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch2_Mode2N; /** Offset 0x007C - Ch2_OdtLevels - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch2_OdtLevels; /** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). **/ uint8_t Ch3_RankEnable; /** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), 0x01:x16, 0x02:x32, 0x03:x64. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch3_DeviceWidth; /** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch3_DramDensity; /** Offset 0x0080 - Ch3_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description.. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description.. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - 2KB (B). **/ uint8_t Ch3_Option; /** Offset 0x0081 - Ch3_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. **/ uint8_t Ch3_OdtConfig; /** Offset 0x0082 - Ch3_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch3_TristateClk1; /** Offset 0x0083 - Ch3_Mode2N - [0] 2N Mode.\nBoolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch3_Mode2N; /** Offset 0x0084 - Ch3_OdtLevels - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch3_OdtLevels; /** Offset 0x0085 - RmtCheckRun - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + RmtCheckRun: 0x00(Default). **/ uint8_t RmtCheckRun; @@ -486,28 +487,34 @@ struct FSP_M_CONFIG { uint8_t Ch3_Bit_swizzling[32]; /** Offset 0x0106 - RmtMarginCheckScaleHighThreshold - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. + RmtMarginCheckScaleHighThreshold. 0x0000(Default). **/ uint16_t RmtMarginCheckScaleHighThreshold; /** Offset 0x0108 - MsgLevelMask - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. + MsgLevelMask. 0x00000000(Default). **/ uint32_t MsgLevelMask; /** Offset 0x010C - FIT Table Pointer - FIT table pointer. + FIT table pointer. 0x00000000(Default). **/ uint32_t FitTablePtr; /** Offset 0x0110 - GPIO Table Pointer - GPIO table pointer to a BL_GPIO_PAD_INIT structure. + GPIO table pointer to a BL_GPIO_PAD_INIT structure. 0x00000000(Default). **/ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0114 +/** Offset 0x0114 - Enhance the port 8xh decoding + Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). + $EN_DIS **/ - uint8_t ReservedFspmUpd[60]; + uint8_t EnhancePort8xhDecoding; + +/** Offset 0x0115 +**/ + uint8_t ReservedFspmUpd[59]; } __attribute__((packed)); /** Fsp M Test Configuration @@ -538,6 +545,8 @@ struct FSP_M_RESTRICTED_CONFIG { #define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ +/** Fsp M UPD Configuration +**/ struct FSPM_UPD { /** Offset 0x0000 diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index f2f867b..2ada27f 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -41,76 +41,76 @@ are permitted provided that the following conditions are met: struct FSP_S_CONFIG { /** Offset 0x0020 - ActiveProcessorCores - Number of active cores. + Number of active cores. 0:Disable(Default), 1:Enable. **/ uint8_t ActiveProcessorCores; /** Offset 0x0021 - Disable Core1 - Disable/Enable Core1. + Disable/Enable Core1. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t DisableCore1; /** Offset 0x0022 - Disable Core2 - Disable/Enable Core2. + Disable/Enable Core2. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t DisableCore2; /** Offset 0x0023 - Disable Core3 - Disable/Enable Core3. + Disable/Enable Core3. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t DisableCore3; /** Offset 0x0024 - VMX Enable - Enable or Disable VMX. + Enable or Disable VMX. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t VmxEnable; /** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) **/ uint8_t ProcTraceMemSize; /** Offset 0x0026 - Enable Processor Trace - Enable or Disable Processor Trace feature. + Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t ProcTraceEnable; /** Offset 0x0027 - Eist - Enable or Disable Intel SpeedStep Technology. + Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t Eist; /** Offset 0x0028 - Boot PState - Boot PState with HFM or LFM. 0: HFM; 1: LFM. + Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. **/ uint8_t BootPState; /** Offset 0x0029 - CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable. + Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t EnableCx; /** Offset 0x002A - Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable. + Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t C1e; /** Offset 0x002B - Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t BiProcHot; /** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto. + Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. **/ uint8_t PkgCStateLimit; @@ -119,407 +119,1220 @@ struct FSP_S_CONFIG { uint8_t UnusedUpdSpace0; /** Offset 0x002E - C-State auto-demotion - C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3. + C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion to C1 and C3. **/ uint8_t CStateAutoDemotion; /** Offset 0x002F - C-State un-demotion - C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion. + C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. **/ uint8_t CStateUnDemotion; /** Offset 0x0030 - Max Core C-State - Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx. + Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). **/ uint8_t MaxCoreCState; /** Offset 0x0031 - Package C-State Demotion - Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable. + Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PkgCStateDemotion; /** Offset 0x0032 - Package C-State Un-demotion - Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable. + Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PkgCStateUnDemotion; /** Offset 0x0033 - Turbo Mode - Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable. + Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t TurboMode; -/** Offset 0x0034 +/** Offset 0x0034 - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. 0(Default). **/ - uint8_t UnusedUpdSpace1[12]; + uint8_t HdaVerbTableEntryNum; + +/** Offset 0x0035 - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. 0x00000000(Default). +**/ + uint32_t HdaVerbTablePtr; + +/** Offset 0x0039 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t HideP2sb; + +/** Offset 0x003A - IPU Enable/Disable + Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t IpuEn; + +/** Offset 0x003B - IMGU ACPI mode selection + 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + uint8_t IpuAcpiMode; + +/** Offset 0x003C - GttMmAdr + GttMmAdr structure for initialization. 0xBF000000(Default). +**/ + uint32_t GttMmAdr; + +/** Offset 0x0040 - GmAdr + GmAdr structure for initialization. 0xA0000000(Default). +**/ + uint32_t GmAdr; + +/** Offset 0x0044 - Enable ForceWake + Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t ForceWake; + +/** Offset 0x0045 - Enable PavpLock + Enable/disable PavpLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PavpLock; + +/** Offset 0x0046 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsFreqModify; + +/** Offset 0x0047 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsFreqReq; + +/** Offset 0x0048 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsVideoFreq; + +/** Offset 0x0049 - Enable PmLock + Enable/disable PmLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PmLock; + +/** Offset 0x004A - Enable DopClockGating + Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DopClockGating; + +/** Offset 0x004B - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UnsolicitedAttackOverride; + +/** Offset 0x004C - Enable WOPCMSupport + Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t WOPCMSupport; + +/** Offset 0x004D - Enable WOPCMSize + Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t WOPCMSize; + +/** Offset 0x004E - Enable PowerGating + Enable/disable PowerGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PowerGating; + +/** Offset 0x004F - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UnitLevelClockGating; + +/** Offset 0x0050 - Enable FastBoot + Enable/disable FastBoot. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t FastBoot; + +/** Offset 0x0051 - Enable DynSR + Enable/disable DynSR. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DynSR; + +/** Offset 0x0052 - Enable SaIpuEnable + Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SaIpuEnable; + +/** Offset 0x0053 - BMP Logo Data Size + BMP logo data buffer size. 0x00000000(Default). +**/ + uint32_t LogoSize; + +/** Offset 0x0057 - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. 0x00000000(Default). +**/ + uint32_t LogoPtr; + +/** Offset 0x005B - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. 0x00000000(Default). +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x005F - GT PM Support + Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x0060 - RC6(Render Standby) + Enable/Disable render standby support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t EnableRenderStandby; + +/** Offset 0x0061 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0062 - PAVP PR3 + Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PavpPr3; + +/** Offset 0x0063 - CdClock Frequency selection + 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + uint8_t CdClock; + +/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit + Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x0065 - Write Protection Support + Enable/disable Write Protection. 0:Disable, 1:Enable(Default). +**/ + uint8_t WriteProtectionEnable[5]; + +/** Offset 0x006A - Read Protection Support + Enable/disable Read Protection. 0:Disable, 1:Enable(Default). +**/ + uint8_t ReadProtectionEnable[5]; + +/** Offset 0x006F - Protected Range Limitation + The address of the upper limit of protection, 0x0FFFh(Default). +**/ + uint16_t ProtectedRangeLimit[5]; -/** Offset 0x0040 - HD-Audio I/O Buffer Ownership - Set HD-Audio I/O Buffer Ownership. +/** Offset 0x0079 - Protected Range Base + The base address of the upper limit of protection. 0x0000(Default). +**/ + uint16_t ProtectedRangeBase[5]; + +/** Offset 0x0083 - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t Gmm; + +/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk + Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingPgcbClkTrunk; + +/** Offset 0x0085 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSb; + +/** Offset 0x0086 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSbClkTrunk; + +/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition + Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSbClkPartition; + +/** Offset 0x0088 - GMM Clock Gating - Core + Enable/disable Core. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingCore; + +/** Offset 0x0089 - GMM Clock Gating - DMA + Enable/disable DMA. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingDma; + +/** Offset 0x008A - GMM Clock Gating - Register Access + Enable/disable Register Access. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingRegAccess; + +/** Offset 0x008B - GMM Clock Gating - Host + Enable/disable Host. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingHost; + +/** Offset 0x008C - GMM Clock Gating - Partition + Enable/disable Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingPartition; + +/** Offset 0x008D - Clock Gating - Trunk + Enable/disable Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingTrunk; + +/** Offset 0x008E - HD Audio Support + Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t HdaEnable; + +/** Offset 0x008F - HD Audio DSP Support + Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DspEnable; + +/** Offset 0x0090 - Azalia wake-on-ring + Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t Pme; + +/** Offset 0x0091 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. 0:Disable(Default), 1:Enable. 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers **/ uint8_t HdAudioIoBufferOwnership; -/** Offset 0x0041 +/** Offset 0x0092 - HD-Audio I/O Buffer Voltage + HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. + 0: 3.3V, 1: 1.8V +**/ + uint8_t HdAudioIoBufferVoltage; + +/** Offset 0x0093 - HD-Audio Virtual Channel Type + HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. + 0: VC0, 1: VC1 +**/ + uint8_t HdAudioVcType; + +/** Offset 0x0094 - HD-Audio Link Frequency + HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + uint8_t HdAudioLinkFrequency; + +/** Offset 0x0095 - HD-Audio iDisp-Link Frequency + HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + uint8_t HdAudioIDispLinkFrequency; + +/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode + HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. + 0: 2T, 1: 1T +**/ + uint8_t HdAudioIDispLinkTmode; + +/** Offset 0x0097 - HD-Audio Disp DMIC + HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. + 0: Disable, 1: 2ch array, 2: 4ch array **/ - uint8_t UnusedUpdSpace2[5]; + uint8_t DspEndpointDmic; -/** Offset 0x0046 - Enable SD controller - Enable/disable SD Card controller. +/** Offset 0x0098 - HD-Audio Bluetooth + Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SdcardEnabled; + uint8_t DspEndpointBluetooth; -/** Offset 0x0047 - Enable SDIO controller - Enable/disable SDIO controller. +/** Offset 0x0099 - HD-Audio I2S SHK + Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SdioEnabled; + uint8_t DspEndpointI2sSkp; -/** Offset 0x0048 - Enable eMMC controller - Enable/disable eMMC controller. +/** Offset 0x009A - HD-Audio I2S HP + Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t eMMCEnabled; + uint8_t DspEndpointI2sHp; -/** Offset 0x0049 - Enable SATA - Enable/disable SATA controller. +/** Offset 0x009B - HD-Audio Controller Power Gating + Enable/Disable HD-Audio Controller Power Gating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t EnableSata; + uint8_t AudioCtlPwrGate; -/** Offset 0x004A - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID +/** Offset 0x009C - HD-Audio ADSP Power Gating + Enable/Disable HD-Audio ADSP Power Gating. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t SataMode; + uint8_t AudioDspPwrGate; -/** Offset 0x004B - Aggressive SATA LPM Support - Enable SOC to aggressively enter link power state for SATA. +/** Offset 0x009D - HD-Audio CSME Memory Transfers + Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + uint8_t Mmt; + +/** Offset 0x009E - HD-Audio Host Memory Transfers + Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + uint8_t Hmt; + +/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SataSalpSupport; + uint8_t BiosCfgLockDown; -/** Offset 0x004C - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00A0 - HD-Audio Power Gating + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t SataPortsEnable[2]; + uint8_t HDAudioPwrGate; -/** Offset 0x004E - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00A1 - HD-Audio Clock Gatingn + Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t SataPortsDevSlp[2]; + uint8_t HDAudioClkGate; -/** Offset 0x0050 - Enable PCIE RP - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +/** Offset 0x00A2 - Bitmask of DSP Feature + Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation **/ - uint8_t PcieRootPortEn[6]; + uint32_t DspFeatureMask; -/** Offset 0x0056 - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules + Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation **/ - uint8_t PcieRpClkReqNumber[6]; + uint32_t DspPpModuleMask; -/** Offset 0x005C +/** Offset 0x00AA - Enable High Precision Timer + Enable/Disable Hpet. 0:Disable, 1:Enable(Default). + $EN_DIS **/ - uint8_t UnusedUpdSpace3[16]; + uint8_t Hpet; -/** Offset 0x006C - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00AB - Hpet Valid BDF Value + Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t PortUsb20Enable[8]; + uint8_t HpetBdfValid; -/** Offset 0x0074 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00AC - Bus Number of Hpet + Completer ID of Bus Number of Hpet. Default = 0xFA(Default). **/ - uint8_t PortUsb30Enable[6]; + uint8_t HpetBusNumber; -/** Offset 0x007A - Enable XHCI SSIC ports - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. +/** Offset 0x00AD - Device Number of Hpet + Completer ID of Device Number of Hpet. 0x1F(Default). **/ - uint8_t SsicPortEnable[2]; + uint8_t HpetDeviceNumber; -/** Offset 0x007C - Enable SMBus - Enable/disable SMBus controller. +/** Offset 0x00AE - Function Number of Hpet + Completer ID of Function Number of Hpet. 0x00(Default). +**/ + uint8_t HpetFunctionNumber; + +/** Offset 0x00AF - Hpet Base Address + Hpet Base Address. 0xFED00000(Default). +**/ + uint32_t HpetBase; + +/** Offset 0x00B3 - IoApic Valid BDF Value + Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SmbusEnable; + uint8_t IoApicBdfValid; -/** Offset 0x007D - SC HDA Verb Table Entry Number - Number of Entries in Verb Table. +/** Offset 0x00B4 - Bus Number of IoApic + Completer ID of Bus Number of IoApic. 0xFA(Default). **/ - uint8_t HdaVerbTableEntryNum; + uint8_t IoApicBusNumber; -/** Offset 0x007E - SC HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. +/** Offset 0x00B5 - Device Number of IoApic + Completer ID of Device Number of IoApic. 0x0F(Default). **/ - uint32_t HdaVerbTablePtr; + uint8_t IoApicDeviceNumber; -/** Offset 0x0082 +/** Offset 0x00B6 - Function Number of IoApic + Completer ID of Function Number of IoApic. 0x00(Default). **/ - uint8_t UnusedUpdSpace4[14]; + uint8_t IoApicFunctionNumber; -/** Offset 0x0090 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. +/** Offset 0x00B7 - IOAPIC Entry 24-119 + Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t HideP2sb; + uint8_t IoApicEntry24_119; + +/** Offset 0x00B8 - IO APIC ID + This member determines IOAPIC ID. 0x01(Default). +**/ + uint8_t IoApicId; -/** Offset 0x0091 - Ufs Enable/Disable - Enable/Disable Ufs. +/** Offset 0x00B9 - IoApic Range + Define address bits 19:12 for the IOxAPIC range. 0x00(Default). +**/ + uint8_t IoApicRangeSelect; + +/** Offset 0x00BA - ISH Controller + Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t UfsEnabled; + uint8_t IshEnable; -/** Offset 0x0092 - IPU Enable/Disable - Enable/Disable IPU Device. +/** Offset 0x00BB - ISH Controller + Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t IpuEn; + uint8_t BiosInterface; -/** Offset 0x0093 - IMGU ACPI mode selection - 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device - 0:Disable, 1:IGFX Child device, 2:ACPI device +/** Offset 0x00BC - Bios LockDown Enable + Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t IpuAcpiMode; + uint8_t BiosLock; -/** Offset 0x0094 - ResetSelect - ResetSelect. 0x6:warm reset; 0xE:cold reset +/** Offset 0x00BD - SPI EISS Status + Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). + $EN_DIS **/ - uint8_t ResetSelect; + uint8_t SpiEiss; -/** Offset 0x0095 - CRIDSettings - PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3 +/** Offset 0x00BE - BiosLock SWSMI Number + This member describes the SwSmi value for Bios Lock. 0xA9(Default). **/ - uint8_t CRIDSettings; + uint8_t BiosLockSwSmiNumber; -/** Offset 0x0096 - Enable HPET - Enable/disable HPET. +/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable + Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t Hpet; + uint8_t S0ixEnable; -/** Offset 0x0097 - Enable PCIE Clock Gating - Enable/disable PCIE Clock Gating.0:Enable;1:Disable +/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration + Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t I2cClkGateCfg[8]; + +/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration + Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t HsuartClkGateCfg[4]; + +/** Offset 0x00CC - LPSS SPI Clock Gating Configuration + Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t SpiClkGateCfg[3]; + +/** Offset 0x00CF - I2C Device 0 + Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c0Enable; + +/** Offset 0x00D0 - I2C Device 1 + Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c1Enable; + +/** Offset 0x00D1 - I2C Device 2 + Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c2Enable; + +/** Offset 0x00D2 - I2C Device 3 + Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c3Enable; + +/** Offset 0x00D3 - I2C Device 4 + Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c4Enable; + +/** Offset 0x00D4 - I2C Device 5 + Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c5Enable; + +/** Offset 0x00D5 - I2C Device 6 + Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c6Enable; + +/** Offset 0x00D6 - I2C Device 7 + Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c7Enable; + +/** Offset 0x00D7 - UART Device 0 + Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart0Enable; + +/** Offset 0x00D8 - UART Device 1 + Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart1Enable; + +/** Offset 0x00D9 - UART Device 2 + Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart2Enable; + +/** Offset 0x00DA - UART Device 3 + Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart3Enable; + +/** Offset 0x00DB - SPI UART Device 0 + Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi0Enable; + +/** Offset 0x00DC - SPI UART Device 1 + Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi1Enable; + +/** Offset 0x00DD - SPI UART Device 2 + Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi2Enable; + +/** Offset 0x00DE - UART Debug Bass Address + UART Debug Bass Address. 0x00000000(Default). +**/ + uint32_t Uart2KernelDebugBaseAddress; + +/** Offset 0x00E2 - OS Debug Feature + Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + uint8_t OsDbgEnable; + +/** Offset 0x00E3 - Exi Feature + Enable/Disable Exi Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + uint8_t ExiEnable; + +/** Offset 0x00E4 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). $EN_DIS **/ uint8_t PcieClockGatingDisabled; -/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode - Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable +/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t PcieRootPort8xhDecode; -/** Offset 0x0099 - PCIE 8xh Decode Port Index - PCIE 8xh Decode Port Index. +/** Offset 0x00E6 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. 0x00(Default). **/ uint8_t Pcie8xhDecodePortIndex; -/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write - Enable/disable PCIE root port peer memory write.0:Disable;1:Enable +/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PcieRootPortPeerMemoryWriteEnable; -/** Offset 0x009B - Enable SC Gaussian Mixture Models - Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable - $EN_DIS +/** Offset 0x00E8 - PCIE SWSMI Nubmer + This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ - uint8_t Gmm; + uint8_t PcieAspmSwSmiNumber; -/** Offset 0x009C - GttMmAdr - GttMmAdr structure for initialization. +/** Offset 0x00E9 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). **/ - uint32_t GttMmAdr; + uint8_t PcieRootPortEn[6]; + +/** Offset 0x00EF - Hide PCIE Root Port Configuration Space + Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpHide[6]; + +/** Offset 0x00F5 - PCIE Root Port Slot Implement + Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpSlotImplemented[6]; + +/** Offset 0x00FB - Hot Plug + PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpHotPlug[6]; + +/** Offset 0x0101 - PCIE PM SCI + Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpPmSci[6]; + +/** Offset 0x0107 - PCIE Root Port Extended Sync + Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpExtSync[6]; + +/** Offset 0x010D - Transmitter Half Swing + Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpTransmitterHalfSwing[6]; + +/** Offset 0x0113 - ACS + Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpAcsEnabled[6]; + +/** Offset 0x0119 - Clock Request Support + Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpClkReqSupported[6]; -/** Offset 0x00A0 +/** Offset 0x011F - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, 0x01, 0x02, 0x03. **/ - uint8_t UnusedUpdSpace5[96]; + uint8_t PcieRpClkReqNumber[6]; + +/** Offset 0x0125 - CLKREQ# Detection + Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. +**/ + uint8_t PcieRpClkReqDetect[6]; + +/** Offset 0x012B - Advanced Error Reporting + Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. +**/ + uint8_t AdvancedErrorReporting[6]; + +/** Offset 0x0131 - PME Interrupt + Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. +**/ + uint8_t PmeInterrupt[6]; + +/** Offset 0x0137 - URR + PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t UnsupportedRequestReport[6]; + +/** Offset 0x013D - FER + PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t FatalErrorReport[6]; + +/** Offset 0x0143 - NFER + PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t NoFatalErrorReport[6]; + +/** Offset 0x0149 - CER + PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t CorrectableErrorReport[6]; + +/** Offset 0x014F - SEFE + Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnFatalError[6]; + +/** Offset 0x0155 - SENFE + Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnNonFatalError[6]; + +/** Offset 0x015B - SECE + Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnCorrectableError[6]; + +/** Offset 0x0161 - PCIe Speed + Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. +**/ + uint8_t PcieRpSpeed[6]; + +/** Offset 0x0167 - Physical Slot Number + Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. +**/ + uint8_t PhysicalSlotNumber[6]; + +/** Offset 0x016D - CTO + Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpCompletionTimeout[6]; + +/** Offset 0x0173 - PTM Support + Enable/Diable PTM Support. 0:Disable(Default), 1:Enable. +**/ + uint8_t PtmEnable[6]; -/** Offset 0x0100 - Enable S0ix - Enable/disable S0ix.0:Disable;1:Enable +/** Offset 0x0179 - ASPM + PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, 4:Auto(Default). +**/ + uint8_t PcieRpAspm[6]; + +/** Offset 0x017F - L1 Substates + PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). +**/ + uint8_t PcieRpL1Substates[6]; + +/** Offset 0x0185 - PCH PCIe LTR + PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpLtrEnable[6]; + +/** Offset 0x018B - PCIE LTR Lock + PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpLtrConfigLock[6]; + +/** Offset 0x0191 - PME_B0_S5 Diable bit + PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t S0ix; + uint8_t PmeB0S5Dis; -/** Offset 0x0101 - GmAdr - GmAdr structure for initialization. +/** Offset 0x0192 - PCI Clock Run + This member describes whether or not the PCI ClockRun feature of SC should be enabled. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint32_t GmAdr; + uint8_t PciClockRun; -/** Offset 0x0105 - Enable ForceWake - Enable/disable ForceWake Models.0:Disable;1:Enable +/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ForceWake; + uint8_t Timer8254ClkSetting; -/** Offset 0x0106 - Enable PavpLock - Enable/disable PavpLock.0:Disable;1:Enable +/** Offset 0x0194 - Chipset SATA + Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PavpLock; + uint8_t EnableSata; -/** Offset 0x0107 - Enable GraphicsFreqModify - Enable/disable GraphicsFreqModify.0:Disable;1:Enable +/** Offset 0x0195 - SATA Mode Selection + Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x0196 - Aggressive LPM Support + Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t GraphicsFreqModify; + uint8_t SataSalpSupport; -/** Offset 0x0108 - Enable GraphicsFreqReq - Enable/disable GraphicsFreqReq.0:Disable;1:Enable +/** Offset 0x0197 - SATA Power Optimization + Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsFreqReq; + uint8_t SataPwrOptEnable; -/** Offset 0x0109 - Enable GraphicsVideoFreq - Enable/disable GraphicsVideoFreq.0:Disable;1:Enable +/** Offset 0x0198 - eSATA Speed Limit + Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsVideoFreq; + uint8_t eSATASpeedLimit; + +/** Offset 0x0199 - SATA Speed Limit + SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). + 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) +**/ + uint8_t SpeedLimit; -/** Offset 0x010A - Enable PmLock - Enable/disable PmLock.0:Disable;1:Enable +/** Offset 0x019A - SATA Port + Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). +**/ + uint8_t SataPortsEnable[2]; + +/** Offset 0x019C - SATA Port DevSlp + Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsDevSlp[2]; + +/** Offset 0x019E - SATA Port HotPlug + Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsHotPlug[2]; + +/** Offset 0x01A0 - Mechanical Presence Switch + Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires hardware support. 0:Disable, 1:Enable(Default). +**/ + uint8_t SataPortsInterlockSw[2]; + +/** Offset 0x01A2 - External SATA Ports + Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsExternal[2]; + +/** Offset 0x01A4 - Spin Up Device + Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsSpinUp[2]; + +/** Offset 0x01A6 - SATA Solid State + Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard Disk Drive(Default), 1:Solid State Drive. +**/ + uint8_t SataPortsSolidStateDrive[2]; + +/** Offset 0x01A8 - DITO Configuration + Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsEnableDitoConfig[2]; + +/** Offset 0x01AA - DM Value + DM Value. 0:Minimum, 0x0F:Maximum(Default). +**/ + uint8_t SataPortsDmVal[2]; + +/** Offset 0x01AC - DITO Value + DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). +**/ + uint16_t SataPortsDitoVal[2]; + +/** Offset 0x01B0 - Subsystem Vendor ID + Subsystem Vendor ID. 0x8086(Default). +**/ + uint16_t SubSystemVendorId; + +/** Offset 0x01B2 - Subsystem ID + Subsystem ID. 0x7270(Default). +**/ + uint16_t SubSystemId; + +/** Offset 0x01B4 - PM Base Address + PM Base Address. 0x400(Default). +**/ + uint16_t AcpiBase; + +/** Offset 0x01B6 - PMC Base Address + PMC Base Address. 0xD10010000(Default). +**/ + uint32_t PmcBase; + +/** Offset 0x01BA - P2SB Base Address + P2SB Base Address. 0xD0000000(Default). +**/ + uint32_t P2sbBase; + +/** Offset 0x01BE - CRIDSettings + PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. +**/ + uint8_t CRIDSettings; + +/** Offset 0x01BF - ResetSelect + ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. +**/ + uint8_t ResetSelect; + +/** Offset 0x01C0 - SD Card Support (D27:F0) + Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PmLock; + uint8_t SdcardEnabled; -/** Offset 0x010B +/** Offset 0x01C1 - SeMMC Support (D28:F0) + Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t eMMCEnabled; + +/** Offset 0x01C2 - eMMC Max Speed + Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. + 0:HS400, 1: HS200, 2:DDR50 **/ - uint8_t UnusedUpdSpace6[5]; + uint8_t eMMCHostMaxSpeed; -/** Offset 0x0110 - Enable DopClockGating - Enable/disable DopClockGating.0:Disable;1:Enable +/** Offset 0x01C3 - UFS Support (D29:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DopClockGating; + uint8_t UfsEnabled; -/** Offset 0x0111 - Enable UnsolicitedAttackOverride - Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable +/** Offset 0x01C4 - SDIO Support (D30:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t UnsolicitedAttackOverride; + uint8_t SdioEnabled; -/** Offset 0x0112 - Enable WOPCMSupport - Enable/disable WOPCMSupport.0:Disable;1:Enable +/** Offset 0x01C5 - GPP Lock Feature + Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t WOPCMSupport; + uint8_t GppLock; -/** Offset 0x0113 - Enable WOPCMSize - Enable/disable WOPCMSize.0:Disable;1:Enable +/** Offset 0x01C6 - Serial IRQ + Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t WOPCMSize; + uint8_t SirqEnable; -/** Offset 0x0114 - Enable PowerGating - Enable/disable PowerGating.0:Disable;1:Enable +/** Offset 0x01C7 - Serial IRQ Mode + Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. $EN_DIS **/ - uint8_t PowerGating; + uint8_t SirqMode; -/** Offset 0x0115 - Enable UnitLevelClockGating - Enable/disable UnitLevelClockGating.0:Disable;1:Enable +/** Offset 0x01C8 - Start Frame Pulse Width + Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. $EN_DIS **/ - uint8_t UnitLevelClockGating; + uint8_t StartFramePulse; -/** Offset 0x0116 - Enable FastBoot - Enable/disable FastBoot.0:Disable;1:Enable +/** Offset 0x01C9 - Enable SMBus + Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t FastBoot; + uint8_t SmbusEnable; -/** Offset 0x0117 - Enable DynSR - Enable/disable DynSR.0:Disable;1:Enable +/** Offset 0x01CA - SMBus ARP Support + Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DynSR; + uint8_t ArpEnable; + +/** Offset 0x01CB - SMBus Base Address (IO space) + SMBUS Base Address (IO space). 0xEFA0(Default). +**/ + uint16_t SmbusIoBase; + +/** Offset 0x01CD - SMBus Table Elements + The number of elements in the Reserved SMBus Address Table. 0x0080(Default). +**/ + uint16_t NumRsvdSmbusAddresses; + +/** Offset 0x01CF - Reserved SMBus Address Table + Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). +**/ + uint8_t RsvdSmbusAddressTable[128]; -/** Offset 0x0118 - Enable SaIpuEnable - Enable/disable SaIpuEnable.0:Disable;1:Enable +/** Offset 0x024F - XHCI Disable Compliance Mode + Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. $EN_DIS **/ - uint8_t SaIpuEnable; + uint8_t DisableComplianceMode; -/** Offset 0x0119 - Enable VtdEnable - Enable/disable VtdEnable.0:Disable;1:Enable +/** Offset 0x0250 - USB Per-Port Control + Control each of the USB ports (0~3) enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t VtdEnable; + uint8_t UsbPerPortCtl; -/** Offset 0x011A - BMP Logo Data Size - BMP logo data buffer size. +/** Offset 0x0251 - xHCI Mode + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default), 3:SmartAuto. + $EN_DIS **/ - uint32_t LogoSize; + uint8_t Usb30Mode; -/** Offset 0x011E - BMP Logo Data Pointer - BMP logo data pointer to a BMP format buffer. +/** Offset 0x0252 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). **/ - uint32_t LogoPtr; + uint8_t PortUsb20Enable[8]; -/** Offset 0x0122 - Graphics Configuration Data Pointer - Graphics configuration data used for initialization. +/** Offset 0x025A - USB20 Over Current Pin + Over Current Pin number of USB 2.0 Port. 0x00(Default). **/ - uint32_t GraphicsConfigPtr; + uint8_t PortUs20bOverCurrentPin[8]; -/** Offset 0x0126 - GT PM Support - Enable/Disable GT power management support. +/** Offset 0x0262 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). +**/ + uint8_t PortUsb30Enable[6]; + +/** Offset 0x0268 - USB20 Over Current Pin + Over Current Pin number of USB 3.0 Port. 0x01(Default). +**/ + uint8_t PortUs30bOverCurrentPin[6]; + +/** Offset 0x026E - XDCI Support + Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. $EN_DIS **/ - uint8_t PmSupport; + uint8_t UsbOtg; -/** Offset 0x0127 - RC6(Render Standby) - Enable/Disable render standby support. +/** Offset 0x026F - Enable XHCI HSIC Support + Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t EnableRenderStandby; + uint8_t HsicSupportEnable; -/** Offset 0x0128 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). +/** Offset 0x0270 - Enable XHCI SSIC Support + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. 0x00(Default). +**/ + uint8_t SsicPortEnable[2]; + +/** Offset 0x0272 - SSIC Dlane PowerGating + Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PavpEnable; + uint16_t DlanePwrGating; -/** Offset 0x0129 - PAVP PR3 - Enable/Disable PAVP PR3 +/** Offset 0x0274 - VT-d + Enable/Disable VT-d. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PavpPr3; + uint8_t VtdEnable; -/** Offset 0x012A - CdClock Frequency selection - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +/** Offset 0x0275 - HDAudio Delay Timer + The delay timer after Azalia reset. 0x012C(Default). **/ - uint8_t CdClock; + uint16_t ResetWaitTimer; -/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit - Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit +/** Offset 0x0277 - SMI Lock bit + Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PeiGraphicsPeimInit; + uint8_t LockDownGlobalSmi; -/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock +/** Offset 0x0278 - RTC Lock Bits + Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t Timer8254ClkSetting; + uint8_t RtcLock; + +/** Offset 0x0279 - XHCI SSIC RATE + Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. +**/ + uint8_t SsicRate[2]; + +/** Offset 0x027B - SATA Test Mode Selection + Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SataTestMode; + +/** Offset 0x027C - SMBus Dynamic Power Gating + Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint16_t DynamicPowerGating; + +/** Offset 0x027E - Max Snoop Latency + Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). +**/ + uint16_t PcieRpLtrMaxSnoopLatency[6]; + +/** Offset 0x028A - Snoop Latency Override + Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + uint8_t PcieRpSnoopLatencyOverrideMode[6]; + +/** Offset 0x0290 - Snoop Latency Value + LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + uint16_t PcieRpSnoopLatencyOverrideValue[6]; + +/** Offset 0x029C - Snoop Latency Multiplier + LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + uint8_t PcieRpSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02A2 - Max Non-Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). +**/ + uint16_t PcieRpLtrMaxNonSnoopLatency[6]; -/** Offset 0x012D +/** Offset 0x02AE - Non Snoop Latency Override + Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ - uint8_t ReservedFspsUpd[211]; + uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; + +/** Offset 0x02B4 - Non Snoop Latency Value + LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + uint16_t PcieRpNonSnoopLatencyOverrideValue[6]; + +/** Offset 0x02C0 - Non Snoop Latency Multiplier + LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale + Specifies scale used for slot power limit value. 0x00(Default). +**/ + uint8_t PcieRpSlotPowerLimitScale[6]; + +/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value + Specifies upper limit on power supplie by slot. 0x00(Default). +**/ + uint8_t PcieRpSlotPowerLimitValue[6]; + +/** Offset 0x02D2 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize(Default), 1: Skip + $EN_DIS +**/ + uint8_t SkipMpInit; + +/** Offset 0x02D3 +**/ + uint8_t ReservedFspsUpd[45]; } __attribute__((packed)); /** Fsp S Test Configuration **/ struct FSP_S_TEST_CONFIG { -/** Offset 0x0200 +/** Offset 0x0300 **/ uint32_t Signature; -/** Offset 0x0204 +/** Offset 0x0304 **/ uint8_t ReservedFspsTestUpd[12]; } __attribute__((packed)); @@ -528,17 +1341,19 @@ struct FSP_S_TEST_CONFIG { **/ struct FSP_S_RESTRICTED_CONFIG { -/** Offset 0x0210 +/** Offset 0x0310 **/ uint32_t Signature; -/** Offset 0x0214 +/** Offset 0x0314 **/ uint8_t ReservedFspsRestrictedUpd[12]; } __attribute__((packed)); #define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +/** Fsp S UPD Configuration +**/ struct FSPS_UPD { /** Offset 0x0000 @@ -549,15 +1364,15 @@ struct FSPS_UPD { **/ struct FSP_S_CONFIG FspsConfig; -/** Offset 0x0200 +/** Offset 0x0300 **/ struct FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0210 +/** Offset 0x0310 **/ struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; -/** Offset 0x0220 +/** Offset 0x0320 **/ uint16_t UpdTerminator; } __attribute__((packed));

1 0

New patch to review for coreboot: soc/intel/apollolake: Update platform-specific FSP headers
by Andrey Petrov 31 Mar '16

31 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14217 -gerrit commit 338c4d74ff0735ccc372694d4c03ce22fea5fedf Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 18 14:43:00 2016 -0700 soc/intel/apollolake: Update platform-specific FSP headers This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/chip.c | 5 + src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 149 +-- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 1241 ++++++++++++++++---- 3 files changed, 1112 insertions(+), 283 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 2374a88..90c473d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -88,6 +88,11 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + + /* Our defaults may not match FSP defaults, so we set explicitly */ + silconfig->AcpiBase = ACPI_PMIO_BASE; + silconfig->PmcBase = PMC_BAR0 + 0x1000; + silconfig->P2sbBase = P2SB_BAR; } struct chip_operations soc_intel_apollolake_ops = { diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index e55b42b..9d3f8f6 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -81,6 +81,7 @@ struct BL_GPIO_PAD_INIT { wchar_t *PadName; } __attribute__((packed)); + /** Fsp M Architectural UPD **/ struct FSP_M_ARCH_UPD { @@ -119,349 +120,349 @@ struct FSP_M_ARCH_UPD { /** Offset 0x0038 **/ - uint8_t ReservedFspmArchUpd[8]; + uint8_t Reserved1[8]; } __attribute__((packed)); /** Fsp M Configuration **/ struct FSP_M_CONFIG { -/** Offset 0x0040 - Debug Serial Port Base - Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. +/** Offset 0x0040 - Debug Serial Port Base address + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. 0x00000000(Default). **/ uint32_t SerialDebugPortAddress; /** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. + 16550 compatible debug serial port resource type. NONE means no serial port support. 0x02:MMIO(Default). 0:NONE, 1:I/O, 2:MMIO **/ uint8_t SerialDebugPortType; /** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. 0x02:SOC UART2(Default). 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device **/ uint8_t SerialDebugPortDevice; /** Offset 0x0046 - Debug Serial Port Stride Size - Debug serial port register map stride size in bytes. + Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). 0:1, 2:4 **/ uint8_t SerialDebugPortStrideSize; /** Offset 0x0047 - Memory Fast Boot - Enable/Disable MRC fast boot support. + Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t MrcFastBoot; /** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t Igd; /** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. 0x02:64 MB(Default). 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB **/ uint8_t IgdDvmt50PreAlloc; /** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. + Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), 0x2:256 MB, 0x3:512 MB. 0x1:128 MB, 0x2:256 MB, 0x3:512 MB **/ uint8_t IgdApertureSize; /** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. + Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 MB(Default). 0x1:2 MB, 0x2:4 MB, 0x3:8 MB **/ uint8_t GttSize; /** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. + Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), 0x2:IGD, 0x3:PCI 0x0:AUTO, 0x2:IGD, 0x3:PCI **/ uint8_t PrimaryVideoAdaptor; /** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. 0x00(Default). 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD **/ uint8_t Package; /** Offset 0x004E - Profile - Profile list + Profile list. 0x19(Default). 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 **/ uint8_t Profile; /** Offset 0x004F - MemoryDown - Memory Down. + Memory Down. 0x0(Default). 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 **/ uint8_t MemoryDown; /** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. + NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB, 0x02:2KB, 0x00(Default). 0x1:1KB, 0x2:2KB **/ uint8_t DDR3LPageSize; /** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. + NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. 0x0:Not Supported, 0x1:Supported **/ uint8_t DDR3LASR; /** Offset 0x0052 - ScramblerSupport - Scrambler Support. + Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). $EN_DIS **/ uint8_t ScramblerSupport; /** Offset 0x0053 - ChannelHashMask - Channel Hash Mask. + Channel Hash Mask. 0x00(Default). **/ uint16_t ChannelHashMask; /** Offset 0x0055 - SliceHashMask - Slice Hash Mask. + Slice Hash Mask. 0x00(Default). **/ uint16_t SliceHashMask; /** Offset 0x0057 - InterleavedMode - Interleaved Mode. + Interleaved Mode. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ uint8_t InterleavedMode; /** Offset 0x0058 - ChannelsSlicesEnable - Channels Slices Enable. + Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ uint8_t ChannelsSlicesEnable; /** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. + Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ uint8_t MinRefRate2xEnable; /** Offset 0x005A - DualRankSupportEnable - Dual Rank Support Enable. + Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t DualRankSupportEnable; /** Offset 0x005B - RmtMode - Rank Margin Tool Mode. + Rank Margin Tool Mode. 0x00(Default). $EN_DIS **/ uint8_t RmtMode; /** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) **/ uint16_t MemorySizeLimit; /** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). **/ uint16_t LowMemoryMaxValue; /** Offset 0x0060 - DisableFastBoot - 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. + 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train of memory. $EN_DIS **/ uint8_t DisableFastBoot; /** Offset 0x0061 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). **/ uint16_t HighMemoryMaxValue; /** Offset 0x0063 - DIMM0SPDAddress - DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). **/ uint8_t DIMM0SPDAddress; /** Offset 0x0064 - DIMM1SPDAddress - DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). **/ uint8_t DIMM1SPDAddress; /** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). **/ uint8_t Ch0_RankEnable; /** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch0_DeviceWidth; /** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch0_DramDensity; /** Offset 0x0068 - Ch0_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). 0x03(Default). **/ uint8_t Ch0_Option; /** Offset 0x0069 - Ch0_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ uint8_t Ch0_OdtConfig; /** Offset 0x006A - Ch0_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\n Boolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch0_TristateClk1; /** Offset 0x006B - Ch0_Mode2N - [0] 2N Mode.\n Boolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch0_Mode2N; /** Offset 0x006C - Ch0_OdtLevels - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). **/ uint8_t Ch0_OdtLevels; /** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch1 rank. **/ uint8_t Ch1_RankEnable; /** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch1_DeviceWidth; /** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch1_DramDensity; /** Offset 0x0070 - Ch1_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B), 0x03(Default). **/ uint8_t Ch1_Option; /** Offset 0x0071 - Ch1_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ uint8_t Ch1_OdtConfig; /** Offset 0x0072 - Ch1_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch1_TristateClk1; /** Offset 0x0073 - Ch1_Mode2N - [0] 2N Mode.\nBoolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch1_Mode2N; /** Offset 0x0074 - Ch1_OdtLevels - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch1_OdtLevels; /** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch2 rank. **/ uint8_t Ch2_RankEnable; /** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch2_DeviceWidth; /** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch2_DramDensity; /** Offset 0x0078 - Ch2_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description.. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description.. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). 01:2KB (B). **/ uint8_t Ch2_Option; /** Offset 0x0079 - Ch2_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ uint8_t Ch2_OdtConfig; /** Offset 0x007A - Ch2_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch2_TristateClk1; /** Offset 0x007B - Ch2_Mode2N - [0] 2N Mode.\nBoolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch2_Mode2N; /** Offset 0x007C - Ch2_OdtLevels - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch2_OdtLevels; /** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. + NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). **/ uint8_t Ch3_RankEnable; /** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), 0x01:x16, 0x02:x32, 0x03:x64. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch3_DeviceWidth; /** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch3_DramDensity; /** Offset 0x0080 - Ch3_Option - [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description.. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description.. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - 2KB (B). **/ uint8_t Ch3_Option; /** Offset 0x0081 - Ch3_OdtConfig - [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. + ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. **/ uint8_t Ch3_OdtConfig; /** Offset 0x0082 - Ch3_TristateClk1 - [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. + Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ uint8_t Ch3_TristateClk1; /** Offset 0x0083 - Ch3_Mode2N - [0] 2N Mode.\nBoolean value. + 2N Mode. 0x00(Default). **/ uint8_t Ch3_Mode2N; /** Offset 0x0084 - Ch3_OdtLevels - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch3_OdtLevels; /** Offset 0x0085 - RmtCheckRun - [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. + RmtCheckRun: 0x00(Default). **/ uint8_t RmtCheckRun; @@ -486,28 +487,34 @@ struct FSP_M_CONFIG { uint8_t Ch3_Bit_swizzling[32]; /** Offset 0x0106 - RmtMarginCheckScaleHighThreshold - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. + RmtMarginCheckScaleHighThreshold. 0x0000(Default). **/ uint16_t RmtMarginCheckScaleHighThreshold; /** Offset 0x0108 - MsgLevelMask - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. + MsgLevelMask. 0x00000000(Default). **/ uint32_t MsgLevelMask; /** Offset 0x010C - FIT Table Pointer - FIT table pointer. + FIT table pointer. 0x00000000(Default). **/ uint32_t FitTablePtr; /** Offset 0x0110 - GPIO Table Pointer - GPIO table pointer to a BL_GPIO_PAD_INIT structure. + GPIO table pointer to a BL_GPIO_PAD_INIT structure. 0x00000000(Default). **/ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0114 +/** Offset 0x0114 - Enhance the port 8xh decoding + Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). + $EN_DIS **/ - uint8_t ReservedFspmUpd[60]; + uint8_t EnhancePort8xhDecoding; + +/** Offset 0x0115 +**/ + uint8_t ReservedFspmUpd[59]; } __attribute__((packed)); /** Fsp M Test Configuration @@ -538,6 +545,8 @@ struct FSP_M_RESTRICTED_CONFIG { #define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ +/** Fsp M UPD Configuration +**/ struct FSPM_UPD { /** Offset 0x0000 diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index f2f867b..2ada27f 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -41,76 +41,76 @@ are permitted provided that the following conditions are met: struct FSP_S_CONFIG { /** Offset 0x0020 - ActiveProcessorCores - Number of active cores. + Number of active cores. 0:Disable(Default), 1:Enable. **/ uint8_t ActiveProcessorCores; /** Offset 0x0021 - Disable Core1 - Disable/Enable Core1. + Disable/Enable Core1. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t DisableCore1; /** Offset 0x0022 - Disable Core2 - Disable/Enable Core2. + Disable/Enable Core2. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t DisableCore2; /** Offset 0x0023 - Disable Core3 - Disable/Enable Core3. + Disable/Enable Core3. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t DisableCore3; /** Offset 0x0024 - VMX Enable - Enable or Disable VMX. + Enable or Disable VMX. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t VmxEnable; /** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) **/ uint8_t ProcTraceMemSize; /** Offset 0x0026 - Enable Processor Trace - Enable or Disable Processor Trace feature. + Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t ProcTraceEnable; /** Offset 0x0027 - Eist - Enable or Disable Intel SpeedStep Technology. + Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t Eist; /** Offset 0x0028 - Boot PState - Boot PState with HFM or LFM. 0: HFM; 1: LFM. + Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. **/ uint8_t BootPState; /** Offset 0x0029 - CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable. + Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t EnableCx; /** Offset 0x002A - Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable. + Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t C1e; /** Offset 0x002B - Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t BiProcHot; /** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto. + Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. **/ uint8_t PkgCStateLimit; @@ -119,407 +119,1220 @@ struct FSP_S_CONFIG { uint8_t UnusedUpdSpace0; /** Offset 0x002E - C-State auto-demotion - C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3. + C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion to C1 and C3. **/ uint8_t CStateAutoDemotion; /** Offset 0x002F - C-State un-demotion - C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion. + C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. **/ uint8_t CStateUnDemotion; /** Offset 0x0030 - Max Core C-State - Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx. + Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). **/ uint8_t MaxCoreCState; /** Offset 0x0031 - Package C-State Demotion - Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable. + Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PkgCStateDemotion; /** Offset 0x0032 - Package C-State Un-demotion - Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable. + Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PkgCStateUnDemotion; /** Offset 0x0033 - Turbo Mode - Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable. + Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t TurboMode; -/** Offset 0x0034 +/** Offset 0x0034 - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. 0(Default). **/ - uint8_t UnusedUpdSpace1[12]; + uint8_t HdaVerbTableEntryNum; + +/** Offset 0x0035 - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. 0x00000000(Default). +**/ + uint32_t HdaVerbTablePtr; + +/** Offset 0x0039 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t HideP2sb; + +/** Offset 0x003A - IPU Enable/Disable + Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t IpuEn; + +/** Offset 0x003B - IMGU ACPI mode selection + 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + uint8_t IpuAcpiMode; + +/** Offset 0x003C - GttMmAdr + GttMmAdr structure for initialization. 0xBF000000(Default). +**/ + uint32_t GttMmAdr; + +/** Offset 0x0040 - GmAdr + GmAdr structure for initialization. 0xA0000000(Default). +**/ + uint32_t GmAdr; + +/** Offset 0x0044 - Enable ForceWake + Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t ForceWake; + +/** Offset 0x0045 - Enable PavpLock + Enable/disable PavpLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PavpLock; + +/** Offset 0x0046 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsFreqModify; + +/** Offset 0x0047 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsFreqReq; + +/** Offset 0x0048 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsVideoFreq; + +/** Offset 0x0049 - Enable PmLock + Enable/disable PmLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PmLock; + +/** Offset 0x004A - Enable DopClockGating + Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DopClockGating; + +/** Offset 0x004B - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UnsolicitedAttackOverride; + +/** Offset 0x004C - Enable WOPCMSupport + Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t WOPCMSupport; + +/** Offset 0x004D - Enable WOPCMSize + Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t WOPCMSize; + +/** Offset 0x004E - Enable PowerGating + Enable/disable PowerGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PowerGating; + +/** Offset 0x004F - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UnitLevelClockGating; + +/** Offset 0x0050 - Enable FastBoot + Enable/disable FastBoot. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t FastBoot; + +/** Offset 0x0051 - Enable DynSR + Enable/disable DynSR. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DynSR; + +/** Offset 0x0052 - Enable SaIpuEnable + Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SaIpuEnable; + +/** Offset 0x0053 - BMP Logo Data Size + BMP logo data buffer size. 0x00000000(Default). +**/ + uint32_t LogoSize; + +/** Offset 0x0057 - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. 0x00000000(Default). +**/ + uint32_t LogoPtr; + +/** Offset 0x005B - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. 0x00000000(Default). +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x005F - GT PM Support + Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x0060 - RC6(Render Standby) + Enable/Disable render standby support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t EnableRenderStandby; + +/** Offset 0x0061 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0062 - PAVP PR3 + Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PavpPr3; + +/** Offset 0x0063 - CdClock Frequency selection + 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + uint8_t CdClock; + +/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit + Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x0065 - Write Protection Support + Enable/disable Write Protection. 0:Disable, 1:Enable(Default). +**/ + uint8_t WriteProtectionEnable[5]; + +/** Offset 0x006A - Read Protection Support + Enable/disable Read Protection. 0:Disable, 1:Enable(Default). +**/ + uint8_t ReadProtectionEnable[5]; + +/** Offset 0x006F - Protected Range Limitation + The address of the upper limit of protection, 0x0FFFh(Default). +**/ + uint16_t ProtectedRangeLimit[5]; -/** Offset 0x0040 - HD-Audio I/O Buffer Ownership - Set HD-Audio I/O Buffer Ownership. +/** Offset 0x0079 - Protected Range Base + The base address of the upper limit of protection. 0x0000(Default). +**/ + uint16_t ProtectedRangeBase[5]; + +/** Offset 0x0083 - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t Gmm; + +/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk + Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingPgcbClkTrunk; + +/** Offset 0x0085 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSb; + +/** Offset 0x0086 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSbClkTrunk; + +/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition + Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSbClkPartition; + +/** Offset 0x0088 - GMM Clock Gating - Core + Enable/disable Core. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingCore; + +/** Offset 0x0089 - GMM Clock Gating - DMA + Enable/disable DMA. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingDma; + +/** Offset 0x008A - GMM Clock Gating - Register Access + Enable/disable Register Access. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingRegAccess; + +/** Offset 0x008B - GMM Clock Gating - Host + Enable/disable Host. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingHost; + +/** Offset 0x008C - GMM Clock Gating - Partition + Enable/disable Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingPartition; + +/** Offset 0x008D - Clock Gating - Trunk + Enable/disable Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingTrunk; + +/** Offset 0x008E - HD Audio Support + Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t HdaEnable; + +/** Offset 0x008F - HD Audio DSP Support + Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DspEnable; + +/** Offset 0x0090 - Azalia wake-on-ring + Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t Pme; + +/** Offset 0x0091 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. 0:Disable(Default), 1:Enable. 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers **/ uint8_t HdAudioIoBufferOwnership; -/** Offset 0x0041 +/** Offset 0x0092 - HD-Audio I/O Buffer Voltage + HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. + 0: 3.3V, 1: 1.8V +**/ + uint8_t HdAudioIoBufferVoltage; + +/** Offset 0x0093 - HD-Audio Virtual Channel Type + HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. + 0: VC0, 1: VC1 +**/ + uint8_t HdAudioVcType; + +/** Offset 0x0094 - HD-Audio Link Frequency + HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + uint8_t HdAudioLinkFrequency; + +/** Offset 0x0095 - HD-Audio iDisp-Link Frequency + HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + uint8_t HdAudioIDispLinkFrequency; + +/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode + HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. + 0: 2T, 1: 1T +**/ + uint8_t HdAudioIDispLinkTmode; + +/** Offset 0x0097 - HD-Audio Disp DMIC + HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. + 0: Disable, 1: 2ch array, 2: 4ch array **/ - uint8_t UnusedUpdSpace2[5]; + uint8_t DspEndpointDmic; -/** Offset 0x0046 - Enable SD controller - Enable/disable SD Card controller. +/** Offset 0x0098 - HD-Audio Bluetooth + Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SdcardEnabled; + uint8_t DspEndpointBluetooth; -/** Offset 0x0047 - Enable SDIO controller - Enable/disable SDIO controller. +/** Offset 0x0099 - HD-Audio I2S SHK + Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SdioEnabled; + uint8_t DspEndpointI2sSkp; -/** Offset 0x0048 - Enable eMMC controller - Enable/disable eMMC controller. +/** Offset 0x009A - HD-Audio I2S HP + Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t eMMCEnabled; + uint8_t DspEndpointI2sHp; -/** Offset 0x0049 - Enable SATA - Enable/disable SATA controller. +/** Offset 0x009B - HD-Audio Controller Power Gating + Enable/Disable HD-Audio Controller Power Gating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t EnableSata; + uint8_t AudioCtlPwrGate; -/** Offset 0x004A - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID +/** Offset 0x009C - HD-Audio ADSP Power Gating + Enable/Disable HD-Audio ADSP Power Gating. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t SataMode; + uint8_t AudioDspPwrGate; -/** Offset 0x004B - Aggressive SATA LPM Support - Enable SOC to aggressively enter link power state for SATA. +/** Offset 0x009D - HD-Audio CSME Memory Transfers + Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + uint8_t Mmt; + +/** Offset 0x009E - HD-Audio Host Memory Transfers + Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + uint8_t Hmt; + +/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SataSalpSupport; + uint8_t BiosCfgLockDown; -/** Offset 0x004C - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00A0 - HD-Audio Power Gating + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t SataPortsEnable[2]; + uint8_t HDAudioPwrGate; -/** Offset 0x004E - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00A1 - HD-Audio Clock Gatingn + Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t SataPortsDevSlp[2]; + uint8_t HDAudioClkGate; -/** Offset 0x0050 - Enable PCIE RP - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +/** Offset 0x00A2 - Bitmask of DSP Feature + Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation **/ - uint8_t PcieRootPortEn[6]; + uint32_t DspFeatureMask; -/** Offset 0x0056 - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules + Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation **/ - uint8_t PcieRpClkReqNumber[6]; + uint32_t DspPpModuleMask; -/** Offset 0x005C +/** Offset 0x00AA - Enable High Precision Timer + Enable/Disable Hpet. 0:Disable, 1:Enable(Default). + $EN_DIS **/ - uint8_t UnusedUpdSpace3[16]; + uint8_t Hpet; -/** Offset 0x006C - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00AB - Hpet Valid BDF Value + Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t PortUsb20Enable[8]; + uint8_t HpetBdfValid; -/** Offset 0x0074 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +/** Offset 0x00AC - Bus Number of Hpet + Completer ID of Bus Number of Hpet. Default = 0xFA(Default). **/ - uint8_t PortUsb30Enable[6]; + uint8_t HpetBusNumber; -/** Offset 0x007A - Enable XHCI SSIC ports - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. +/** Offset 0x00AD - Device Number of Hpet + Completer ID of Device Number of Hpet. 0x1F(Default). **/ - uint8_t SsicPortEnable[2]; + uint8_t HpetDeviceNumber; -/** Offset 0x007C - Enable SMBus - Enable/disable SMBus controller. +/** Offset 0x00AE - Function Number of Hpet + Completer ID of Function Number of Hpet. 0x00(Default). +**/ + uint8_t HpetFunctionNumber; + +/** Offset 0x00AF - Hpet Base Address + Hpet Base Address. 0xFED00000(Default). +**/ + uint32_t HpetBase; + +/** Offset 0x00B3 - IoApic Valid BDF Value + Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SmbusEnable; + uint8_t IoApicBdfValid; -/** Offset 0x007D - SC HDA Verb Table Entry Number - Number of Entries in Verb Table. +/** Offset 0x00B4 - Bus Number of IoApic + Completer ID of Bus Number of IoApic. 0xFA(Default). **/ - uint8_t HdaVerbTableEntryNum; + uint8_t IoApicBusNumber; -/** Offset 0x007E - SC HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. +/** Offset 0x00B5 - Device Number of IoApic + Completer ID of Device Number of IoApic. 0x0F(Default). **/ - uint32_t HdaVerbTablePtr; + uint8_t IoApicDeviceNumber; -/** Offset 0x0082 +/** Offset 0x00B6 - Function Number of IoApic + Completer ID of Function Number of IoApic. 0x00(Default). **/ - uint8_t UnusedUpdSpace4[14]; + uint8_t IoApicFunctionNumber; -/** Offset 0x0090 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. +/** Offset 0x00B7 - IOAPIC Entry 24-119 + Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t HideP2sb; + uint8_t IoApicEntry24_119; + +/** Offset 0x00B8 - IO APIC ID + This member determines IOAPIC ID. 0x01(Default). +**/ + uint8_t IoApicId; -/** Offset 0x0091 - Ufs Enable/Disable - Enable/Disable Ufs. +/** Offset 0x00B9 - IoApic Range + Define address bits 19:12 for the IOxAPIC range. 0x00(Default). +**/ + uint8_t IoApicRangeSelect; + +/** Offset 0x00BA - ISH Controller + Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t UfsEnabled; + uint8_t IshEnable; -/** Offset 0x0092 - IPU Enable/Disable - Enable/Disable IPU Device. +/** Offset 0x00BB - ISH Controller + Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t IpuEn; + uint8_t BiosInterface; -/** Offset 0x0093 - IMGU ACPI mode selection - 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device - 0:Disable, 1:IGFX Child device, 2:ACPI device +/** Offset 0x00BC - Bios LockDown Enable + Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint8_t IpuAcpiMode; + uint8_t BiosLock; -/** Offset 0x0094 - ResetSelect - ResetSelect. 0x6:warm reset; 0xE:cold reset +/** Offset 0x00BD - SPI EISS Status + Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). + $EN_DIS **/ - uint8_t ResetSelect; + uint8_t SpiEiss; -/** Offset 0x0095 - CRIDSettings - PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3 +/** Offset 0x00BE - BiosLock SWSMI Number + This member describes the SwSmi value for Bios Lock. 0xA9(Default). **/ - uint8_t CRIDSettings; + uint8_t BiosLockSwSmiNumber; -/** Offset 0x0096 - Enable HPET - Enable/disable HPET. +/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable + Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t Hpet; + uint8_t S0ixEnable; -/** Offset 0x0097 - Enable PCIE Clock Gating - Enable/disable PCIE Clock Gating.0:Enable;1:Disable +/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration + Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t I2cClkGateCfg[8]; + +/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration + Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t HsuartClkGateCfg[4]; + +/** Offset 0x00CC - LPSS SPI Clock Gating Configuration + Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t SpiClkGateCfg[3]; + +/** Offset 0x00CF - I2C Device 0 + Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c0Enable; + +/** Offset 0x00D0 - I2C Device 1 + Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c1Enable; + +/** Offset 0x00D1 - I2C Device 2 + Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c2Enable; + +/** Offset 0x00D2 - I2C Device 3 + Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c3Enable; + +/** Offset 0x00D3 - I2C Device 4 + Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c4Enable; + +/** Offset 0x00D4 - I2C Device 5 + Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c5Enable; + +/** Offset 0x00D5 - I2C Device 6 + Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c6Enable; + +/** Offset 0x00D6 - I2C Device 7 + Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c7Enable; + +/** Offset 0x00D7 - UART Device 0 + Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart0Enable; + +/** Offset 0x00D8 - UART Device 1 + Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart1Enable; + +/** Offset 0x00D9 - UART Device 2 + Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart2Enable; + +/** Offset 0x00DA - UART Device 3 + Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart3Enable; + +/** Offset 0x00DB - SPI UART Device 0 + Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi0Enable; + +/** Offset 0x00DC - SPI UART Device 1 + Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi1Enable; + +/** Offset 0x00DD - SPI UART Device 2 + Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi2Enable; + +/** Offset 0x00DE - UART Debug Bass Address + UART Debug Bass Address. 0x00000000(Default). +**/ + uint32_t Uart2KernelDebugBaseAddress; + +/** Offset 0x00E2 - OS Debug Feature + Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + uint8_t OsDbgEnable; + +/** Offset 0x00E3 - Exi Feature + Enable/Disable Exi Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + uint8_t ExiEnable; + +/** Offset 0x00E4 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). $EN_DIS **/ uint8_t PcieClockGatingDisabled; -/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode - Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable +/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t PcieRootPort8xhDecode; -/** Offset 0x0099 - PCIE 8xh Decode Port Index - PCIE 8xh Decode Port Index. +/** Offset 0x00E6 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. 0x00(Default). **/ uint8_t Pcie8xhDecodePortIndex; -/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write - Enable/disable PCIE root port peer memory write.0:Disable;1:Enable +/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PcieRootPortPeerMemoryWriteEnable; -/** Offset 0x009B - Enable SC Gaussian Mixture Models - Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable - $EN_DIS +/** Offset 0x00E8 - PCIE SWSMI Nubmer + This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ - uint8_t Gmm; + uint8_t PcieAspmSwSmiNumber; -/** Offset 0x009C - GttMmAdr - GttMmAdr structure for initialization. +/** Offset 0x00E9 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). **/ - uint32_t GttMmAdr; + uint8_t PcieRootPortEn[6]; + +/** Offset 0x00EF - Hide PCIE Root Port Configuration Space + Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpHide[6]; + +/** Offset 0x00F5 - PCIE Root Port Slot Implement + Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpSlotImplemented[6]; + +/** Offset 0x00FB - Hot Plug + PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpHotPlug[6]; + +/** Offset 0x0101 - PCIE PM SCI + Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpPmSci[6]; + +/** Offset 0x0107 - PCIE Root Port Extended Sync + Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpExtSync[6]; + +/** Offset 0x010D - Transmitter Half Swing + Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpTransmitterHalfSwing[6]; + +/** Offset 0x0113 - ACS + Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpAcsEnabled[6]; + +/** Offset 0x0119 - Clock Request Support + Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpClkReqSupported[6]; -/** Offset 0x00A0 +/** Offset 0x011F - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, 0x01, 0x02, 0x03. **/ - uint8_t UnusedUpdSpace5[96]; + uint8_t PcieRpClkReqNumber[6]; + +/** Offset 0x0125 - CLKREQ# Detection + Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. +**/ + uint8_t PcieRpClkReqDetect[6]; + +/** Offset 0x012B - Advanced Error Reporting + Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. +**/ + uint8_t AdvancedErrorReporting[6]; + +/** Offset 0x0131 - PME Interrupt + Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. +**/ + uint8_t PmeInterrupt[6]; + +/** Offset 0x0137 - URR + PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t UnsupportedRequestReport[6]; + +/** Offset 0x013D - FER + PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t FatalErrorReport[6]; + +/** Offset 0x0143 - NFER + PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t NoFatalErrorReport[6]; + +/** Offset 0x0149 - CER + PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t CorrectableErrorReport[6]; + +/** Offset 0x014F - SEFE + Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnFatalError[6]; + +/** Offset 0x0155 - SENFE + Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnNonFatalError[6]; + +/** Offset 0x015B - SECE + Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnCorrectableError[6]; + +/** Offset 0x0161 - PCIe Speed + Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. +**/ + uint8_t PcieRpSpeed[6]; + +/** Offset 0x0167 - Physical Slot Number + Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. +**/ + uint8_t PhysicalSlotNumber[6]; + +/** Offset 0x016D - CTO + Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpCompletionTimeout[6]; + +/** Offset 0x0173 - PTM Support + Enable/Diable PTM Support. 0:Disable(Default), 1:Enable. +**/ + uint8_t PtmEnable[6]; -/** Offset 0x0100 - Enable S0ix - Enable/disable S0ix.0:Disable;1:Enable +/** Offset 0x0179 - ASPM + PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, 4:Auto(Default). +**/ + uint8_t PcieRpAspm[6]; + +/** Offset 0x017F - L1 Substates + PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). +**/ + uint8_t PcieRpL1Substates[6]; + +/** Offset 0x0185 - PCH PCIe LTR + PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpLtrEnable[6]; + +/** Offset 0x018B - PCIE LTR Lock + PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpLtrConfigLock[6]; + +/** Offset 0x0191 - PME_B0_S5 Diable bit + PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t S0ix; + uint8_t PmeB0S5Dis; -/** Offset 0x0101 - GmAdr - GmAdr structure for initialization. +/** Offset 0x0192 - PCI Clock Run + This member describes whether or not the PCI ClockRun feature of SC should be enabled. 0:Disable(Default), 1:Enable. + $EN_DIS **/ - uint32_t GmAdr; + uint8_t PciClockRun; -/** Offset 0x0105 - Enable ForceWake - Enable/disable ForceWake Models.0:Disable;1:Enable +/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ForceWake; + uint8_t Timer8254ClkSetting; -/** Offset 0x0106 - Enable PavpLock - Enable/disable PavpLock.0:Disable;1:Enable +/** Offset 0x0194 - Chipset SATA + Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PavpLock; + uint8_t EnableSata; -/** Offset 0x0107 - Enable GraphicsFreqModify - Enable/disable GraphicsFreqModify.0:Disable;1:Enable +/** Offset 0x0195 - SATA Mode Selection + Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x0196 - Aggressive LPM Support + Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t GraphicsFreqModify; + uint8_t SataSalpSupport; -/** Offset 0x0108 - Enable GraphicsFreqReq - Enable/disable GraphicsFreqReq.0:Disable;1:Enable +/** Offset 0x0197 - SATA Power Optimization + Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsFreqReq; + uint8_t SataPwrOptEnable; -/** Offset 0x0109 - Enable GraphicsVideoFreq - Enable/disable GraphicsVideoFreq.0:Disable;1:Enable +/** Offset 0x0198 - eSATA Speed Limit + Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsVideoFreq; + uint8_t eSATASpeedLimit; + +/** Offset 0x0199 - SATA Speed Limit + SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). + 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) +**/ + uint8_t SpeedLimit; -/** Offset 0x010A - Enable PmLock - Enable/disable PmLock.0:Disable;1:Enable +/** Offset 0x019A - SATA Port + Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). +**/ + uint8_t SataPortsEnable[2]; + +/** Offset 0x019C - SATA Port DevSlp + Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsDevSlp[2]; + +/** Offset 0x019E - SATA Port HotPlug + Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsHotPlug[2]; + +/** Offset 0x01A0 - Mechanical Presence Switch + Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires hardware support. 0:Disable, 1:Enable(Default). +**/ + uint8_t SataPortsInterlockSw[2]; + +/** Offset 0x01A2 - External SATA Ports + Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsExternal[2]; + +/** Offset 0x01A4 - Spin Up Device + Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsSpinUp[2]; + +/** Offset 0x01A6 - SATA Solid State + Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard Disk Drive(Default), 1:Solid State Drive. +**/ + uint8_t SataPortsSolidStateDrive[2]; + +/** Offset 0x01A8 - DITO Configuration + Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsEnableDitoConfig[2]; + +/** Offset 0x01AA - DM Value + DM Value. 0:Minimum, 0x0F:Maximum(Default). +**/ + uint8_t SataPortsDmVal[2]; + +/** Offset 0x01AC - DITO Value + DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). +**/ + uint16_t SataPortsDitoVal[2]; + +/** Offset 0x01B0 - Subsystem Vendor ID + Subsystem Vendor ID. 0x8086(Default). +**/ + uint16_t SubSystemVendorId; + +/** Offset 0x01B2 - Subsystem ID + Subsystem ID. 0x7270(Default). +**/ + uint16_t SubSystemId; + +/** Offset 0x01B4 - PM Base Address + PM Base Address. 0x400(Default). +**/ + uint16_t AcpiBase; + +/** Offset 0x01B6 - PMC Base Address + PMC Base Address. 0xD10010000(Default). +**/ + uint32_t PmcBase; + +/** Offset 0x01BA - P2SB Base Address + P2SB Base Address. 0xD0000000(Default). +**/ + uint32_t P2sbBase; + +/** Offset 0x01BE - CRIDSettings + PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. +**/ + uint8_t CRIDSettings; + +/** Offset 0x01BF - ResetSelect + ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. +**/ + uint8_t ResetSelect; + +/** Offset 0x01C0 - SD Card Support (D27:F0) + Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PmLock; + uint8_t SdcardEnabled; -/** Offset 0x010B +/** Offset 0x01C1 - SeMMC Support (D28:F0) + Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t eMMCEnabled; + +/** Offset 0x01C2 - eMMC Max Speed + Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. + 0:HS400, 1: HS200, 2:DDR50 **/ - uint8_t UnusedUpdSpace6[5]; + uint8_t eMMCHostMaxSpeed; -/** Offset 0x0110 - Enable DopClockGating - Enable/disable DopClockGating.0:Disable;1:Enable +/** Offset 0x01C3 - UFS Support (D29:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DopClockGating; + uint8_t UfsEnabled; -/** Offset 0x0111 - Enable UnsolicitedAttackOverride - Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable +/** Offset 0x01C4 - SDIO Support (D30:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t UnsolicitedAttackOverride; + uint8_t SdioEnabled; -/** Offset 0x0112 - Enable WOPCMSupport - Enable/disable WOPCMSupport.0:Disable;1:Enable +/** Offset 0x01C5 - GPP Lock Feature + Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t WOPCMSupport; + uint8_t GppLock; -/** Offset 0x0113 - Enable WOPCMSize - Enable/disable WOPCMSize.0:Disable;1:Enable +/** Offset 0x01C6 - Serial IRQ + Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t WOPCMSize; + uint8_t SirqEnable; -/** Offset 0x0114 - Enable PowerGating - Enable/disable PowerGating.0:Disable;1:Enable +/** Offset 0x01C7 - Serial IRQ Mode + Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. $EN_DIS **/ - uint8_t PowerGating; + uint8_t SirqMode; -/** Offset 0x0115 - Enable UnitLevelClockGating - Enable/disable UnitLevelClockGating.0:Disable;1:Enable +/** Offset 0x01C8 - Start Frame Pulse Width + Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. $EN_DIS **/ - uint8_t UnitLevelClockGating; + uint8_t StartFramePulse; -/** Offset 0x0116 - Enable FastBoot - Enable/disable FastBoot.0:Disable;1:Enable +/** Offset 0x01C9 - Enable SMBus + Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t FastBoot; + uint8_t SmbusEnable; -/** Offset 0x0117 - Enable DynSR - Enable/disable DynSR.0:Disable;1:Enable +/** Offset 0x01CA - SMBus ARP Support + Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DynSR; + uint8_t ArpEnable; + +/** Offset 0x01CB - SMBus Base Address (IO space) + SMBUS Base Address (IO space). 0xEFA0(Default). +**/ + uint16_t SmbusIoBase; + +/** Offset 0x01CD - SMBus Table Elements + The number of elements in the Reserved SMBus Address Table. 0x0080(Default). +**/ + uint16_t NumRsvdSmbusAddresses; + +/** Offset 0x01CF - Reserved SMBus Address Table + Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). +**/ + uint8_t RsvdSmbusAddressTable[128]; -/** Offset 0x0118 - Enable SaIpuEnable - Enable/disable SaIpuEnable.0:Disable;1:Enable +/** Offset 0x024F - XHCI Disable Compliance Mode + Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. $EN_DIS **/ - uint8_t SaIpuEnable; + uint8_t DisableComplianceMode; -/** Offset 0x0119 - Enable VtdEnable - Enable/disable VtdEnable.0:Disable;1:Enable +/** Offset 0x0250 - USB Per-Port Control + Control each of the USB ports (0~3) enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t VtdEnable; + uint8_t UsbPerPortCtl; -/** Offset 0x011A - BMP Logo Data Size - BMP logo data buffer size. +/** Offset 0x0251 - xHCI Mode + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default), 3:SmartAuto. + $EN_DIS **/ - uint32_t LogoSize; + uint8_t Usb30Mode; -/** Offset 0x011E - BMP Logo Data Pointer - BMP logo data pointer to a BMP format buffer. +/** Offset 0x0252 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). **/ - uint32_t LogoPtr; + uint8_t PortUsb20Enable[8]; -/** Offset 0x0122 - Graphics Configuration Data Pointer - Graphics configuration data used for initialization. +/** Offset 0x025A - USB20 Over Current Pin + Over Current Pin number of USB 2.0 Port. 0x00(Default). **/ - uint32_t GraphicsConfigPtr; + uint8_t PortUs20bOverCurrentPin[8]; -/** Offset 0x0126 - GT PM Support - Enable/Disable GT power management support. +/** Offset 0x0262 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). +**/ + uint8_t PortUsb30Enable[6]; + +/** Offset 0x0268 - USB20 Over Current Pin + Over Current Pin number of USB 3.0 Port. 0x01(Default). +**/ + uint8_t PortUs30bOverCurrentPin[6]; + +/** Offset 0x026E - XDCI Support + Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. $EN_DIS **/ - uint8_t PmSupport; + uint8_t UsbOtg; -/** Offset 0x0127 - RC6(Render Standby) - Enable/Disable render standby support. +/** Offset 0x026F - Enable XHCI HSIC Support + Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t EnableRenderStandby; + uint8_t HsicSupportEnable; -/** Offset 0x0128 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). +/** Offset 0x0270 - Enable XHCI SSIC Support + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. 0x00(Default). +**/ + uint8_t SsicPortEnable[2]; + +/** Offset 0x0272 - SSIC Dlane PowerGating + Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PavpEnable; + uint16_t DlanePwrGating; -/** Offset 0x0129 - PAVP PR3 - Enable/Disable PAVP PR3 +/** Offset 0x0274 - VT-d + Enable/Disable VT-d. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PavpPr3; + uint8_t VtdEnable; -/** Offset 0x012A - CdClock Frequency selection - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +/** Offset 0x0275 - HDAudio Delay Timer + The delay timer after Azalia reset. 0x012C(Default). **/ - uint8_t CdClock; + uint16_t ResetWaitTimer; -/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit - Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit +/** Offset 0x0277 - SMI Lock bit + Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PeiGraphicsPeimInit; + uint8_t LockDownGlobalSmi; -/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock +/** Offset 0x0278 - RTC Lock Bits + Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t Timer8254ClkSetting; + uint8_t RtcLock; + +/** Offset 0x0279 - XHCI SSIC RATE + Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. +**/ + uint8_t SsicRate[2]; + +/** Offset 0x027B - SATA Test Mode Selection + Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SataTestMode; + +/** Offset 0x027C - SMBus Dynamic Power Gating + Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint16_t DynamicPowerGating; + +/** Offset 0x027E - Max Snoop Latency + Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). +**/ + uint16_t PcieRpLtrMaxSnoopLatency[6]; + +/** Offset 0x028A - Snoop Latency Override + Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + uint8_t PcieRpSnoopLatencyOverrideMode[6]; + +/** Offset 0x0290 - Snoop Latency Value + LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + uint16_t PcieRpSnoopLatencyOverrideValue[6]; + +/** Offset 0x029C - Snoop Latency Multiplier + LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + uint8_t PcieRpSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02A2 - Max Non-Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). +**/ + uint16_t PcieRpLtrMaxNonSnoopLatency[6]; -/** Offset 0x012D +/** Offset 0x02AE - Non Snoop Latency Override + Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ - uint8_t ReservedFspsUpd[211]; + uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; + +/** Offset 0x02B4 - Non Snoop Latency Value + LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + uint16_t PcieRpNonSnoopLatencyOverrideValue[6]; + +/** Offset 0x02C0 - Non Snoop Latency Multiplier + LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale + Specifies scale used for slot power limit value. 0x00(Default). +**/ + uint8_t PcieRpSlotPowerLimitScale[6]; + +/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value + Specifies upper limit on power supplie by slot. 0x00(Default). +**/ + uint8_t PcieRpSlotPowerLimitValue[6]; + +/** Offset 0x02D2 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize(Default), 1: Skip + $EN_DIS +**/ + uint8_t SkipMpInit; + +/** Offset 0x02D3 +**/ + uint8_t ReservedFspsUpd[45]; } __attribute__((packed)); /** Fsp S Test Configuration **/ struct FSP_S_TEST_CONFIG { -/** Offset 0x0200 +/** Offset 0x0300 **/ uint32_t Signature; -/** Offset 0x0204 +/** Offset 0x0304 **/ uint8_t ReservedFspsTestUpd[12]; } __attribute__((packed)); @@ -528,17 +1341,19 @@ struct FSP_S_TEST_CONFIG { **/ struct FSP_S_RESTRICTED_CONFIG { -/** Offset 0x0210 +/** Offset 0x0310 **/ uint32_t Signature; -/** Offset 0x0214 +/** Offset 0x0314 **/ uint8_t ReservedFspsRestrictedUpd[12]; } __attribute__((packed)); #define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +/** Fsp S UPD Configuration +**/ struct FSPS_UPD { /** Offset 0x0000 @@ -549,15 +1364,15 @@ struct FSPS_UPD { **/ struct FSP_S_CONFIG FspsConfig; -/** Offset 0x0200 +/** Offset 0x0300 **/ struct FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0210 +/** Offset 0x0310 **/ struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; -/** Offset 0x0220 +/** Offset 0x0320 **/ uint16_t UpdTerminator; } __attribute__((packed));

1 0

Patch merged into coreboot/master: vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in comment
by gerrit＠coreboot.org 31 Mar '16

31 Mar '16

the following patch was just integrated into master: commit 7454bdf3e28bce0e4bce597885cc69f6a5114f75 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 15 10:47:50 2013 +0100 vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in comment The typo is not present anymore in Family 16h (Kabini), so fix it for the older families (Family 10h, 12h, 14h, 15h, 15h Trinity) too using the command below. $ git grep -l ' ne ' src/vendorcode/amd/agesa | xargs sed -i 's/ ne / be /g' Change-Id: I9cb419251eeec79925f48a5832fac339d40f01d1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/5543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/5543 for details. -gerrit

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: signal that FSP components are loaded
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14211 -gerrit commit 2dd9fcf665c422970483905579fc5ea6d3bbb5f9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 12:48:30 2016 -0500 drivers/intel/fsp2_0: signal that FSP components are loaded In order for the platform code to handle situations where special actions are required after a piece of code is loaded use arch_segment_loaded() to signal to the platform code that the component is fully loaded into memory. Change-Id: I119cfc9913f15eb4968fe5bf6a56589e2c53f2d1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp2_0/util.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index a234a7c..c4fe8dc 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -17,6 +17,7 @@ #include <fsp/util.h> #include <lib.h> #include <memrange.h> +#include <program_loading.h> #include <string.h> static bool looks_like_fsp_header(const uint8_t *raw_hdr) @@ -130,5 +131,8 @@ enum cb_err fsp_load_binary(struct fsp_header *hdr, if (rdev_readat(&file_data, (void *)hdr->image_base, 0, hdr->image_size) < 0) return CB_ERR; + /* Signal that FSP component has been loaded. */ + arch_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); + return CB_SUCCESS; }

1 0

Patch set updated for coreboot: soc/intel/apollolake: use CAR code coherency for all CAR stages
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14210 -gerrit commit fa0913fde1b676de9cc31cd3091c48c4da2636f7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 11:38:13 2016 -0500 soc/intel/apollolake: use CAR code coherency for all CAR stages The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image is flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/bootblock/bootblock.c | 9 ------- src/soc/intel/apollolake/car.c | 33 ++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 41ac847..70ab515 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c +bootblock-y += car.c bootblock-y += gpio.c bootblock-y += mmap_boot.c bootblock-y += placeholders.c @@ -18,6 +19,7 @@ bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += placeholders.c +romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 4ea3f70..a9258e1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -12,7 +12,6 @@ #include <arch/cpu.h> #include <bootblock_common.h> #include <device/pci.h> -#include <program_loading.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/northbridge.h> @@ -36,14 +35,6 @@ void asmlinkage bootblock_c_entry(void) main(); } -void platform_prog_run(struct prog *prog) -{ - /* Flush L1D cache to L2 */ - msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= (1 << 8); - wrmsr(MSR_POWER_MISC, msr); -} - void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c new file mode 100644 index 0000000..7646865 --- /dev/null +++ b/src/soc/intel/apollolake/car.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <program_loading.h> +#include <soc/cpu.h> + +/* + * This file supports the necessary hoops one needs to jump through since + * early FSP component and early stages are running from cache-as-ram. + */ + +static void flush_l1d_to_l2(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= (1 << 8); + wrmsr(MSR_POWER_MISC, msr); +} + +void platform_prog_run(struct prog *prog) +{ + /* Flush L1D cache to L2 */ + flush_l1d_to_l2(); +}

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Patch set updated for coreboot: soc/intel/apollolake: use platform_segment_loaded() for CAR coherency
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14215 -gerrit commit 721019cdc709d2af21a67b732b6f691f0c34f983 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 14:00:47 2016 -0500 soc/intel/apollolake: use platform_segment_loaded() for CAR coherency Instead of using arch_segment_loaded() implement platform_segment_loaded() so as not to tangle the notion of arch and the chipset. Lastly, add a TODO to allow filtering of the L1D to L2 flush depending on the region loaded. Change-Id: I52e7cd2ae6e2d95f21bdd2fe1a471a10565309cb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/car.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index c49d7ef..b0a5b45 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -26,8 +26,10 @@ static void flush_l1d_to_l2(void) wrmsr(MSR_POWER_MISC, msr); } -void arch_segment_loaded(uintptr_t start, size_t size, int flags) +void platform_segment_loaded(uintptr_t start, size_t size, int flags) { + /* TODO: filter on address to see if L1D flushing required. */ + /* Flush L1D cache to L2 on final segment loaded */ if (flags & SEG_FINAL) flush_l1d_to_l2();

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Patch set updated for coreboot: lib/prog_loading: introduce prog_segment_loaded()
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14214 -gerrit commit 68075825335d9f15fd9bdf15ca7ba32d0078f379 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 13:49:00 2016 -0500 lib/prog_loading: introduce prog_segment_loaded() In order to not muddle arch vs chipset implementations provide a generic prog_segment_loaded() which calls platform_segment_loaded() and arch_segment_loaded() in that order. This allows the arch variants to live in src/arch while the chipset/platform code can implement their own. Change-Id: I17b6497219ec904d92bd286f18c9ec96b2b7af25 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/postcar_loader.c | 2 +- src/drivers/intel/fsp2_0/util.c | 2 +- src/include/program_loading.h | 11 +++++++++-- src/lib/cbfs.c | 2 +- src/lib/prog_ops.c | 12 ++++++++++++ src/lib/rmodule.c | 2 +- src/lib/selfboot.c | 2 +- 7 files changed, 26 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index eba90d4..cc1d460 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -115,7 +115,7 @@ void run_postcar_phase(struct postcar_frame *pcf) * Signal to rest of system that another update was made to the * postcar program prior to running it. */ - arch_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), + prog_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), SEG_FINAL); prog_run(&prog); diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index c4fe8dc..743bc9a 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -132,7 +132,7 @@ enum cb_err fsp_load_binary(struct fsp_header *hdr, return CB_ERR; /* Signal that FSP component has been loaded. */ - arch_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); + prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); return CB_SUCCESS; } diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 8ac73dd..42addb8 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -37,8 +37,15 @@ enum prog_type { PROG_BL32, }; -/* Called for each segment of a program loaded. The SEG_FINAL flag will be - * set on the last segment loaded. */ +/* + * prog_segment_loaded() is called for each segment of a program loaded. The + * SEG_FINAL flag will be set on the last segment loaded. The following two + * functions, platform_segment_loaded() and arch_segment_loaded(), are called + * in that order within prog_segment_loaded(). In short, rely on + * prog_segment_loaded() to perform the proper dispatch sequence. + */ +void prog_segment_loaded(uintptr_t start, size_t size, int flags); +void platform_segment_loaded(uintptr_t start, size_t size, int flags); void arch_segment_loaded(uintptr_t start, size_t size, int flags); /* Return true if arch supports bounce buffer. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 82bfa2d..e1626d7 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -206,7 +206,7 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Clear area not covered by file. */ memset(&load[fsize], 0, stage.memlen - fsize); - arch_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); + prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); out: prog_set_area(pstage, load, stage.memlen); diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c index 67bdcc0..bc889fc 100644 --- a/src/lib/prog_ops.c +++ b/src/lib/prog_ops.c @@ -17,6 +17,18 @@ #include <program_loading.h> /* For each segment of a program loaded this function is called*/ +void prog_segment_loaded(uintptr_t start, size_t size, int flags) +{ + platform_segment_loaded(start, size, flags); + arch_segment_loaded(start, size, flags); +} + +void __attribute__ ((weak)) platform_segment_loaded(uintptr_t start, + size_t size, int flags) +{ + /* do nothing */ +} + void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size, int flags) { diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 9825e6a..7043157 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -197,7 +197,7 @@ int rmodule_load(void *base, struct rmodule *module) return -1; rmodule_clear_bss(module); - arch_segment_loaded((uintptr_t)module->location, + prog_segment_loaded((uintptr_t)module->location, rmodule_memory_size(module), SEG_FINAL); return 0; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 7d3e2dd..23eda14 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -452,7 +452,7 @@ static int load_self_segments( * Each architecture can perform additonal operations * on the loaded segment */ - arch_segment_loaded((uintptr_t)dest, ptr->s_memsz, + prog_segment_loaded((uintptr_t)dest, ptr->s_memsz, last_non_empty == ptr ? SEG_FINAL : 0); } }

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Patch set updated for coreboot: arch/x86: notify the system when the postcar parameter was updated
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14213 -gerrit commit 040b3369ba7927f16c4f57d960e551b7ba92f1e9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 13:36:33 2016 -0500 arch/x86: notify the system when the postcar parameter was updated While rmodule_load() calls arch_segment_loaded() when it's done loading any pieces of code which further modify it, like changing parameters within the program itself, need to notify the rest of the system. Change-Id: Ia3374b58488120ba6279592a77d7f9c6217f1215 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/postcar_loader.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 580cc45..eba90d4 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -111,5 +111,12 @@ void run_postcar_phase(struct postcar_frame *pcf) *(uintptr_t *)rsl.params = pcf->stack; + /* + * Signal to rest of system that another update was made to the + * postcar program prior to running it. + */ + arch_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), + SEG_FINAL); + prog_run(&prog); }

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Patch set updated for coreboot: soc/intel/apollolake: use arch_segment_loaded() for CAR code coherency
by Aaron Durbin 31 Mar '16

31 Mar '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14212 -gerrit commit 942a9ff655ccc823149f0c5021bab8e7a1a1cb2b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 31 13:26:46 2016 -0500 soc/intel/apollolake: use arch_segment_loaded() for CAR code coherency Instead of using platform_prog_run() for flushing programs from L1D to L2 for code coherency purposes use arch_segment_loaded() instead as that it's primary purpose. The arch_segment_loaded() is called within the infrastructure at the appropriate places when loading programs. Therefore use that to perform the L1D flush instead of when something is just about to run. Change-Id: Ib0a6be6f676dcf2c946ef5702471af65d89133e9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/car.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 7646865..c49d7ef 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -26,8 +26,9 @@ static void flush_l1d_to_l2(void) wrmsr(MSR_POWER_MISC, msr); } -void platform_prog_run(struct prog *prog) +void arch_segment_loaded(uintptr_t start, size_t size, int flags) { - /* Flush L1D cache to L2 */ - flush_l1d_to_l2(); + /* Flush L1D cache to L2 on final segment loaded */ + if (flags & SEG_FINAL) + flush_l1d_to_l2(); }

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix revision mask for DR processors
by Timothy Pearson 31 Mar '16

31 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14216 -gerrit commit 341b23fc4d6bbeba5f68abc28e484ca7ad8f0f0a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 31 15:25:27 2016 -0500 nb/amd/mct_ddr3: Fix revision mask for DR processors The revision mask for all DR-* series processors was incorrectly set to only include the DR-B revision mask. Include all DR-* series prcessors in the DR_ALL revision mask. Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE) --- src/northbridge/amd/amdmct/amddefs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9193a04..bbdd2ed 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -67,7 +67,7 @@ #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) -#define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))

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coreboot-gerrit March 2016