coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: Makefile.inc: Align paths in CBFS add messages
by gerrit＠coreboot.org 30 Sep '15

30 Sep '15

the following patch was just integrated into master: commit 16fa8823f8289b74f575243cea277dc8743fd024 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Sep 25 09:18:43 2015 +0200 Makefile.inc: Align paths in CBFS add messages Building coreboot with the SeaBIOS or FILO payload selected, their config and revision are added to CBFS. ``` Creating out/bios.bin.elf CBFS coreboot.rom PAYLOAD payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA) CONFIG .config REVISION build.h CONFIG payloads/external/SeaBIOS/seabios/.config REVISION payloads/external/SeaBIOS/seabios/out/version.c CBFSPRINT coreboot.rom ``` Align the path of the payload config by removing one space. Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11710 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11710 for details. -gerrit

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Patch merged into coreboot/master: chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
by gerrit＠coreboot.org 30 Sep '15

30 Sep '15

the following patch was just integrated into master: commit 3faea59e26bc535f0b1827a2249e36abf2d08f6a Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:44:56 2015 +0200 chromeos: vboot_common: Avoid code duplication when grabbing the handoff info vboot_handoff_flag was duplicating the logic to grab the handoff info, that is already made available with vboot_get_handoff_info. This uses vboot_get_handoff_info in vboot_handoff_flag instead. Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11498 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11498 for details. -gerrit

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Patch set updated for coreboot: Makefile.inc: Align paths in CBFS add messages
by Paul Menzel 30 Sep '15

30 Sep '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11710 -gerrit commit 1b6e5bd33f4d163946767577bfadda9743b2d607 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Sep 25 09:18:43 2015 +0200 Makefile.inc: Align paths in CBFS add messages Building coreboot with the SeaBIOS or FILO payload selected, their config and revision are added to CBFS. ``` Creating out/bios.bin.elf CBFS coreboot.rom PAYLOAD payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA) CONFIG .config REVISION build.h CONFIG payloads/external/SeaBIOS/seabios/.config REVISION payloads/external/SeaBIOS/seabios/out/version.c CBFSPRINT coreboot.rom ``` Align the path of the payload config by removing one space. Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index ac6ce0b..3c4848e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -659,7 +659,7 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) endif endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(PAYLOAD_CONFIG)\n" + @printf " CONFIG $(PAYLOAD_CONFIG)\n" if [ -f "$(PAYLOAD_CONFIG)" ]; then \ $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_CONFIG)" -n payload_config -t raw; \ fi

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Patch set updated for coreboot: cbmem: add coreboot table records for each cbmem entry
by Aaron Durbin 30 Sep '15

30 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757 -gerrit commit 881780957aa9a925f6f81183e77d3bcff3d29f87 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:26:54 2015 -0500 cbmem: add coreboot table records for each cbmem entry In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++ src/include/cbmem.h | 4 +-- src/include/imd.h | 16 +++++++++ src/lib/coreboot_table.c | 3 ++ src/lib/imd.c | 44 +++++++++++++++++++++++ src/lib/imd_cbmem.c | 43 ++++++++++++++++++++-- 6 files changed, 119 insertions(+), 4 deletions(-) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 2ed4d7f..5e0c87c 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -308,6 +308,19 @@ struct lb_boot_media_params { uint64_t boot_media_size; }; +/* + * There can be more than one of these records as there is one per cbmem entry. + */ +#define LB_TAG_CBMEM_ENTRY 0x0031 +struct lb_cbmem_entry { + uint32_t tag; + uint32_t size; + + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 60de5a7..b34cf06 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,7 @@ #ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> +#include <boot/coreboot_tables.h> struct cbmem_entry; @@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery); void cbmem_run_init_hooks(int is_recovery); void cbmem_fail_resume(void); -#ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); -#endif /* __PRE_RAM__ */ +void cbmem_add_records_to_cbtable(struct lb_header *header); #if ENV_RAMSTAGE #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ diff --git a/src/include/imd.h b/src/include/imd.h index a444b4f..b373ab5 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); /* Returns pointer to region described by entry or NULL on failure. */ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); +/* Returns id for the imd entry. */ +uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry); + /* Attempt to remove entry from imd. */ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); @@ -136,6 +139,13 @@ struct imd_lookup { int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, size_t size); +struct imd_cursor; +/* Initialize an imd_cursor object to walk the IMD entries. */ +int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor); + +/* Retrieve the next imd entry the cursor is referencing. Returns NULL when + * no more entries exist. */ +const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor); /* * The struct imd is a handle for working with an in-memory directory. @@ -152,4 +162,10 @@ struct imd { struct imdr sm; }; +struct imd_cursor { + size_t current_imdr; + size_t current_entry; + const struct imdr *imdr[2]; +}; + #endif /* _IMD_H_ */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6859bf2..1bd356d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -517,6 +517,9 @@ unsigned long write_coreboot_table( lb_boot_media_params(head); + /* Add all cbmem entries into the coreboot tables. */ + cbmem_add_records_to_cbtable(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 612e3f1..67a76a4 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) return imdr_entry_at(imdr, entry); } +uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry) +{ + return entry->id; +} + int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry) { struct imd_root *r; @@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, return 0; } + +int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor) +{ + if (imd == NULL || cursor == NULL) + return -1; + + memset(cursor, 0, sizeof(*cursor)); + + cursor->imdr[0] = &imd->lg; + cursor->imdr[1] = &imd->sm; + + return 0; +} + +const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor) +{ + struct imd_root *r; + const struct imd_entry *e; + + if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr)) + return NULL; + + r = imdr_root(cursor->imdr[cursor->current_imdr]); + + if (r == NULL) + return NULL; + + if (cursor->current_entry >= r->num_entries) { + /* Try next imdr. */ + cursor->current_imdr++; + cursor->current_entry = 0; + return imd_cursor_next(cursor); + } + + e = &r->entries[cursor->current_entry]; + cursor->current_entry++; + + return e; +} diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index fa65334..d60acc9 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } -#if ENV_RAMSTAGE void cbmem_add_bootmem(void) { void *base = NULL; @@ -277,10 +276,50 @@ void cbmem_add_bootmem(void) bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE); } +#if ENV_RAMSTAGE +/* + * -fdata-sections doesn't work so well on read only strings. They all + * get put in the same section even though those strings may never be + * referenced in the final binary. + */ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup)); } -#endif /* __PRE_RAM__ */ +#endif + +void cbmem_add_records_to_cbtable(struct lb_header *header) +{ + struct imd_cursor cursor; + struct imd *imd; + + imd = cbmem_get_imd(); + + if (imd_cursor_init(imd, &cursor)) + return; + + while (1) { + const struct imd_entry *e; + struct lb_cbmem_entry *lbe; + uint32_t id; + + e = imd_cursor_next(&cursor); + + if (e == NULL) + break; + + id = imd_entry_id(imd, e); + /* Don't add these metadata entries. */ + if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) + continue; + + lbe = (struct lb_cbmem_entry *)lb_new_record(header); + lbe->tag = LB_TAG_CBMEM_ENTRY; + lbe->size = sizeof(*lbe); + lbe->address = (uintptr_t)imd_entry_at(imd, e); + lbe->entry_size = imd_entry_size(imd, e); + lbe->id = id; + } +}

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Patch set updated for coreboot: util/cbmem: remove duplicated cbmem data structure logic.
by Aaron Durbin 30 Sep '15

30 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758 -gerrit commit 55525d89e91fb82177e875099923452d9b429213 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:33:01 2015 -0500 util/cbmem: remove duplicated cbmem data structure logic. The cbmem utility shouldn't be using the intra coreboot data structures for obtaining the produced data/information. Instead use the newly added cbmem records in the coreboot tables for pulling out the data one wants by using the generic indexing of coreboot table entries. BUG=chrome-os-partner:43731 BRANCH=None TEST=Interrogated cbmem table of contents with updated code. Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c --- util/cbmem/cbmem.c | 203 +++++++++++++++++++++-------------------------------- 1 file changed, 80 insertions(+), 123 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 74cb52d..3e4b8a0 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -60,8 +60,8 @@ static int verbose = 0; /* File handle used to access /dev/mem */ static int mem_fd; -/* IMD root pointer location */ -static uint64_t rootptr = 0; +static uint64_t lbtable_address; +static size_t lbtable_size; /* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case @@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size) return v; } -static void *map_memory(u64 physical) +static void *map_lbtable(void) { - return map_memory_size(physical, MAP_BYTES); + if (lbtable_address == 0 || lbtable_size == 0) { + fprintf(stderr, "No coreboot table area found!\n"); + return NULL; + } + + return map_memory_size(lbtable_address, lbtable_size); +} + +static void unmap_lbtable(void) +{ + unmap_memory(); +} + +/* Find the first cbmem entry filling in the details. */ +static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size) +{ + uint8_t *table; + size_t offset; + int ret = -1; + + table = map_lbtable(); + + if (table == NULL) + return -1; + + offset = 0; + + while (offset < lbtable_size) { + struct lb_record *lbr; + struct lb_cbmem_entry *lbe; + + lbr = (void *)(table + offset); + offset += lbr->size; + + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; + + lbe = (void *)lbr; + if (lbe->id != id) + continue; + + *addr = lbe->address; + *size = lbe->entry_size; + ret = 0; + break; + } + + unmap_lbtable(); + return ret; } /* @@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size) found = 1; debug("Found!\n"); + /* Keep reference to lbtable. */ + lbtable_address = address; + lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh); + lbtable_size = lbh->table_bytes; + for (j = 0; j < lbh->table_bytes; j += lbr_p->size) { lbr_p = (struct lb_record*) ((char *)lbtable + j); debug(" coreboot table entry 0x%02x\n", lbr_p->tag); @@ -692,44 +745,6 @@ static void dump_cbmem_hex(void) hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); } -/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ -#define DYN_CBMEM_ALIGN_SIZE (4096) -#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define CBMEM_POINTER_MAGIC 0xc0389481 -#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) - -struct cbmem_root_pointer { - uint32_t magic; - /* Relative to upper limit/offset. */ - int32_t root_offset; -} __attribute__((packed)); - -struct dynamic_cbmem_entry { - uint32_t magic; - int32_t start_offset; - uint32_t size; - uint32_t id; -} __attribute__((packed)); - -struct cbmem_root { - uint32_t max_entries; - uint32_t num_entries; - uint32_t flags; - uint32_t entry_align; - int32_t max_offset; - struct dynamic_cbmem_entry entries[0]; -} __attribute__((packed)); - -#define CBMEM_MAGIC 0x434f5245 -#define MAX_CBMEM_ENTRIES 16 - -struct cbmem_entry { - uint32_t magic; - uint32_t id; - uint64_t base; - uint64_t size; -} __attribute__((packed)); - struct cbmem_id_to_name { uint32_t id; const char *name; @@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) printf(" %08" PRIx64 "\n", size); } -static void dump_static_cbmem_toc(struct cbmem_entry *entries) +static void dump_cbmem_toc(void) { int i; + uint8_t *table; + size_t offset; - printf("CBMEM table of contents:\n"); - printf(" ID START LENGTH\n"); - - for (i=0; i<MAX_CBMEM_ENTRIES; i++) { - if (entries[i].magic != CBMEM_MAGIC) - break; - cbmem_print_entry(i, entries[i].id, - entries[i].base, entries[i].size); - } -} + table = map_lbtable(); -static void dump_dynamic_cbmem_toc(struct cbmem_root *root) -{ - int i; - debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n", - root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset); + if (table == NULL) + return; printf("CBMEM table of contents:\n"); printf(" ID START LENGTH\n"); - for (i = 0; i < root->num_entries; i++) { - if(root->entries[i].magic != CBMEM_ENTRY_MAGIC) - break; - cbmem_print_entry(i, root->entries[i].id, - rootptr + root->entries[i].start_offset, root->entries[i].size); - } -} - -static void dump_cbmem_toc(void) -{ - uint64_t start; - void *cbmem_area; - struct cbmem_entry *entries; + i = 0; + offset = 0; - if (cbmem.type != LB_MEM_TABLE) { - fprintf(stderr, "No coreboot CBMEM area found!\n"); - return; - } + while (offset < lbtable_size) { + struct lb_record *lbr; + struct lb_cbmem_entry *lbe; - start = unpack_lb64(cbmem.start); + lbr = (void *)(table + offset); + offset += lbr->size; - cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size)); - entries = (struct cbmem_entry *)cbmem_area; + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; - if (entries[0].magic == CBMEM_MAGIC) { - dump_static_cbmem_toc(entries); - } else { - rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size); - rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); - rootptr -= sizeof(struct cbmem_root_pointer); - unmap_memory(); - struct cbmem_root_pointer *r = - map_memory_size(rootptr, sizeof(*r)); - if (r->magic == CBMEM_POINTER_MAGIC) { - struct cbmem_root *root; - uint64_t rootaddr = rootptr + r->root_offset; - unmap_memory(); - root = map_memory_size(rootaddr, ROOT_MIN_SIZE); - dump_dynamic_cbmem_toc(root); - } else - fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n"); + lbe = (void *)lbr; + cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size); + i++; } - unmap_memory(); + unmap_lbtable(); } #define COVERAGE_MAGIC 0x584d4153 @@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode) static void dump_coverage(void) { - int i, found = 0; uint64_t start; - struct cbmem_entry *entries; + size_t size; void *coverage; unsigned long phys_offset; #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset) - if (cbmem.type != LB_MEM_TABLE) { - fprintf(stderr, "No coreboot table area found!\n"); + if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) { + fprintf(stderr, "No coverage information found\n"); return; } - start = unpack_lb64(cbmem.start); - - entries = (struct cbmem_entry *)map_memory(start); - - for (i=0; i<MAX_CBMEM_ENTRIES; i++) { - if (entries[i].magic != CBMEM_MAGIC) - break; - if (entries[i].id == CBMEM_ID_COVERAGE) { - found = 1; - break; - } - } - - if (!found) { - unmap_memory(); - fprintf(stderr, "No coverage information found in" - " CBMEM area.\n"); - return; - } - - start = entries[i].base; - unmap_memory(); /* Map coverage area */ - coverage = map_memory(start); + coverage = map_memory_size(start, size); phys_offset = (unsigned long)coverage - (unsigned long)start; printf("Dumping coverage data...\n");

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Patch set updated for coreboot: coreinfo: reboot when finished
by Maxime de Roucy 30 Sep '15

30 Sep '15

Maxime de Roucy (maxime.deroucy(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11731 -gerrit commit 3d533a5f66850cb0e69e472fd1ab90a0ae1a1090 Author: Maxime de Roucy <maxime.deroucy(a)gmail.com> Date: Sun Sep 27 15:53:40 2015 +0200 coreinfo: reboot when finished Avoid a "General Protection Fault Exception" when launched by SeaBIOS on pcengines APU1 Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7 Signed-off-by: Maxime de Roucy <maxime.deroucy(a)gmail.com> --- payloads/coreinfo/coreinfo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 5bd1068..df52056 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -301,6 +301,9 @@ int main(void) loop(); + /* reboot */ + outb(0x6, 0xcf9); + halt(); return 0; }

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New patch to review for coreboot: northbridge/intel/gm45: Use IS_ENABLED macro to increase build coverage
by Audrey Pearson 30 Sep '15

30 Sep '15

Audrey Pearson (apearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11760 -gerrit commit 7e67fcb9a2691b5447a0cbb31e77293667db024e Author: Audrey Pearson <apearson(a)raptorengineeringinc.com> Date: Wed Sep 30 14:44:13 2015 -0500 northbridge/intel/gm45: Use IS_ENABLED macro to increase build coverage Change-Id: I4bd689af5459b23ebc74c7623fefd56785af96f0 Signed-off-by: Audrey Pearson <apearson(a)raptorengineeringinc.com> --- src/northbridge/intel/gm45/gma.c | 780 +++++++++++++++++++-------------------- 1 file changed, 390 insertions(+), 390 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 42b340a..1c47c2a 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -46,392 +46,392 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - static void power_port(u8 *mmio) { - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - write32(mmio + 0x00061100, 0x00010000); - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - read32(mmio + 0x00061100); // = 0x00000000 - read32(mmio + 0x00064200); // = 0x0000001c - write32(mmio + 0x00064210, 0x8004003e); - write32(mmio + 0x00064214, 0x80060002); - write32(mmio + 0x00064218, 0x01000000); - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - write32(mmio + 0x00064f00, 0x0100030c); - write32(mmio + 0x00064f04, 0x00b8230c); - write32(mmio + 0x00064f08, 0x06f8930c); - write32(mmio + 0x00064f0c, 0x09f8e38e); - write32(mmio + 0x00064f10, 0x00b8030c); - write32(mmio + 0x00064f14, 0x0b78830c); - write32(mmio + 0x00064f18, 0x0ff8d3cf); - write32(mmio + 0x00064f1c, 0x01e8030c); - write32(mmio + 0x00064f20, 0x0ff863cf); - write32(mmio + 0x00064f24, 0x0ff803cf); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x00044000); // = 0x00000000 - write32(mmio + 0x00044030, 0x00001000); - read32(mmio + 0x00061150); // = 0x0000001c - write32(mmio + 0x00061150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x00044000); // = 0x00000000 - read32(mmio + LVDS); // = 0x40000002 + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + read32(mmio + 0x00061100); // = 0x00000000 + write32(mmio + 0x00061100, 0x00000000); + write32(mmio + 0x00061100, 0x00010000); + read32(mmio + 0x00061100); // = 0x00010000 + read32(mmio + 0x00061100); // = 0x00010000 + read32(mmio + 0x00061100); // = 0x00000000 + write32(mmio + 0x00061100, 0x00000000); + read32(mmio + 0x00061100); // = 0x00000000 + read32(mmio + 0x00064200); // = 0x0000001c + write32(mmio + 0x00064210, 0x8004003e); + write32(mmio + 0x00064214, 0x80060002); + write32(mmio + 0x00064218, 0x01000000); + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + read32(mmio + 0x00064210); // = 0x0144003e + write32(mmio + 0x00064210, 0x8074003e); + read32(mmio + 0x00064210); // = 0x5144003e + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + read32(mmio + 0x00064210); // = 0x0144003e + write32(mmio + 0x00064210, 0x8074003e); + read32(mmio + 0x00064210); // = 0x5144003e + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + read32(mmio + 0x00064210); // = 0x0144003e + write32(mmio + 0x00064210, 0x8074003e); + read32(mmio + 0x00064210); // = 0x5144003e + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + write32(mmio + 0x00064f00, 0x0100030c); + write32(mmio + 0x00064f04, 0x00b8230c); + write32(mmio + 0x00064f08, 0x06f8930c); + write32(mmio + 0x00064f0c, 0x09f8e38e); + write32(mmio + 0x00064f10, 0x00b8030c); + write32(mmio + 0x00064f14, 0x0b78830c); + write32(mmio + 0x00064f18, 0x0ff8d3cf); + write32(mmio + 0x00064f1c, 0x01e8030c); + write32(mmio + 0x00064f20, 0x0ff863cf); + write32(mmio + 0x00064f24, 0x0ff803cf); + write32(mmio + 0x000c4030, 0x00001000); + read32(mmio + 0x00044000); // = 0x00000000 + write32(mmio + 0x00044030, 0x00001000); + read32(mmio + 0x00061150); // = 0x0000001c + write32(mmio + 0x00061150, 0x0000089c); + write32(mmio + 0x000fcc00, 0x01986f00); + write32(mmio + 0x000fcc0c, 0x01986f00); + write32(mmio + 0x000fcc18, 0x01986f00); + write32(mmio + 0x000fcc24, 0x01986f00); + read32(mmio + 0x00044000); // = 0x00000000 + read32(mmio + LVDS); // = 0x40000002 + } } static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + int i; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + vga_gr_write(0x18, 0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } - int i; - u8 edid_data[128]; - struct edid edid; - struct edid_mode *mode; - u32 hactive, vactive, right_border, bottom_border; - int hpolarity, vpolarity; - u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; - u32 candp1, candn; - u32 best_delta = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; - - vga_gr_write(0x18, 0); - - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } + write32(mmio + ADPA, 0x40008c18); + write32(mmio + 0x7041c, 0x0); + write32(mmio + _DPLL_B_MD, 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + power_port(mmio); + + intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + + target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock + : (2 * mode->pixel_clock); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } - write32(mmio + ADPA, 0x40008c18); - write32(mmio + 0x7041c, 0x0); - write32(mmio + _DPLL_B_MD, 0x3); - - vga_misc_write(0x67); - - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - power_port(mmio); - - intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); - decode_edid(edid_data, - sizeof(edid_data), &edid); - mode = &edid.mode; - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; - vactive = edid.y_resolution; - right_border = mode->hborder; - bottom_border = mode->vborder; - hpolarity = (mode->phsync == '-'); - vpolarity = (mode->pvsync == '-'); - vsync = mode->vspw; - hsync = mode->hspw; - vblank = mode->vbl; - hblank = mode->hbl; - hfront_porch = mode->hso; - vfront_porch = mode->vso; - - target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -#else - vga_textmode_init(); -#endif - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom + 60000) / 120000; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (120000 * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } } } - } - if (best_delta == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return; - } + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); - - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_DEBUG, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_DEBUG, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_DEBUG, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_DEBUG, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, - info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); - printk(BIOS_DEBUG, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); - - write32(mmio + LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - mdelay(1); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(mmio + FP0(0), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - /* Re-lock the registers. */ - write32(mmio + PP_CONTROL, - (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - - write32(mmio + LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); -#else - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); -#endif - - mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); -#else - write32(mmio + VGACNTRL, 0x22c4008e); -#endif - - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0xb01a2050); - mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - ); - write32(mmio + LVDS, - LVDS_PORT_ENABLE - | (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); - mdelay(1); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS - | PANEL_POWER_ON | PANEL_POWER_RESET); - - printk (BIOS_DEBUG, "waiting for panel powerup\n"); - while (1) { - u32 reg32; - reg32 = read32(mmio + PP_STATUS); - if (((reg32 >> 28) & 3) == 0) - break; - } - printk (BIOS_DEBUG, "panel powered up\n"); + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + mdelay(1); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PP_CONTROL, + (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0x20000000); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + } + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0x22c4008e); + } + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + 0x00060100, 0xb01c4000); + write32(mmio + 0x000f000c, 0xb01a2050); + mdelay(1); + write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC + ); + write32(mmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(mmio + PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); - write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } + } } -#endif static void gma_func0_init(struct device *dev) { @@ -447,30 +447,30 @@ static void gma_func0_init(struct device *dev) struct northbridge_intel_gm45_config *conf = dev->chip_info; -#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); -#else - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); - } + if (!CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + } else { + u32 physbase; + struct resource *lfb_res; + struct resource *pio_res; + + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + + physbase = pci_read_config32(dev, 0x5c) & ~0xf; - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); -#endif + if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base + && lfb_res && lfb_res->base) { + printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, + pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); + } /* Post VBIOS init */ /* Enable Backlight */

1 0

Patch set updated for coreboot: northbridge/intel/gm45: Fix native VGA init
by Audrey Pearson 30 Sep '15

30 Sep '15

Audrey Pearson (apearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11738 -gerrit commit 44a9388820a437f9239d4246d3c66bcd8e6939aa Author: Audrey Pearson <apearson(a)raptorengineeringinc.com> Date: Tue Sep 29 12:36:52 2015 -0500 northbridge/intel/gm45: Fix native VGA init Building an image for the Lenovo X200 with native graphics initialization selected fails due to the changes introduced by commit a3b898aa (edid: Clean-up the edid struct). Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25 Signed-off-by: Audrey Pearson <apearson(a)raptorengineeringinc.com> --- src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index f29b9b1..42b340a 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -109,6 +109,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, int i; u8 edid_data[128]; struct edid edid; + struct edid_mode *mode; u32 hactive, vactive, right_border, bottom_border; int hpolarity, vpolarity; u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; @@ -155,25 +156,26 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); decode_edid(edid_data, sizeof(edid_data), &edid); + mode = &edid.mode; /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); hactive = edid.x_resolution; vactive = edid.y_resolution; - right_border = edid.hborder; - bottom_border = edid.vborder; - hpolarity = (edid.phsync == '-'); - vpolarity = (edid.pvsync == '-'); - vsync = edid.vspw; - hsync = edid.hspw; - vblank = edid.vbl; - hblank = edid.hbl; - hfront_porch = edid.hso; - vfront_porch = edid.vso; - - target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock - : (2 * edid.pixel_clock); + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + + target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock + : (2 * mode->pixel_clock); #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_sr_write(1, 1); vga_sr_write(0x2, 0xf); @@ -240,8 +242,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",

1 0

Patch set updated for coreboot: chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
by Paul Kocialkowski 30 Sep '15

30 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498 -gerrit commit d24592268b2d08fde103f6a09e21e7600bc7b93e Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:44:56 2015 +0200 chromeos: vboot_common: Avoid code duplication when grabbing the handoff info vboot_handoff_flag was duplicating the logic to grab the handoff info, that is already made available with vboot_get_handoff_info. This uses vboot_get_handoff_info in vboot_handoff_flag instead. Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/vendorcode/google/chromeos/vboot_common.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 1c216d0..6184b0d 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -58,10 +58,9 @@ int vboot_get_handoff_info(void **addr, uint32_t *size) static int vboot_handoff_flag(uint32_t flag) { struct vboot_handoff *vbho; + uint32_t size; - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) + if (vboot_get_handoff_info((void **)&vbho, &size)) return 0; return !!(vbho->init_params.out_flags & flag);

1 0

New patch to review for coreboot: tegra132/tegra210: remove verstage.c
by Aaron Durbin 30 Sep '15

30 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11759 -gerrit commit 9f7a083882b39fda8bd5447d6fabd61402d64053 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 13:29:15 2015 -0500 tegra132/tegra210: remove verstage.c I missed these Makefile.inc changes. As verstage.c was removed remove the references within the Makefile.incs. Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/nvidia/tegra132/Makefile.inc | 1 - src/soc/nvidia/tegra210/Makefile.inc | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index bdd8074..54530b1 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -21,7 +21,6 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif -verstage-y += verstage.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index fb38d38..90b60b5e 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -23,7 +23,6 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif -verstage-y += verstage.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c

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coreboot-gerrit September 2015