coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: amd8111, ck804, mcp55: use CONFIG_HPET_ADDRESS
by Jonathan A. Kollasch 15 Jul '15

15 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10925 -gerrit commit 1a75a61584ad2f9e27934c140915e2b7d527d35c Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Wed Jul 15 13:47:33 2015 -0500 amd8111, ck804, mcp55: use CONFIG_HPET_ADDRESS As acpi_write_hpet() uses CONFIG_HPET_ADDRESS in the HPET table we need to use CONFIG_HPET_ADDRESS when assigning it to the device. Change-Id: I656f917658f1c1717bb3653fa048a6d36fca2454 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index df3eff4..8841760 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -26,7 +26,7 @@ static void enable_hpet(struct device *dev) { unsigned long hpet_address; - pci_write_config32(dev,0xa0, 0xfed00001); + pci_write_config32(dev, 0xa0, CONFIG_HPET_ADDRESS|1); hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d0f687f..be8a39c 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -207,7 +207,7 @@ static void ck804_lpc_read_resources(device_t dev) res = find_resource(dev, 0x44); /* HPET */ if (res) { - res->base = 0xfed00000; + res->base = CONFIG_HPET_ADDRESS; res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 8d1a83a..5726c76 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -83,7 +83,7 @@ static void enable_hpet(struct device *dev) { unsigned long hpet_address; - pci_write_config32(dev, 0x44, 0xfed00001); + pci_write_config32(dev, 0x44, CONFIG_HPET_ADDRESS|1); hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); }

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New patch to review for coreboot: payloads: preliminary depthcharge support
by Stefan Reinauer 15 Jul '15

15 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10924 -gerrit commit 726c592882154f99be18c6862dc85aad2e1f1ad5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 15 10:24:18 2015 -0700 payloads: preliminary depthcharge support This is the first piece of many to build a Chrome OS firmware image right out of an upstream coreboot source tree. This does not provide you with a booting image, because many more steps are necessary, such as deploying the required stages to the A/B sections, adding the root and recovery key, images, and signing the RW sections. Change-Id: Id0195bd3b4e454f382782106d6512469106daac5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/external/Makefile.inc | 6 ++++ payloads/external/depthcharge/Kconfig | 7 ++++ payloads/external/depthcharge/Kconfig.name | 8 +++++ payloads/external/depthcharge/Makefile.inc | 53 ++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 165670d..ed9aaee 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -22,6 +22,9 @@ ifeq ($(CONFIG_PAYLOAD_ELF),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) endif +ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) +COREBOOT_ROM_DEPENDENCIES+=depthcharge +endif ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) COREBOOT_ROM_DEPENDENCIES+=seabios endif @@ -48,6 +51,9 @@ seabios: CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) +depthcharge: + $(MAKE) -C payloads/external/depthcharge -f Makefile.inc + filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig new file mode 100644 index 0000000..84b36e5 --- /dev/null +++ b/payloads/external/depthcharge/Kconfig @@ -0,0 +1,7 @@ +if PAYLOAD_DEPTHCHARGE + +config PAYLOAD_FILE + string + default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" + +endif diff --git a/payloads/external/depthcharge/Kconfig.name b/payloads/external/depthcharge/Kconfig.name new file mode 100644 index 0000000..bc564ec --- /dev/null +++ b/payloads/external/depthcharge/Kconfig.name @@ -0,0 +1,8 @@ +config PAYLOAD_DEPTHCHARGE + bool "Depthcharge" + depends on CHROMEOS + help + Select this option if you want to build a coreboot image + with a depthcharge payload. + + See http://coreboot.org/Payloads for more information. diff --git a/payloads/external/depthcharge/Makefile.inc b/payloads/external/depthcharge/Makefile.inc new file mode 100644 index 0000000..95a850b --- /dev/null +++ b/payloads/external/depthcharge/Makefile.inc @@ -0,0 +1,53 @@ +TAG-y=origin/master + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES +unexport src srck obj objk + +BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR)) + +all: build + +depthcharge: + echo " Cloning depthcharge from Git" + git clone https://chromium.googlesource.com/chromiumos/platform/depthcharge + +fetch: depthcharge + cd depthcharge; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + then echo " Fetching new commits from the depthcharge git repo"; git fetch; fi + +checkout: fetch + echo " Checking out depthcharge revision $(TAG-y)" + cd depthcharge; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + +config: checkout + echo " CONFIG depthcharge $(TAG-y)" + cp depthcharge/board/$(BOARD)/defconfig depthcharge/.config + pwd + yes "" | make -C depthcharge oldconfig + +build: config + echo " MAKE depthcharge $(TAG-y)" + cp depthcharge/board/$(BOARD)/defconfig.libpayload ../../libpayload/.config + yes "" | make -C ../../libpayload oldconfig + cd ../../libpayload && make + make -C ../../libpayload install DESTDIR=installed + export VERSION=$$(cd depthcharge && \ + git describe --tags --long --dirty 2>/dev/null || \ + echo "unknown") ; \ + cd depthcharge && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(abspath ../../libpayload/installed/libpayload) \ + VB_SOURCE=3rdparty/vboot defconfig + cd depthcharge && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(abspath ../../libpayload/installed/libpayload) \ + VB_SOURCE=../../../../3rdparty/vboot depthcharge_unified + +clean: + test -d depthcharge/out && rm -rf depthcharge/out || exit 0 + +distclean: + rm -rf depthcharge + +.PHONY: checkout config build clean distclean clone fetch

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New patch to review for coreboot: payloads: Move payloads logic to payloads directory
by Stefan Reinauer 15 Jul '15

15 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10923 -gerrit commit 47d3bbebcc832f3ae933e37fbeb486dea1dea50f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 14 15:57:44 2015 -0700 payloads: Move payloads logic to payloads directory Change-Id: I6437e30da6ab675d32dc81c5d6d3fd9bcdc67f06 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 12 ------------ payloads/external/Makefile.inc | 13 +++++++++++++ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 347e07b..b402155 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -542,18 +542,6 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ########################################################################### COREBOOT_ROM_DEPENDENCIES:= -ifeq ($(CONFIG_PAYLOAD_ELF),y) -COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) -endif -ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -COREBOOT_ROM_DEPENDENCIES+=seabios -endif -ifeq ($(CONFIG_PAYLOAD_FILO),y) -COREBOOT_ROM_DEPENDENCIES+=filo -endif -ifeq ($(CONFIG_PAYLOAD_GRUB2),y) -COREBOOT_ROM_DEPENDENCIES+=grub2 -endif extract_nth=$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-))) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 33ed47f..165670d 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -19,6 +19,19 @@ ## Foundation, Inc. ## +ifeq ($(CONFIG_PAYLOAD_ELF),y) +COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) +endif +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) +COREBOOT_ROM_DEPENDENCIES+=seabios +endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) +COREBOOT_ROM_DEPENDENCIES+=filo +endif +ifeq ($(CONFIG_PAYLOAD_GRUB2),y) +COREBOOT_ROM_DEPENDENCIES+=grub2 +endif + seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ HOSTCC="$(HOSTCC)" \

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Patch merged into coreboot/master: amd/model_fxx rev.F: emit P-states when no intermediates exist
by gerrit＠coreboot.org 15 Jul '15

15 Jul '15

the following patch was just integrated into master: commit e731f721bedee7ce9c6ac21249fac05ff5cf63d3 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 13 17:05:07 2015 -0500 amd/model_fxx rev.F: emit P-states when no intermediates exist Relevant for systems having processors that only have two (the minimum and maximum) P-states, such as the Opteron 2210 at 1.0 and 1.8GHz. Change-Id: Ic66fe6d10ce495c1bf21796cb7e1eb4e11e85283 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10910 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10910 for details. -gerrit

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New patch to review for coreboot: indent style fix for lapic_cpu_init.c
by Jonathan A. Kollasch 15 Jul '15

15 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10922 -gerrit commit 92c07e149dcd30b8c36cfea36fcabdcb94ba1605 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Wed Jul 15 11:27:18 2015 -0500 indent style fix for lapic_cpu_init.c Change-Id: I2821aaed1bc6324e671f68e4e4effb9dd006dcd9 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0e314fd..7fedd00 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -310,7 +310,7 @@ int start_cpu(struct device *cpu) break; } udelay(10); - } + } } secondary_stack = 0; spin_unlock(&start_cpu_lock);

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Patch set updated for coreboot: AMD K8: Avoid duplicate variables in SSDT on multisocket systems
by Jonathan A. Kollasch 15 Jul '15

15 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10912 -gerrit commit 34b9718a4fde068ed94c3b64889770d7634be274 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 13 21:03:10 2015 -0500 AMD K8: Avoid duplicate variables in SSDT on multisocket systems Related-to: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9 (ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems) Change-Id: I0b5f265278d90cbaeddc6fc4432933856050f784 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/northbridge/amd/amdk8/acpi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 10228cf..0e35979 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -282,6 +282,17 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { void k8acpi_write_vars(device_t device) { + /* + * If more than one physical CPU is installed k8acpi_write_vars() + * is called more than once. If we don't prevent it, a SSDT table + * with duplicate variables will cause some ACPI parsers confused + * enough to fail. + */ + static uint8_t ssdt_generated = 0; + if (ssdt_generated) + return; + ssdt_generated = 1; + msr_t msr; char pscope[] = "\\_SB.PCI0";

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Patch merged into coreboot/master: libpayload: assume cbfs file alignment is 64 byte
by gerrit＠coreboot.org 15 Jul '15

15 Jul '15

the following patch was just integrated into master: commit 2272b80a1dafdee57d8ca89860e9e988f1dceafc Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jul 14 22:29:04 2015 +0200 libpayload: assume cbfs file alignment is 64 byte Change-Id: I8dfd8fbd452ce92fbca2cf095bc5e43e4a26969d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10920 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10920 for details. -gerrit

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Patch merged into coreboot/master: cbfs: hardcode file alignment
by gerrit＠coreboot.org 15 Jul '15

15 Jul '15

the following patch was just integrated into master: commit 4d3e4c421e94814884d1ff035a4c4ec80d4b33b2 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jul 14 22:28:27 2015 +0200 cbfs: hardcode file alignment Assume that it's 64 byte. Change-Id: I168facd92f64c2cf99c26c350c60317807a4aed4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10919 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10919 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: fix alignment to 64 byte
by gerrit＠coreboot.org 15 Jul '15

15 Jul '15

the following patch was just integrated into master: commit 45acb34ffce5ffef1e574305b4e18af6d26df46b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jul 14 22:18:23 2015 +0200 cbfstool: fix alignment to 64 byte It's not like we _ever_ changed it, so drop the option and make cbfstool use the default. always. Change-Id: Ia1b99fda03d5852137a362422e979f4a4dffc5ed Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10918 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10918 for details. -gerrit

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Patch set updated for coreboot: armv8 : coreboot for qemu aarch64 #Work in progress#
by Naman Govil 15 Jul '15

15 Jul '15

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10527 -gerrit commit 7bd4e6816c6a6164d15bc9fa6e5180fcb42d6654 Author: Naman Govil <namangov(a)gmail.com> Date: Wed Jul 15 02:51:36 2015 -0400 armv8 : coreboot for qemu aarch64 #Work in progress# This patchset aims to add a new mainboard (emulation) for arm64. By the end of this work, we will have coreboot running on a qemu-system-aarch64. Change-Id: I5550dcaae9981908e0c3bf6961206a70bebac5d1 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/arch/arm64/armv8/bootblock_simple.c | 2 +- src/arch/arm64/c_entry.c | 22 ++- src/arch/arm64/cpu.c | 3 +- src/arch/arm64/cpu.h | 204 +++++++++++++++++++++ src/arch/arm64/include/arch/cpu.h | 204 +++++++++++++++++++++ src/arch/arm64/include/armv8/arch/secmon.h | 4 +- src/cpu/armltd/armv8/Kconfig | 11 ++ src/mainboard/emulation/qemu-armv8/Kconfig | 55 ++++++ src/mainboard/emulation/qemu-armv8/Kconfig.name | 2 + src/mainboard/emulation/qemu-armv8/Makefile.inc | 40 ++++ src/mainboard/emulation/qemu-armv8/board_info.txt | 3 + .../emulation/qemu-armv8/bootblock-common.h | 19 ++ src/mainboard/emulation/qemu-armv8/bootblock.c | 22 +++ src/mainboard/emulation/qemu-armv8/cbmem.c | 25 +++ src/mainboard/emulation/qemu-armv8/cpu_lib.S | 29 +++ src/mainboard/emulation/qemu-armv8/devicetree.cb | 20 ++ src/mainboard/emulation/qemu-armv8/mainboard.c | 27 +++ src/mainboard/emulation/qemu-armv8/media.c | 25 +++ src/mainboard/emulation/qemu-armv8/memlayout.ld | 48 +++++ src/mainboard/emulation/qemu-armv8/romstage.c | 24 +++ src/mainboard/emulation/qemu-armv8/timer.c | 27 +++ src/mainboard/emulation/qemu-armv8/uart.c | 24 +++ 22 files changed, 827 insertions(+), 13 deletions(-) diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c index c93a100..681bbf9 100644 --- a/src/arch/arm64/armv8/bootblock_simple.c +++ b/src/arch/arm64/armv8/bootblock_simple.c @@ -51,7 +51,7 @@ void main(void) */ if (boot_cpu()) { - bootblock_cpu_init(); + //bootblock_cpu_init(); bootblock_mainboard_init(); } diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index 5970405..3f672a3 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -63,22 +63,26 @@ static void arm64_init(void) main(); } -static void secondary_cpu_start(void) -{ -#ifndef __PRE_RAM__ - mmu_enable(); - exception_hwinit(); +//static void secondary_cpu_start(void) +//{ +//#ifndef __PRE_RAM__ +// mmu_enable(); +// exception_hwinit(); /* This will never return. */ - arch_secondary_cpu_init(); -#endif -} +// arch_secondary_cpu_init(); +//#endif +//} /* * This variable holds entry point for CPUs starting up. The first * element is the BSP path, and the second is the non-BSP path. */ -void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init }; +#ifdef __PRE_RAM__ +void (*c_entry[2])(void) = { &arm64_init, NULL}; +#else +void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init}; +#endif void *prepare_secondary_cpu_startup(void) { diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c index 3cf73ae..1026434 100644 --- a/src/arch/arm64/cpu.c +++ b/src/arch/arm64/cpu.c @@ -219,8 +219,9 @@ void arch_cpu_wait_for_action(void) action_queue_complete(q, orig); } } - +#ifdef __PRE_RAM__ int boot_cpu(void) { return cpu_is_bsp(); } +#endif diff --git a/src/arch/arm64/cpu.h b/src/arch/arm64/cpu.h new file mode 100644 index 0000000..ae16fa1 --- /dev/null +++ b/src/arch/arm64/cpu.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_CPU_H__ +#define __ARCH_CPU_H__ + +#define asmlinkage + +#if !defined(__PRE_RAM__) +#include <arch/barrier.h> +#include <arch/mpidr.h> +#include <device/device.h> + +enum { + CPU_ID_END = 0x00000000, +}; + +struct cpu_device_id { + uint32_t midr; +}; + +struct cpu_driver { + /* This is excessive as init() is the only one called. */ + struct device_operations *ops; + const struct cpu_device_id *id_table; +}; + +/* Action to run. */ +struct cpu_action { + void (*run)(void *arg); + void *arg; +}; + +/* + * Actions are queued to 'todo'. When picked up 'todo' is cleared. The + * 'completed' field is set to the original 'todo' value when the action + * is complete. + */ +struct cpu_action_queue { + struct cpu_action *todo; + struct cpu_action *completed; +}; + +struct cpu_info { + device_t cpu; + struct cpu_action_queue action_queue; + unsigned int online; + /* Current assumption is that id matches smp_processor_id(). */ + unsigned int id; + uint64_t mpidr; +}; + +/* Obtain cpu_info for current executing CPU. */ +struct cpu_info *cpu_info(void); + +extern struct cpu_info *bsp_cpu_info; +extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; + +static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) +{ + return &cpu_infos[id]; +} + +/* Ran only by BSP at initial boot strapping. */ +static inline void cpu_set_bsp(void) +{ + bsp_cpu_info = cpu_info(); +} + +static inline int cpu_is_bsp(void) +{ + return cpu_info() == bsp_cpu_info; +} + +static inline int cpu_online(struct cpu_info *ci) +{ + return load_acquire(&ci->online) != 0; +} + +static inline void cpu_mark_online(struct cpu_info *ci) +{ + ci->mpidr = read_affinity_mpidr(); + store_release(&ci->online, 1); +} + +/* Provide number of CPUs online. */ +size_t cpus_online(void); + +/* Control routines for starting CPUs. */ +struct cpu_control_ops { + /* Return the maximum number of CPUs supported. */ + size_t (*total_cpus)(void); + /* + * Start the requested CPU and have it start running entry(). + * Returns 0 on success, < 0 on error. + */ + int (*start_cpu)(unsigned int id, void (*entry)(void)); +}; + +/* + * Initialize all DEVICE_PATH_CPUS under the DEVICE_PATH_CPU_CLUSTER cluster. + * type DEVICE_PATH_CPUS. Start up is controlled by cntrl_ops. + */ +void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops); + +/* + * Run cpu_action returning < 0 on error, 0 on success. There are synchronous + * and asynchronous methods. Both cases ensure the action has been picked up + * by the target cpu. The synchronous variants will wait for the action to + * be completed before returning. + * + * Though the current implementation allows queuing actions on the main cpu, + * the main cpu doesn't process its own queue. + */ +int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus(struct cpu_action *action); +int arch_run_on_all_cpus_but_self(struct cpu_action *action); +int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus_async(struct cpu_action *action); +int arch_run_on_all_cpus_but_self_async(struct cpu_action *action); + +/* Wait for actions to be perfomed. */ +void arch_cpu_wait_for_action(void); + +#endif /* !__PRE_RAM__ */ + +/* + * Returns logical cpu in range [0:MAX_CPUS). SoC should define this. + * Additionally, this is needed early in arm64 init so it should not + * rely on a stack. Standard clobber list is fair game: x0-x7 and x0 + * returns the logical cpu number. + */ +unsigned int smp_processor_id(void); + +/* + * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided + * a pointer the correct non-BSP entry point will be returned. The + * first instruction is for BSP and the 2nd is for non-BSP. Instructions + * are all 32-bit on arm64. + */ +static inline void *secondary_entry_point(void *e) +{ + uintptr_t nonbsp = (uintptr_t)e; + + return (void *)(nonbsp + sizeof(uint32_t)); +} + +/* + * The arm64_cpu_startup() initializes a CPU's exception stack and regular + * stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + */ +void arm64_cpu_startup(void); + +/* + * The arm64_cpu_startup_resume() initializes a CPU's exception stack and + * regular stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + * Additionally, it also restores saved register data and enables MMU, caches + * and exceptions before jumping to C environment for both BSP and non-BSP CPUs. + */ +void arm64_cpu_startup_resume(void); + +/* + * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of + * ARM arch timer. + */ +void arm64_arch_timer_init(void); + +/* + * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM. + * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported. + */ +#define NO_L2_FLUSH 0 +#define L2_FLUSH_HW 0 +#define L2_FLUSH_SW 1 + +#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) +void cortex_a57_cpu_power_down(int l2_flush); +#else +static inline void cortex_a57_cpu_power_down(int l2_flush) {} +#endif + +#endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/arch/cpu.h b/src/arch/arm64/include/arch/cpu.h new file mode 100644 index 0000000..ae16fa1 --- /dev/null +++ b/src/arch/arm64/include/arch/cpu.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_CPU_H__ +#define __ARCH_CPU_H__ + +#define asmlinkage + +#if !defined(__PRE_RAM__) +#include <arch/barrier.h> +#include <arch/mpidr.h> +#include <device/device.h> + +enum { + CPU_ID_END = 0x00000000, +}; + +struct cpu_device_id { + uint32_t midr; +}; + +struct cpu_driver { + /* This is excessive as init() is the only one called. */ + struct device_operations *ops; + const struct cpu_device_id *id_table; +}; + +/* Action to run. */ +struct cpu_action { + void (*run)(void *arg); + void *arg; +}; + +/* + * Actions are queued to 'todo'. When picked up 'todo' is cleared. The + * 'completed' field is set to the original 'todo' value when the action + * is complete. + */ +struct cpu_action_queue { + struct cpu_action *todo; + struct cpu_action *completed; +}; + +struct cpu_info { + device_t cpu; + struct cpu_action_queue action_queue; + unsigned int online; + /* Current assumption is that id matches smp_processor_id(). */ + unsigned int id; + uint64_t mpidr; +}; + +/* Obtain cpu_info for current executing CPU. */ +struct cpu_info *cpu_info(void); + +extern struct cpu_info *bsp_cpu_info; +extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; + +static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) +{ + return &cpu_infos[id]; +} + +/* Ran only by BSP at initial boot strapping. */ +static inline void cpu_set_bsp(void) +{ + bsp_cpu_info = cpu_info(); +} + +static inline int cpu_is_bsp(void) +{ + return cpu_info() == bsp_cpu_info; +} + +static inline int cpu_online(struct cpu_info *ci) +{ + return load_acquire(&ci->online) != 0; +} + +static inline void cpu_mark_online(struct cpu_info *ci) +{ + ci->mpidr = read_affinity_mpidr(); + store_release(&ci->online, 1); +} + +/* Provide number of CPUs online. */ +size_t cpus_online(void); + +/* Control routines for starting CPUs. */ +struct cpu_control_ops { + /* Return the maximum number of CPUs supported. */ + size_t (*total_cpus)(void); + /* + * Start the requested CPU and have it start running entry(). + * Returns 0 on success, < 0 on error. + */ + int (*start_cpu)(unsigned int id, void (*entry)(void)); +}; + +/* + * Initialize all DEVICE_PATH_CPUS under the DEVICE_PATH_CPU_CLUSTER cluster. + * type DEVICE_PATH_CPUS. Start up is controlled by cntrl_ops. + */ +void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops); + +/* + * Run cpu_action returning < 0 on error, 0 on success. There are synchronous + * and asynchronous methods. Both cases ensure the action has been picked up + * by the target cpu. The synchronous variants will wait for the action to + * be completed before returning. + * + * Though the current implementation allows queuing actions on the main cpu, + * the main cpu doesn't process its own queue. + */ +int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus(struct cpu_action *action); +int arch_run_on_all_cpus_but_self(struct cpu_action *action); +int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus_async(struct cpu_action *action); +int arch_run_on_all_cpus_but_self_async(struct cpu_action *action); + +/* Wait for actions to be perfomed. */ +void arch_cpu_wait_for_action(void); + +#endif /* !__PRE_RAM__ */ + +/* + * Returns logical cpu in range [0:MAX_CPUS). SoC should define this. + * Additionally, this is needed early in arm64 init so it should not + * rely on a stack. Standard clobber list is fair game: x0-x7 and x0 + * returns the logical cpu number. + */ +unsigned int smp_processor_id(void); + +/* + * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided + * a pointer the correct non-BSP entry point will be returned. The + * first instruction is for BSP and the 2nd is for non-BSP. Instructions + * are all 32-bit on arm64. + */ +static inline void *secondary_entry_point(void *e) +{ + uintptr_t nonbsp = (uintptr_t)e; + + return (void *)(nonbsp + sizeof(uint32_t)); +} + +/* + * The arm64_cpu_startup() initializes a CPU's exception stack and regular + * stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + */ +void arm64_cpu_startup(void); + +/* + * The arm64_cpu_startup_resume() initializes a CPU's exception stack and + * regular stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + * Additionally, it also restores saved register data and enables MMU, caches + * and exceptions before jumping to C environment for both BSP and non-BSP CPUs. + */ +void arm64_cpu_startup_resume(void); + +/* + * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of + * ARM arch timer. + */ +void arm64_arch_timer_init(void); + +/* + * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM. + * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported. + */ +#define NO_L2_FLUSH 0 +#define L2_FLUSH_HW 0 +#define L2_FLUSH_SW 1 + +#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) +void cortex_a57_cpu_power_down(int l2_flush); +#else +static inline void cortex_a57_cpu_power_down(int l2_flush) {} +#endif + +#endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h index f8351b5..6458893 100644 --- a/src/arch/arm64/include/armv8/arch/secmon.h +++ b/src/arch/arm64/include/armv8/arch/secmon.h @@ -24,8 +24,8 @@ struct secmon_params { size_t online_cpus; - struct cpu_action bsp; - struct cpu_action secondary; + struct cpu_action *bsp; + struct cpu_action *secondary; }; void secmon_run(void (*entry)(void *), void *arg); diff --git a/src/cpu/armltd/armv8/Kconfig b/src/cpu/armltd/armv8/Kconfig new file mode 100644 index 0000000..e73980c --- /dev/null +++ b/src/cpu/armltd/armv8/Kconfig @@ -0,0 +1,11 @@ +config CPU_ARMLTD_ARMV8 + bool + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + default n + +if CPU_ARMLTD_ARMV8 + +endif diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig b/src/mainboard/emulation/qemu-armv8/Kconfig new file mode 100644 index 0000000..d152813 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Kconfig @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# WRITE THE INSTRUCTIONS TO EXECUTE +# To execute, do: +# export QEMU_AUDIO_DRV=none +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom + +if BOARD_EMULATION_QEMU_ARMV8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select DRIVERS_UART_PL011 + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + select CONSOLE_SERIAL + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select BOARD_ROMSIZE_KB_4096 + + +config MAINBOARD_DIR + string + default emulation/qemu-armv8 + +config MAINBOARD_PART_NUMBER + string + default "QEMU ARMv8" + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "ARM Ltd." + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_EMULATION_QEMU_ARMV8 diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig.name b/src/mainboard/emulation/qemu-armv8/Kconfig.name new file mode 100644 index 0000000..bb3a0e4 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_EMULATION_QEMU_ARMV8 + bool "QEMU armv8" diff --git a/src/mainboard/emulation/qemu-armv8/Makefile.inc b/src/mainboard/emulation/qemu-armv8/Makefile.inc new file mode 100644 index 0000000..7fa8880 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Makefile.inc @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +romstage-y += romstage.c + +romstage-y += cbmem.c +ramstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += timer.c +romstage-y += timer.c +ramstage-y += timer.c + +bootblock-y += uart.c +romstage-y += uart.c +ramstage-y += uart.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld + +bootblock-y += cpu_lib.S +romstage-y += cpu_lib.S +ramstage-y += cpu_lib.S + diff --git a/src/mainboard/emulation/qemu-armv8/board_info.txt b/src/mainboard/emulation/qemu-armv8/board_info.txt new file mode 100644 index 0000000..69c5eb6 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU armv8 +Category: emulation +Board URL: http://fabrice.bellard.free.fr/qemu/ diff --git a/src/mainboard/emulation/qemu-armv8/bootblock-common.h b/src/mainboard/emulation/qemu-armv8/bootblock-common.h new file mode 100644 index 0000000..09cff10 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/bootblock-common.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <console/console.h> + +void bootblock_cpu_init(void); diff --git a/src/mainboard/emulation/qemu-armv8/bootblock.c b/src/mainboard/emulation/qemu-armv8/bootblock.c new file mode 100644 index 0000000..d198a43 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <console/console.h> +#include "bootblock-common.h" + +void bootblock_cpu_init(void) +{ +} diff --git a/src/mainboard/emulation/qemu-armv8/cbmem.c b/src/mainboard/emulation/qemu-armv8/cbmem.c new file mode 100644 index 0000000..d3a2d6f --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stddef.h> +#include <cbmem.h> +#include <symbols.h> + +void *cbmem_top(void) +{ + return _dram + (CONFIG_DRAM_SIZE_MB << 20); +} diff --git a/src/mainboard/emulation/qemu-armv8/cpu_lib.S b/src/mainboard/emulation/qemu-armv8/cpu_lib.S new file mode 100644 index 0000000..13eed4b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/cpu_lib.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright 2015, Naman Govil <namangov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +.text +.global smp_processor_id +smp_processor_id: + /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */ + /* Multiprocessor Afinity Register (MPIDR) contains CPU ID for a57 */ + mrs x0, mpidr_el1 + uxtb w0, w0 + ret diff --git a/src/mainboard/emulation/qemu-armv8/devicetree.cb b/src/mainboard/emulation/qemu-armv8/devicetree.cb new file mode 100644 index 0000000..fa3c03a --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# TODO fill with Versatile Express board data in QEMU. +chip cpu/armltd/armv8 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-armv8/mainboard.c b/src/mainboard/emulation/qemu-armv8/mainboard.c new file mode 100644 index 0000000..b73ab9d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Enable qemu/armv8 device...\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-armv8/media.c b/src/mainboard/emulation/qemu-armv8/media.c new file mode 100644 index 0000000..4d4edd8 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> + +/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-armv8/memlayout.ld b/src/mainboard/emulation/qemu-armv8/memlayout.ld new file mode 100644 index 0000000..ee8132d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/memlayout.ld @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C )2015, Naman Govil <namangov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Memory map for qemu armv8: + * + * 0x0000_0000: jump instruction (required by qemu) + * 0x0001_0000: bootblock (entry of kernel / firmware) + * 0x0002_0000: romstage, assume up to 128KB in size. + * 0x0007_ff00: stack pointer + * 0x0010_0000: CBFS header + * 0x0011_0000: CBFS data + * 0x0100_0000: reserved for ramstage + * 0x1000_0000: I/O map address + */ + +SECTIONS +{ + /* TODO: does this thing emulate SRAM? */ + + BOOTBLOCK(0x10000, 64K) + ROMSTAGE(0x20000, 128K) + STACK(0x000FC000, 16K) + + DRAM_START(0x01000000) + RAMSTAGE(0x01000000, 16M) +} diff --git a/src/mainboard/emulation/qemu-armv8/romstage.c b/src/mainboard/emulation/qemu-armv8/romstage.c new file mode 100644 index 0000000..158989f --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <program_loading.h> + +void main(void) +{ + console_init(); + run_ramstage(); +} diff --git a/src/mainboard/emulation/qemu-armv8/timer.c b/src/mainboard/emulation/qemu-armv8/timer.c new file mode 100644 index 0000000..b6d048b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void udelay(unsigned int n); +void udelay(unsigned int n) +{ + /* TODO provide delay here. */ +} + +int init_timer(void); +int init_timer(void) +{ + return 0; +} diff --git a/src/mainboard/emulation/qemu-armv8/uart.c b/src/mainboard/emulation/qemu-armv8/uart.c new file mode 100644 index 0000000..d751b15 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/uart.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/uart.h> + +#define UART0_IO_ADDRESS (0x90000000) + +uintptr_t uart_platform_base(int idx) +{ + return UART0_IO_ADDRESS; +}

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2017

2016

2015

2014

2013

coreboot-gerrit July 2015