coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: Hack up per-board user selectable 64bit scheme
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11109 -gerrit commit 396490cea93c4b210628965b9dbbf1342c365605 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 31 16:57:40 2015 -0700 Hack up per-board user selectable 64bit scheme Change-Id: I91b1316896e69b081c861d99ff0c04be3c1d90c1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Kconfig | 5 +++++ src/cpu/amd/agesa/Kconfig | 12 ++++++++---- src/mainboard/asrock/e350m1/Kconfig | 1 + 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 88b2592..8905266 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -138,3 +138,8 @@ config ID_SECTION_OFFSET config COMPILE_IN_DSDT bool "compile in DSDT and use that over DSDT in CBFS" default n + +config BOARD_HAS_64BIT + bool "Compile 64bit coreboot" + depends on ARCH_X86 + default n diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 45e1d63..e3fee59 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,14 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_64 - select ARCH_VERSTAGE_X86_64 - select ARCH_ROMSTAGE_X86_64 - select ARCH_RAMSTAGE_X86_64 + select ARCH_BOOTBLOCK_X86_64 if BOARD_HAS_64BIT + select ARCH_VERSTAGE_X86_64 if BOARD_HAS_64BIT + select ARCH_ROMSTAGE_X86_64 if BOARD_HAS_64BIT + select ARCH_RAMSTAGE_X86_64 if BOARD_HAS_64BIT + select ARCH_BOOTBLOCK_X86_32 if !BOARD_HAS_64BIT + select ARCH_VERSTAGE_X86_32 if !BOARD_HAS_64BIT + select ARCH_ROMSTAGE_X86_32 if !BOARD_HAS_64BIT + select ARCH_RAMSTAGE_X86_32 if !BOARD_HAS_64BIT select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index ff3e8f4..a2d0a5a 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA + select BOARD_HAS_64BIT config MAINBOARD_DIR string

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New patch to review for coreboot: Drop unused code from gcc-intrin.h
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11108 -gerrit commit 89dcf416c00040550cd4822136f6832d6dcad282 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 31 16:44:55 2015 -0700 Drop unused code from gcc-intrin.h Change-Id: I3df66320d0bc18221f947b47e7f09533daafabad Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 36 ----------------------- 1 file changed, 36 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 9ae45c3..5d77c4d 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -612,40 +612,4 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) } #endif /* __SSE3__ */ -static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) -{ - __asm__ __volatile__ ( - "rep ; stosb " - : "+D" (dest), "+c" (count) - : "a"(data) - ); -} - -static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count) -{ - __asm__ __volatile__ ( - "movsb " - : "+D" (dest), "+S"(data), "+c" (count) - ); -} - -static __inline__ __attribute__((always_inline)) -void debug_point ( unsigned short Port, unsigned long Data ) -{ - __outdword (Port, Data); - __asm__ __volatile__ (".word 0xfeeb"); - -} - -static __inline__ __attribute__((always_inline)) -void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime ) -{ - UINTN Index; - Index = 0; - __outdword (Port, Data); - while (Index < delayTime * 600000) { - __outdword (0xE0, 0); - Index ++; - } -} #endif /* defined (__GNUC__) */

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New patch to review for coreboot: Random x86_64 fixes from Scott
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11107 -gerrit commit 98ceb2f41eb272535de8c8f3b1ed8a049d793cb7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 31 16:44:03 2015 -0700 Random x86_64 fixes from Scott Need to figure out what to do with these Change-Id: I6ed295131347796b27e660ccf3fca0de22801069 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/lib/ramstage.ld | 3 ++- src/southbridge/amd/cimx/sb800/smbus_spd.c | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 5 +++++ src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 8 ++++++++ 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 432df40..c5719d6 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -59,6 +59,7 @@ cpu_drivers = . ; KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; + . = ALIGN(16); _bs_init_begin = .; KEEP(*(.bs_init)); LONG(0); @@ -100,7 +101,7 @@ _heap = .; /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); + . = ALIGN(8); _eheap = .; _eramstage = .; _eprogram = .; diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index 1e458bd..052ee31 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -100,7 +100,7 @@ static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, UINT16 count) { UINT16 index; - UINT8 status; + UINT8 status = 0; UINT8 initial_offset = 0; setupFch(iobase); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S index 48ee5d0..9701087 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -75,6 +75,11 @@ ExecuteFinalHltInstruction: bt $0, %esi /* .if (esi & 1h) */ jz 2f +#ifdef __x86_64__ + /* hack to protect cache as ram page tables until copied to memory */ + jmp 7f +#endif + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ movl %edi, %esi /* Get ApMtrrSettingList */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c index ebcb58e..807a518 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c @@ -852,6 +852,10 @@ ApUtilSetupIdtForHlt ( UINT64 HandlerOffset; UINT64 EferRegister; IDT_BASE_LIMIT IdtInfo; +#ifdef __x86_64__ + // old way doesn't work with the -Og build + static const UINT8 iretOpcode [] = {/*0xEB, 0xFE,*/ 0x48, 0xCF}; // iretq +#endif LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader); if ((EferRegister & 0x100) != 0) { @@ -860,7 +864,11 @@ ApUtilSetupIdtForHlt ( DescSize = 8; } +#ifdef __x86_64__ + HandlerOffset = (UINT64) (intptr_t) &iretOpcode; +#else HandlerOffset = (UINT64) (intptr_t) &NmiHandler; +#endif NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF); NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);

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New patch to review for coreboot: wakeup: Switch back to 32bit mode first
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11106 -gerrit commit 4eddcf7fe77b1b60315b9baa30bb955544d87475 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 31 16:46:28 2015 -0700 wakeup: Switch back to 32bit mode first On x86_64 we need to leave long mode before we can switch to 16bit mode. Oh joy! When's my 64bit resume pointer coming? Why didn't this get caught earlier? Seems the Asrock E350M2 didn't do Suspend/Resume? Yes, I know it's Intel syntax. Will be converted to AT&T syntax as soon as the whole thing actually works.. 8) Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/wakeup.S | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index 38d6ea4..acc8737 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -32,6 +32,34 @@ .globl __wakeup __wakeup: +#ifdef __x86_64__ + .intel_syntax noprefix + xor rax,rax + mov ax, ss + push rax + mov rax, rsp + add rax, 8 + push rax + pushfq + push 0x10 + lea rax,[rip+3] + push rax + iretq + + .code32 + + /* disable paging */ + mov eax, cr0 + btc eax, 31 + mov cr0, eax + + /* disable long mode */ + mov ecx, 0xC0000080 + rdmsr + btc eax, 8 + wrmsr + .att_syntax prefix +#endif /* First prepare the jmp to the resume vector */ mov 0x4(%esp), %eax /* vector */ /* last 4 bits of linear addr are taken as offset */

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Patch set updated for coreboot: break lots of boards
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10594 -gerrit commit d4e092130cd59c4ca2ac69a6ea73ce38647628d2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:05:13 2015 -0700 break lots of boards Enable 64bit compilation for AGESA boards :-) Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 282e1ed..45e1d63 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

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Patch set updated for coreboot: f14: Increase AP stack to 8k on 64bit
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11025 -gerrit commit 8a376626dec1380014dd846296898b95437b98c9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 21 14:37:13 2015 -0700 f14: Increase AP stack to 8k on 64bit This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 2104c27..8f395ce 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ +CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ +#else CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

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Patch set updated for coreboot: ridiculously random ramblings
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11090 -gerrit commit 835d9fb8c9d9ba39bc7b7f01c8f4bed627243a8e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 18:03:18 2015 -0700 ridiculously random ramblings Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 2 +- src/cpu/x86/Makefile.inc | 6 +----- src/cpu/x86/smm/Makefile.inc | 12 ++---------- src/lib/Makefile.inc | 8 ++++---- 4 files changed, 8 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d5b320f..5188e6f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -259,7 +259,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) target-objcopy=-O elf32-i386 -B i386 endif ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_64),y) -target-objcopy=-O elf64-x86_64 -B x86_64 +target-objcopy=-O elf64-x86-64 -B i386:x86-64 endif define ramstage-objs_aml_template diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9ec0768..fb9ea2d 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -30,8 +30,4 @@ $(SIPI_BIN): $(SIPI_RMOD) $(SIPI_BIN).ramstage.manual: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) -else - cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) -endif + cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 2e61018..adf9b38 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -38,11 +38,7 @@ $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) # ELF symbol names. $(obj)/cpu/x86/smm/smm.ramstage.manual: $(obj)/cpu/x86/smm/smm @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) -else - cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) -endif + cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) ifeq ($(CONFIG_SMM_TSEG),y) @@ -72,11 +68,7 @@ $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod $(obj)/cpu/x86/smm/smmstub.ramstage.manual: $(obj)/cpu/x86/smm/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) -else - cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) -endif + cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) # C-based SMM handler. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index bda7586..89a29d9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -94,6 +94,7 @@ romstage-y += compute_ip_checksum.c ifeq ($(CONFIG_COMPILER_GCC),y) romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c +smm-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c @@ -162,11 +163,10 @@ ramstage-y += region.c romstage-y += boot_device.c ramstage-y += boot_device.c -smm-y += region.c +smm-y += region.c mem_pool.c smm-y += boot_device.c -smm-y += fmap.c -smm-y += cbfs.c memcmp.c -smm-$(CONFIG_COMPILER_GCC) += gcc.c +smm-y += fmap.c memcmp.c +smm-y += cbfs.c bootblock-y += version.c romstage-y += version.c

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New patch to review for coreboot: Move function/data sections to common CFLAGS
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11105 -gerrit commit acafc78e88380a3f98c307626ba1b67a9f4a122f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 31 13:50:03 2015 -0700 Move function/data sections to common CFLAGS Instead of adding -ffunction-sections and -fdata-sections to every architecture, just add it to CFLAGS_common, thus making sure that new architectures will pick it up automatically. Change-Id: I38e878851226565b7791d05e222cb4e502e0c8a3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 3 ++- toolchain.inc | 15 +++++---------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 14fa990..a29ee98 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -270,6 +270,8 @@ CFLAGS_common += -pipe -g -nostdinc CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS_common += -Wstrict-aliasing -Wshadow +CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +CFLAGS_common += -ffunction-sections -fdata-sections ifeq ($(CONFIG_COMPILER_GCC),y) # cf. commit f69a99db (coreboot: x86: enable gc-sections) @@ -279,7 +281,6 @@ endif ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror endif -CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer ifneq ($(GDB_DEBUG),) CFLAGS_common += -Og else diff --git a/toolchain.inc b/toolchain.inc index eea0560..195ed77 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -62,16 +62,11 @@ ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv ARCHDIR-mips := mips -CFLAGS_arm += -ffunction-sections -fdata-sections - -CFLAGS_arm64 += -ffunction-sections -fdata-sections -mgeneral-regs-only - -CFLAGS_mips += -mips32r2 -G 0 -ffunction-sections -fdata-sections -CFLAGS_mips += -mno-abicalls -fno-pic - -CFLAGS_x86_32 += -ffunction-sections -fdata-sections -CFLAGS_riscv += -ffunction-sections -fdata-sections - +CFLAGS_arm += +CFLAGS_arm64 += -mgeneral-regs-only +CFLAGS_mips += -mips32r2 -G 0 -mno-abicalls -fno-pic +CFLAGS_riscv += +CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone # Some boards only provide 2K stacks, so storing lots of data there leads to

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Patch set updated for coreboot: break lots of boards
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10594 -gerrit commit c21161961c245c5a3285cbd27772ac6aa68f5e99 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:05:13 2015 -0700 break lots of boards Enable 64bit compilation for AGESA boards :-) Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 282e1ed..45e1d63 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

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Patch set updated for coreboot: f14: Increase AP stack to 8k on 64bit
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11025 -gerrit commit 2c5cdc2a6801056ef4cfad3e6b52b97f86f5a07d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 21 14:37:13 2015 -0700 f14: Increase AP stack to 8k on 64bit This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 2104c27..8f395ce 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ +CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ +#else CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

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coreboot-gerrit July 2015