coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: vendorcode: Use cross archiver for libagesa.a on AMD f14
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10593 -gerrit commit f813b4e0b07c73a9fa87a6f4dfa2ca85716bc38e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:03:19 2015 -0700 vendorcode: Use cross archiver for libagesa.a on AMD f14 Change-Id: I61a9f65a1ac4c95096d0ff071a95984cf219caa8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index ba6a30e..a5f7561 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -332,7 +332,7 @@ libagesa-y += Proc/Mem/Main/mu.c $(obj)/libagesa.fam14.a: $$(libagesa-objs) @printf " AGESA $(subst $(obj)/,,$(@))\n" - ar rcs $@ $+ + $(AR_romstage) rcs $@ $+ romstage-libs += $(obj)/libagesa.fam14.a ramstage-libs += $(obj)/libagesa.fam14.a

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Patch set updated for coreboot: superio: use common x86 code on x86-64
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10592 -gerrit commit 16e737fb6dd0ff0f9abd7ec7beb1a5fbe547b7af Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:02:24 2015 -0700 superio: use common x86 code on x86-64 Change-Id: I2ddb5a8b183b21cbd3c3b22c537b815e86bd4738 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/superio/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index de0908d..0c5445a 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -29,3 +29,4 @@ subdirs-y += via subdirs-y += winbond ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += common/conf_mode.c +ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += common/conf_mode.c

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Patch set updated for coreboot: break lots of boards
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10594 -gerrit commit 84d67243bbd514f86d2a353084825006fd623804 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:05:13 2015 -0700 break lots of boards Enable 64bit compilation for AGESA boards :-) Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 282e1ed..45e1d63 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

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Patch set updated for coreboot: x86: Port x86 over to compile cleanly with x86-64
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10586 -gerrit commit 76880e7fc795e9ac5aa3425ac310d52cd04bea01 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:23:48 2015 -0700 x86: Port x86 over to compile cleanly with x86-64 Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Makefile.inc | 4 + src/arch/x86/boot/boot.c | 68 ++++++++++++-- src/arch/x86/boot/gdt.c | 8 +- src/arch/x86/boot/mpspec.c | 5 +- src/arch/x86/boot/wakeup.S | 5 + src/arch/x86/include/arch/cpu.h | 8 +- src/arch/x86/include/arch/rom_segs.h | 1 + src/arch/x86/include/arch/stages.h | 4 + src/arch/x86/lib/c_start.S | 171 +++++++++++++++++++++++++++-------- src/arch/x86/lib/cpu.c | 4 + src/arch/x86/lib/cpu_common.c | 9 ++ src/arch/x86/lib/ebda.c | 4 +- src/arch/x86/lib/exception.c | 6 +- src/arch/x86/lib/pci_ops_mmconf.c | 2 +- 14 files changed, 243 insertions(+), 56 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4c00162..7e10acb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -125,7 +125,11 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +else + $(LD_bootblock) -m elf_x86_64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +endif endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index d86a6c3..8600471 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -39,17 +39,64 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" +#ifdef __x86_64__ + /* switch back to 32-bit mode */ + " push %4\n\t" + " push %3\n\t" + " push %2\n\t" + " push %1\n\t" + " push %0\n\t" + + ".intel_syntax noprefix\n\t" + /* use iret to switch to 32-bit code segment */ + " xor rax,rax\n\t" + " mov ax, ss\n\t" + " push rax\n\t" + " mov rax, rsp\n\t" + " add rax, 8\n\t" + " push rax\n\t" + " pushfq\n\t" + " push 0x10\n\t" + " lea rax,[rip+3]\n\t" + " push rax\n\t" + " iretq\n\t" + ".code32\n\t" + /* disable paging */ + " mov eax, cr0\n\t" + " btc eax, 31\n\t" + " mov cr0, eax\n\t" + /* disable long mode */ + " mov ecx, 0xC0000080\n\t" + " rdmsr\n\t" + " btc eax, 8\n\t" + " wrmsr\n\t" + + " pop eax\n\t" + " add esp, 4\n\t" + " pop ebx\n\t" + " add esp, 4\n\t" + " pop ecx\n\t" + + " add esp, 4\n\t" + " pop edx\n\t" + " add esp, 4\n\t" + " pop esi\n\t" + " add esp, 4\n\t" + + ".att_syntax prefix\n\t" +#endif + /* Save the callee save registers... */ " pushl %%esi\n\t" " pushl %%edi\n\t" " pushl %%ebx\n\t" /* Save the parameters I was passed */ - " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ - " pushl %1\n\t" /* 12 buffer */ - " pushl %2\n\t" /* 8 lb_size */ - " pushl %3\n\t" /* 4 entry */ - " pushl %4\n\t" /* 0 elf_boot_notes */ + " pushl $0\n\t" /* 20 adjust */ + " pushl %%eax\n\t" /* 16 lb_start */ + " pushl %%ebx\n\t" /* 12 buffer */ + " pushl %%ecx\n\t" /* 8 lb_size */ + " pushl %%edx\n\t" /* 4 entry */ + " pushl %%esi\n\t" /* 0 elf_boot_notes */ /* Compute the adjustment */ " xorl %%eax, %%eax\n\t" " subl 16(%%esp), %%eax\n\t" @@ -115,7 +162,9 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " popl %%ebx\n\t" " popl %%edi\n\t" " popl %%esi\n\t" - +#ifdef __x86_64__ + ".code64\n\t" +#endif :: "ri" (lb_start), "ri" (buffer), "ri" (lb_size), "ri" (entry), @@ -140,7 +189,12 @@ void arch_prog_run(struct prog *prog) if (ENV_RAMSTAGE) try_payload(prog); __asm__ volatile ( +#ifdef __x86_64__ + "jmp *%%rdi\n" +#else "jmp *%%edi\n" +#endif + :: "D"(prog_entry(prog)) ); } diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 44156ea..a21fab2 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -26,7 +26,11 @@ /* i386 lgdt argument */ struct gdtarg { u16 limit; +#ifdef __x86_64__ + u64 base; +#else u32 base; +#endif } __attribute__((packed)); /* Copy GDT to new location and reload it. @@ -35,7 +39,7 @@ struct gdtarg { static void move_gdt(int is_recovery) { void *newgdt; - u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; + u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt; struct gdtarg gdtarg; newgdt = cbmem_find(CBMEM_ID_GDT); @@ -49,7 +53,7 @@ static void move_gdt(int is_recovery) memcpy((void*)newgdt, &gdt, num_gdt_bytes); } - gdtarg.base = (u32)newgdt; + gdtarg.base = (uintptr_t)newgdt; gdtarg.limit = num_gdt_bytes - 1; __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 4474d7c..1a0ac31 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -73,7 +73,7 @@ static unsigned char smp_compute_checksum(void *v, int len) return checksum; } -static void *smp_write_floating_table_physaddr(u32 addr, u32 mpf_physptr, unsigned int virtualwire) +static void *smp_write_floating_table_physaddr(uintptr_t addr, uintptr_t mpf_physptr, unsigned int virtualwire) { struct intel_mp_floating *mf; void *v; @@ -591,6 +591,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)tmp - (unsigned int)v); + printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - + (uintptr_t)v)); return (unsigned long)tmp; } diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a614b55..38d6ea4 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -24,7 +24,12 @@ /* CR0 bits */ #define PE (1 << 0) +#ifdef __x86_64__ + .code64 +#else .code32 +#endif + .globl __wakeup __wakeup: /* First prepare the jmp to the resume vector */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 851b58d..5c371d9 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -179,8 +179,14 @@ struct cpu_info { static inline struct cpu_info *cpu_info(void) { struct cpu_info *ci; - __asm__("andl %%esp,%0; " + __asm__( +#ifdef __x86_64__ + "and %%rsp,%0; " + "or %2, %0 " +#else + "andl %%esp,%0; " "orl %2, %0 " +#endif :"=r" (ci) : "0" (~(CONFIG_STACK_SIZE - 1)), "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h index 8c00eb3..3b3711b 100644 --- a/src/arch/x86/include/arch/rom_segs.h +++ b/src/arch/x86/include/arch/rom_segs.h @@ -3,5 +3,6 @@ #define ROM_CODE_SEG 0x08 #define ROM_DATA_SEG 0x10 +#define ROM_CODE_SEG64 0x18 #endif /* ROM_SEGS_H */ diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 80df8e2..dfdb592 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -27,7 +27,11 @@ void asmlinkage copy_and_run(void); static inline void stage_exit(void *entry) { __asm__ volatile ( +#ifdef __x86_64__ + "jmp *%%rdi\n" +#else "jmp *%%edi\n" +#endif :: "D"(entry) ); } diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index dbed123..582966b 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -17,20 +17,30 @@ thread_stacks: #endif .section ".text._start", "ax", @progbits +#ifdef __x86_64__ + .code64 +#else .code32 +#endif .globl _start .globl __rmodule_entry __rmodule_entry: _start: cli lgdt %cs:gdtaddr +#ifndef __x86_64__ ljmp $0x10, $1f +#endif 1: movl $0x18, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss movl %eax, %fs movl %eax, %gs +#ifdef __x86_64__ + mov $0x48, %ecx + call SetCodeSelector +#endif post_code(POST_ENTRY_C_START) /* post 13 */ @@ -54,11 +64,11 @@ _start: #if CONFIG_COOP_MULTITASKING /* Push the thread pointer. */ - pushl $0 + push $0 #endif /* Push the cpu index and struct cpu */ - pushl $0 - pushl $0 + push $0 + push $0 /* Initialize the Interrupt Descriptor table */ leal _idt, %edi @@ -76,7 +86,11 @@ _start: jne 1b /* Load the Interrupt descriptor table */ +#ifndef __x86_64__ lidt idtarg +#else + // FIXME port table to x64 - lidt idtarg +#endif /* * Now we are finished. Memory is up, data is copied and @@ -97,122 +111,150 @@ _start: jmp .Lhlt vec0: - pushl $0 /* error code */ - pushl $0 /* vector */ + push $0 /* error code */ + push $0 /* vector */ jmp int_hand vec1: - pushl $0 /* error code */ - pushl $1 /* vector */ + push $0 /* error code */ + push $1 /* vector */ jmp int_hand vec2: - pushl $0 /* error code */ - pushl $2 /* vector */ + push $0 /* error code */ + push $2 /* vector */ jmp int_hand vec3: - pushl $0 /* error code */ - pushl $3 /* vector */ + push $0 /* error code */ + push $3 /* vector */ jmp int_hand vec4: - pushl $0 /* error code */ - pushl $4 /* vector */ + push $0 /* error code */ + push $4 /* vector */ jmp int_hand vec5: - pushl $0 /* error code */ - pushl $5 /* vector */ + push $0 /* error code */ + push $5 /* vector */ jmp int_hand vec6: - pushl $0 /* error code */ - pushl $6 /* vector */ + push $0 /* error code */ + push $6 /* vector */ jmp int_hand vec7: - pushl $0 /* error code */ - pushl $7 /* vector */ + push $0 /* error code */ + push $7 /* vector */ jmp int_hand vec8: /* error code */ - pushl $8 /* vector */ + push $8 /* vector */ jmp int_hand .word 0x9090 vec9: - pushl $0 /* error code */ - pushl $9 /* vector */ + push $0 /* error code */ + push $9 /* vector */ jmp int_hand vec10: /* error code */ - pushl $10 /* vector */ + push $10 /* vector */ jmp int_hand .word 0x9090 vec11: /* error code */ - pushl $11 /* vector */ + push $11 /* vector */ jmp int_hand .word 0x9090 vec12: /* error code */ - pushl $12 /* vector */ + push $12 /* vector */ jmp int_hand .word 0x9090 vec13: /* error code */ - pushl $13 /* vector */ + push $13 /* vector */ jmp int_hand .word 0x9090 vec14: /* error code */ - pushl $14 /* vector */ + push $14 /* vector */ jmp int_hand .word 0x9090 vec15: - pushl $0 /* error code */ - pushl $15 /* vector */ + push $0 /* error code */ + push $15 /* vector */ jmp int_hand vec16: - pushl $0 /* error code */ - pushl $16 /* vector */ + push $0 /* error code */ + push $16 /* vector */ jmp int_hand vec17: /* error code */ - pushl $17 /* vector */ + push $17 /* vector */ jmp int_hand .word 0x9090 vec18: - pushl $0 /* error code */ - pushl $18 /* vector */ + push $0 /* error code */ + push $18 /* vector */ jmp int_hand vec19: - pushl $0 /* error code */ - pushl $19 /* vector */ + push $0 /* error code */ + push $19 /* vector */ jmp int_hand int_hand: - /* At this point on the stack there is: + /* At this point, on x86-32, on the stack there is: * 0(%esp) vector * 4(%esp) error code * 8(%esp) eip * 12(%esp) cs * 16(%esp) eflags */ +#ifdef __x86_64__ + push %rdi + push %rsi + push %rbp + /* Original stack pointer */ + lea 32(%rsp), %rbp + push %rbp + push %rbx + push %rdx + push %rcx + push %rax + + push %rsp /* Pointer to structure on the stack */ + call x86_exception + pop %rax /* Drop the pointer */ + + pop %rax + pop %rcx + pop %rdx + pop %rbx + pop %rbp /* Ignore saved %rsp value */ + pop %rbp + pop %rsi + pop %rdi + + add $8, %rsp /* pop of the vector and error code */ +#else pushl %edi pushl %esi pushl %ebp + /* Original stack pointer */ leal 32(%esp), %ebp pushl %ebp @@ -235,6 +277,7 @@ int_hand: popl %edi addl $8, %esp /* pop of the vector and error code */ +#endif iret @@ -242,21 +285,33 @@ int_hand: .globl gdb_stub_breakpoint gdb_stub_breakpoint: +#ifdef __x86_64__ + pop %rax /* Return address */ + pushfl + push %cs + push %rax /* Return address */ + push $0 /* No error code */ + push $32 /* vector 32 is user defined */ +#else popl %eax /* Return address */ pushfl pushl %cs pushl %eax /* Return address */ pushl $0 /* No error code */ pushl $32 /* vector 32 is user defined */ +#endif jmp int_hand - #endif .globl gdt, gdt_end, idtarg gdtaddr: .word gdt_end - gdt - 1 +#ifdef __x86_64__ + .quad gdt +#else .long gdt /* we know the offset */ +#endif .data @@ -287,7 +342,11 @@ gdt: /* selgdt 0x18, flat data segment */ .word 0xffff, 0x0000 +#ifdef __x86_64__ + .byte 0x00, 0x92, 0xcf, 0x00 +#else .byte 0x00, 0x93, 0xcf, 0x00 +#endif /* selgdt 0x20, unused */ .word 0x0000, 0x0000 /* dummy */ @@ -312,6 +371,12 @@ gdt: /* selgdt 0x40, flat code segment 16 bit */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + +#ifdef __x86_64__ + /* selgdt 0x48, flat x64 code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 +#endif gdt_end: idtarg: @@ -322,5 +387,35 @@ _idt: .fill 20, 8, 0 # idt is uninitialized _idt_end: +#ifdef __x86_64__ +SetCodeSelector: +.intel_syntax noprefix + + # save rsp because iret will align it to a 16 byte boundary + mov rdx, rsp + + # use iret to jump to a 64-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov ax, ss # need to push ss.. + push rax # push ss instuction not valid in x64 mode, so use ax + push rsp + pushfq + push rcx # cx is code segment selector from caller + mov rax, offset setCodeSelectorLongJump + push rax + + # the iret will continue at next instruction, with the new cs value loaded + iretq + +setCodeSelectorLongJump: + # restore rsp, it might not have been 16-byte aligned on entry + mov rsp, rdx + ret +.att_syntax prefix + + .previous +.code64 +#else .previous .code32 +#endif diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index db72695..3eb7b94 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -10,6 +10,7 @@ #include <device/device.h> #include <smp/spinlock.h> +#ifndef __x86_64__ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -78,6 +79,7 @@ static int deep_magic_nexgen_probe(void) : "=a" (ret) : : "cx", "dx" ); return ret; } +#endif /* List of cpu vendor strings along with their normalized * id values. @@ -131,6 +133,7 @@ static void identify_cpu(struct device *cpu) vendor_name[0] = '\0'; /* Unset */ +#ifndef __x86_64__ /* Find the id and vendor_name */ if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ @@ -148,6 +151,7 @@ static void identify_cpu(struct device *cpu) memcpy(vendor_name, "NexGenDriven", 13); } } +#endif if (cpu_have_cpuid()) { int cpuid_level; struct cpuid_result result; diff --git a/src/arch/x86/lib/cpu_common.c b/src/arch/x86/lib/cpu_common.c index 6c5561d..af0ab2a 100644 --- a/src/arch/x86/lib/cpu_common.c +++ b/src/arch/x86/lib/cpu_common.c @@ -10,6 +10,7 @@ #include <device/device.h> #include <smp/spinlock.h> +#ifndef __x86_64__ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -37,6 +38,14 @@ int cpu_have_cpuid(void) return flag_is_changeable_p(X86_EFLAGS_ID); } +#else + +int cpu_have_cpuid(void) +{ + return 1; +} +#endif + int cpu_cpuid_extended_level(void) { return cpuid_eax(0x80000000); diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c index 6089578..47dfbdb 100644 --- a/src/arch/x86/lib/ebda.c +++ b/src/arch/x86/lib/ebda.c @@ -40,8 +40,8 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) write16(X86_EBDA_SEGMENT, ebda_segment); /* Set up EBDA */ - memset((void *)(ebda_segment << 4), 0, ebda_size); - write16((void*)(ebda_segment << 4), (ebda_size >> 10)); + memset((void *)((uintptr_t)ebda_segment << 4), 0, ebda_size); + write16((void*)((uintptr_t)ebda_segment << 4), (ebda_size >> 10)); } void setup_default_ebda(void) diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index f64b2e7..65181e2 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -494,16 +494,16 @@ void x86_exception(struct eregs *info) info->error_code, info->eflags, info->eax, info->ebx, info->ecx, info->edx, info->edi, info->esi, info->ebp, info->esp); - u8 *code = (u8*)((u32)info->eip - (MDUMP_SIZE >>1)); + u8 *code = (u8*)((uintptr_t)info->eip - (MDUMP_SIZE >>1)); /* Align to 8-byte boundary please, and print eight bytes per row. * This is done to make DRAM burst timing/reordering errors more * evident from the looking at the dump */ - code = (u8*)((u32)code & ~0x7); + code = (u8*)((uintptr_t)code & ~0x7); int i; for(i = 0; i < MDUMP_SIZE; i++) { if( (i & 0x07) == 0 ) - printk(BIOS_EMERG, "\n%.8x:\t", (int)code + i ); + printk(BIOS_EMERG, "\n%p:\t", code + i); printk(BIOS_EMERG, "%.2x ", code[i]); } die(""); diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 4853f6b..e4fa128 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -10,7 +10,7 @@ */ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \ - ((void *)((CONFIG_MMCONF_BASE_ADDRESS |\ + ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\ (((SEGBUS) & 0xFFF) << 20) |\ (((DEVFN) & 0xFF) << 12) |\ ((WHERE) & 0xFFF)) & ~MASK))

1 0

Patch set updated for coreboot: device: Use x86 specific code on x86-64
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10584 -gerrit commit 8fba1125ea3de3fcc07e5085542040f8adfc8ded Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:19:14 2015 -0700 device: Use x86 specific code on x86-64 Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/device/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 3918115..1e19a7c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -10,6 +10,7 @@ ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c +ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c

1 0

Patch set updated for coreboot: prog_loader: Play nice with gc-sections
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10585 -gerrit commit b9d3add423ae89a5bd4ce6fc624a1ed844355030 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:19:50 2015 -0700 prog_loader: Play nice with gc-sections This is the wrong fix I'm sure, but it got me a bit further Change-Id: I75518149b53c24eda4b985b0fef856447e196dec Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/lib/prog_loaders.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ec5eeb8..7c00aba 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -121,6 +121,8 @@ fail: die("Ramstage was not loaded!\n"); } +#ifdef __RAMSTAGE__ // gc-sections should take care of this + static struct prog global_payload = PROG_INIT(ASSET_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); @@ -170,3 +172,5 @@ void payload_run(void) prog_run(payload); } + +#endif

1 0

Patch set updated for coreboot: SB800: Port to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10582 -gerrit commit 2e89279770bc2b7cfdbeace74f919c874ba7fb35 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:17:38 2015 -0700 SB800: Port to 64bit Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/southbridge/amd/cimx/sb800/fadt.c | 25 +++++++++++++++++++------ src/southbridge/amd/cimx/sb800/late.c | 8 ++++---- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 70173b6..d8fdd6f 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ @@ -153,10 +161,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; +#ifdef __x86_64__ + fadt->x_firmware_ctl_h = ((uintptr_t)facs) >> 32; +#endif + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; +#ifdef __x86_64__ + fadt->x_dsdt_h = ((uintptr_t)dsdt) >> 32; +#endif fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ada673..01900fe 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -108,15 +108,15 @@ static void ahci_raid_init(struct device *dev) bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); - caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = *(volatile u32 *)((uintptr_t)bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + ports= *(volatile u32 *)((uintptr_t)bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); + val = *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL); if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; } dev->command |= PCI_COMMAND_MASTER;

1 0

Patch set updated for coreboot: Port Fam14 northbridge code to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10583 -gerrit commit 0bd5fd9f7538e963575fef53a9ef7790e859d4b0 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:18:09 2015 -0700 Port Fam14 northbridge code to 64bit Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/northbridge/amd/agesa/family14/northbridge.c | 6 +++--- src/northbridge/amd/agesa/oem_s3.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fcc0d87..691fdf6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -529,7 +529,7 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); + printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); unsigned long mmio_basek; u32 pci_tolm; @@ -741,11 +741,11 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index dfc1ebc..2897e39 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -39,7 +39,7 @@ typedef enum { #error "Please increase the value of S3_DATA_SIZE" #endif -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) +static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len) { /* FIXME: Find file from CBFS. */ u32 s3_data = CONFIG_S3_DATA_POS; @@ -65,7 +65,7 @@ static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) { AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock; - u32 pos, size; + uintptr_t pos, size; get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); @@ -120,7 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; u8 MTRRStorage[S3_DATA_MTRR_SIZE]; u32 MTRRStorageSize = 0; - u32 pos, size; + uintptr_t pos, size; if (HIGH_ROMSTAGE_STACK_SIZE) cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); @@ -151,7 +151,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) const void *OemS3Saved_MTRR_Storage(void) { - u32 pos, size; + uintptr_t pos, size; get_s3nv_data(S3DataTypeMTRR, &pos, &size); if (!size) return NULL;

1 0

Patch set updated for coreboot: SB800: Port to 64bit
by Stefan Reinauer 18 Jun '15

18 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10582 -gerrit commit d3215a087d6201f2f8ca30cdeec27e39ac617d18 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:17:38 2015 -0700 SB800: Port to 64bit Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/southbridge/amd/cimx/sb800/fadt.c | 20 ++++++++++++++------ src/southbridge/amd/cimx/sb800/late.c | 8 ++++---- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 70173b6..6a565b8 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_WARN, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_WARN, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ @@ -153,10 +161,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ada673..01900fe 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -108,15 +108,15 @@ static void ahci_raid_init(struct device *dev) bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); - caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = *(volatile u32 *)((uintptr_t)bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + ports= *(volatile u32 *)((uintptr_t)bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); + val = *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL); if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; } dev->command |= PCI_COMMAND_MASTER;

1 0

Patch set updated for coreboot: x86: Port x86 over to compile cleanly with x86-64
by Stefan Reinauer 18 Jun '15

18 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10586 -gerrit commit aab689b85ff1115da6a34d89a9fcdfd2cf7d52c7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:23:48 2015 -0700 x86: Port x86 over to compile cleanly with x86-64 Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Makefile.inc | 4 + src/arch/x86/boot/boot.c | 68 ++++++++++++-- src/arch/x86/boot/gdt.c | 8 +- src/arch/x86/boot/mpspec.c | 5 +- src/arch/x86/boot/wakeup.S | 5 ++ src/arch/x86/include/arch/cpu.h | 8 +- src/arch/x86/include/arch/rom_segs.h | 1 + src/arch/x86/include/arch/stages.h | 4 + src/arch/x86/lib/c_start.S | 170 +++++++++++++++++++++++++++-------- src/arch/x86/lib/cpu.c | 4 + src/arch/x86/lib/cpu_common.c | 9 ++ src/arch/x86/lib/ebda.c | 4 +- src/arch/x86/lib/exception.c | 6 +- src/arch/x86/lib/pci_ops_mmconf.c | 2 +- 14 files changed, 242 insertions(+), 56 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4c00162..7e10acb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -125,7 +125,11 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +else + $(LD_bootblock) -m elf_x86_64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +endif endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index d86a6c3..8600471 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -39,17 +39,64 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" +#ifdef __x86_64__ + /* switch back to 32-bit mode */ + " push %4\n\t" + " push %3\n\t" + " push %2\n\t" + " push %1\n\t" + " push %0\n\t" + + ".intel_syntax noprefix\n\t" + /* use iret to switch to 32-bit code segment */ + " xor rax,rax\n\t" + " mov ax, ss\n\t" + " push rax\n\t" + " mov rax, rsp\n\t" + " add rax, 8\n\t" + " push rax\n\t" + " pushfq\n\t" + " push 0x10\n\t" + " lea rax,[rip+3]\n\t" + " push rax\n\t" + " iretq\n\t" + ".code32\n\t" + /* disable paging */ + " mov eax, cr0\n\t" + " btc eax, 31\n\t" + " mov cr0, eax\n\t" + /* disable long mode */ + " mov ecx, 0xC0000080\n\t" + " rdmsr\n\t" + " btc eax, 8\n\t" + " wrmsr\n\t" + + " pop eax\n\t" + " add esp, 4\n\t" + " pop ebx\n\t" + " add esp, 4\n\t" + " pop ecx\n\t" + + " add esp, 4\n\t" + " pop edx\n\t" + " add esp, 4\n\t" + " pop esi\n\t" + " add esp, 4\n\t" + + ".att_syntax prefix\n\t" +#endif + /* Save the callee save registers... */ " pushl %%esi\n\t" " pushl %%edi\n\t" " pushl %%ebx\n\t" /* Save the parameters I was passed */ - " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ - " pushl %1\n\t" /* 12 buffer */ - " pushl %2\n\t" /* 8 lb_size */ - " pushl %3\n\t" /* 4 entry */ - " pushl %4\n\t" /* 0 elf_boot_notes */ + " pushl $0\n\t" /* 20 adjust */ + " pushl %%eax\n\t" /* 16 lb_start */ + " pushl %%ebx\n\t" /* 12 buffer */ + " pushl %%ecx\n\t" /* 8 lb_size */ + " pushl %%edx\n\t" /* 4 entry */ + " pushl %%esi\n\t" /* 0 elf_boot_notes */ /* Compute the adjustment */ " xorl %%eax, %%eax\n\t" " subl 16(%%esp), %%eax\n\t" @@ -115,7 +162,9 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " popl %%ebx\n\t" " popl %%edi\n\t" " popl %%esi\n\t" - +#ifdef __x86_64__ + ".code64\n\t" +#endif :: "ri" (lb_start), "ri" (buffer), "ri" (lb_size), "ri" (entry), @@ -140,7 +189,12 @@ void arch_prog_run(struct prog *prog) if (ENV_RAMSTAGE) try_payload(prog); __asm__ volatile ( +#ifdef __x86_64__ + "jmp *%%rdi\n" +#else "jmp *%%edi\n" +#endif + :: "D"(prog_entry(prog)) ); } diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 44156ea..a21fab2 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -26,7 +26,11 @@ /* i386 lgdt argument */ struct gdtarg { u16 limit; +#ifdef __x86_64__ + u64 base; +#else u32 base; +#endif } __attribute__((packed)); /* Copy GDT to new location and reload it. @@ -35,7 +39,7 @@ struct gdtarg { static void move_gdt(int is_recovery) { void *newgdt; - u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; + u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt; struct gdtarg gdtarg; newgdt = cbmem_find(CBMEM_ID_GDT); @@ -49,7 +53,7 @@ static void move_gdt(int is_recovery) memcpy((void*)newgdt, &gdt, num_gdt_bytes); } - gdtarg.base = (u32)newgdt; + gdtarg.base = (uintptr_t)newgdt; gdtarg.limit = num_gdt_bytes - 1; __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 4474d7c..1a0ac31 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -73,7 +73,7 @@ static unsigned char smp_compute_checksum(void *v, int len) return checksum; } -static void *smp_write_floating_table_physaddr(u32 addr, u32 mpf_physptr, unsigned int virtualwire) +static void *smp_write_floating_table_physaddr(uintptr_t addr, uintptr_t mpf_physptr, unsigned int virtualwire) { struct intel_mp_floating *mf; void *v; @@ -591,6 +591,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)tmp - (unsigned int)v); + printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - + (uintptr_t)v)); return (unsigned long)tmp; } diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a614b55..38d6ea4 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -24,7 +24,12 @@ /* CR0 bits */ #define PE (1 << 0) +#ifdef __x86_64__ + .code64 +#else .code32 +#endif + .globl __wakeup __wakeup: /* First prepare the jmp to the resume vector */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 851b58d..5c371d9 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -179,8 +179,14 @@ struct cpu_info { static inline struct cpu_info *cpu_info(void) { struct cpu_info *ci; - __asm__("andl %%esp,%0; " + __asm__( +#ifdef __x86_64__ + "and %%rsp,%0; " + "or %2, %0 " +#else + "andl %%esp,%0; " "orl %2, %0 " +#endif :"=r" (ci) : "0" (~(CONFIG_STACK_SIZE - 1)), "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h index 8c00eb3..3b3711b 100644 --- a/src/arch/x86/include/arch/rom_segs.h +++ b/src/arch/x86/include/arch/rom_segs.h @@ -3,5 +3,6 @@ #define ROM_CODE_SEG 0x08 #define ROM_DATA_SEG 0x10 +#define ROM_CODE_SEG64 0x18 #endif /* ROM_SEGS_H */ diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 80df8e2..dfdb592 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -27,7 +27,11 @@ void asmlinkage copy_and_run(void); static inline void stage_exit(void *entry) { __asm__ volatile ( +#ifdef __x86_64__ + "jmp *%%rdi\n" +#else "jmp *%%edi\n" +#endif :: "D"(entry) ); } diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index dbed123..e2c0d82 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -17,20 +17,30 @@ thread_stacks: #endif .section ".text._start", "ax", @progbits +#ifdef __x86_64__ + .code64 +#else .code32 +#endif .globl _start .globl __rmodule_entry __rmodule_entry: _start: cli lgdt %cs:gdtaddr +#ifndef __x86_64__ ljmp $0x10, $1f +#endif 1: movl $0x18, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss movl %eax, %fs movl %eax, %gs +#ifdef __x86_64__ + mov $0x48, %ecx + call SetCodeSelector +#endif post_code(POST_ENTRY_C_START) /* post 13 */ @@ -54,11 +64,11 @@ _start: #if CONFIG_COOP_MULTITASKING /* Push the thread pointer. */ - pushl $0 + push $0 #endif /* Push the cpu index and struct cpu */ - pushl $0 - pushl $0 + push $0 + push $0 /* Initialize the Interrupt Descriptor table */ leal _idt, %edi @@ -76,7 +86,11 @@ _start: jne 1b /* Load the Interrupt descriptor table */ +#ifndef __x86_64__ lidt idtarg +#else + // FIXME port table to x64 - lidt idtarg +#endif /* * Now we are finished. Memory is up, data is copied and @@ -97,122 +111,150 @@ _start: jmp .Lhlt vec0: - pushl $0 /* error code */ - pushl $0 /* vector */ + push $0 /* error code */ + push $0 /* vector */ jmp int_hand vec1: - pushl $0 /* error code */ - pushl $1 /* vector */ + push $0 /* error code */ + push $1 /* vector */ jmp int_hand vec2: - pushl $0 /* error code */ - pushl $2 /* vector */ + push $0 /* error code */ + push $2 /* vector */ jmp int_hand vec3: - pushl $0 /* error code */ - pushl $3 /* vector */ + push $0 /* error code */ + push $3 /* vector */ jmp int_hand vec4: - pushl $0 /* error code */ - pushl $4 /* vector */ + push $0 /* error code */ + push $4 /* vector */ jmp int_hand vec5: - pushl $0 /* error code */ - pushl $5 /* vector */ + push $0 /* error code */ + push $5 /* vector */ jmp int_hand vec6: - pushl $0 /* error code */ - pushl $6 /* vector */ + push $0 /* error code */ + push $6 /* vector */ jmp int_hand vec7: - pushl $0 /* error code */ - pushl $7 /* vector */ + push $0 /* error code */ + push $7 /* vector */ jmp int_hand vec8: /* error code */ - pushl $8 /* vector */ + push $8 /* vector */ jmp int_hand .word 0x9090 vec9: - pushl $0 /* error code */ - pushl $9 /* vector */ + push $0 /* error code */ + push $9 /* vector */ jmp int_hand vec10: /* error code */ - pushl $10 /* vector */ + push $10 /* vector */ jmp int_hand .word 0x9090 vec11: /* error code */ - pushl $11 /* vector */ + push $11 /* vector */ jmp int_hand .word 0x9090 vec12: /* error code */ - pushl $12 /* vector */ + push $12 /* vector */ jmp int_hand .word 0x9090 vec13: /* error code */ - pushl $13 /* vector */ + push $13 /* vector */ jmp int_hand .word 0x9090 vec14: /* error code */ - pushl $14 /* vector */ + push $14 /* vector */ jmp int_hand .word 0x9090 vec15: - pushl $0 /* error code */ - pushl $15 /* vector */ + push $0 /* error code */ + push $15 /* vector */ jmp int_hand vec16: - pushl $0 /* error code */ - pushl $16 /* vector */ + push $0 /* error code */ + push $16 /* vector */ jmp int_hand vec17: /* error code */ - pushl $17 /* vector */ + push $17 /* vector */ jmp int_hand .word 0x9090 vec18: - pushl $0 /* error code */ - pushl $18 /* vector */ + push $0 /* error code */ + push $18 /* vector */ jmp int_hand vec19: - pushl $0 /* error code */ - pushl $19 /* vector */ + push $0 /* error code */ + push $19 /* vector */ jmp int_hand int_hand: - /* At this point on the stack there is: + /* At this point, on x86-32, on the stack there is: * 0(%esp) vector * 4(%esp) error code * 8(%esp) eip * 12(%esp) cs * 16(%esp) eflags */ +#ifdef __x86_64__ + push %rdi + push %rsi + push %rbp + /* Original stack pointer */ + lea 32(%rsp), %rbp + push %rbp + push %rbx + push %rdx + push %rcx + push %rax + + push %rsp /* Pointer to structure on the stack */ + call x86_exception + pop %rax /* Drop the pointer */ + + pop %rax + pop %rcx + pop %rdx + pop %rbx + pop %rbp /* Ignore saved %rsp value */ + pop %rbp + pop %rsi + pop %rdi + + add $8, %rsp /* pop of the vector and error code */ +#else pushl %edi pushl %esi pushl %ebp + /* Original stack pointer */ leal 32(%esp), %ebp pushl %ebp @@ -235,6 +277,7 @@ int_hand: popl %edi addl $8, %esp /* pop of the vector and error code */ +#endif iret @@ -242,21 +285,33 @@ int_hand: .globl gdb_stub_breakpoint gdb_stub_breakpoint: +#ifdef __x86_64__ + pop %rax /* Return address */ + pushfl + push %cs + push %rax /* Return address */ + push $0 /* No error code */ + push $32 /* vector 32 is user defined */ +#else popl %eax /* Return address */ pushfl pushl %cs pushl %eax /* Return address */ pushl $0 /* No error code */ pushl $32 /* vector 32 is user defined */ +#endif jmp int_hand - #endif .globl gdt, gdt_end, idtarg gdtaddr: .word gdt_end - gdt - 1 +#ifdef __x86_64__ + .quad gdt +#else .long gdt /* we know the offset */ +#endif .data @@ -287,7 +342,11 @@ gdt: /* selgdt 0x18, flat data segment */ .word 0xffff, 0x0000 +#ifdef __x86_64__ + .byte 0x00, 0x92, 0xcf, 0x00 +#else .byte 0x00, 0x93, 0xcf, 0x00 +#endif /* selgdt 0x20, unused */ .word 0x0000, 0x0000 /* dummy */ @@ -312,6 +371,12 @@ gdt: /* selgdt 0x40, flat code segment 16 bit */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + +#ifdef __x86_64__ + /* selgdt 0x48, flat x64 code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 +#endif gdt_end: idtarg: @@ -322,5 +387,34 @@ _idt: .fill 20, 8, 0 # idt is uninitialized _idt_end: +SetCodeSelector: +.intel_syntax noprefix + + # save rsp because iret will align it to a 16 byte boundary + mov rdx, rsp + + # use iret to jump to a 64-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov ax, ss # need to push ss.. + push rax # push ss instuction not valid in x64 mode, so use ax + push rsp + pushfq + push rcx # cx is code segment selector from caller + mov rax, offset setCodeSelectorLongJump + push rax + + # the iret will continue at next instruction, with the new cs value loaded + iretq + +setCodeSelectorLongJump: + # restore rsp, it might not have been 16-byte aligned on entry + mov rsp, rdx + ret +.att_syntax prefix + .previous +#ifdef __x86_64__ +.code64 +#else .code32 +#endif diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index db72695..3eb7b94 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -10,6 +10,7 @@ #include <device/device.h> #include <smp/spinlock.h> +#ifndef __x86_64__ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -78,6 +79,7 @@ static int deep_magic_nexgen_probe(void) : "=a" (ret) : : "cx", "dx" ); return ret; } +#endif /* List of cpu vendor strings along with their normalized * id values. @@ -131,6 +133,7 @@ static void identify_cpu(struct device *cpu) vendor_name[0] = '\0'; /* Unset */ +#ifndef __x86_64__ /* Find the id and vendor_name */ if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ @@ -148,6 +151,7 @@ static void identify_cpu(struct device *cpu) memcpy(vendor_name, "NexGenDriven", 13); } } +#endif if (cpu_have_cpuid()) { int cpuid_level; struct cpuid_result result; diff --git a/src/arch/x86/lib/cpu_common.c b/src/arch/x86/lib/cpu_common.c index 6c5561d..af0ab2a 100644 --- a/src/arch/x86/lib/cpu_common.c +++ b/src/arch/x86/lib/cpu_common.c @@ -10,6 +10,7 @@ #include <device/device.h> #include <smp/spinlock.h> +#ifndef __x86_64__ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -37,6 +38,14 @@ int cpu_have_cpuid(void) return flag_is_changeable_p(X86_EFLAGS_ID); } +#else + +int cpu_have_cpuid(void) +{ + return 1; +} +#endif + int cpu_cpuid_extended_level(void) { return cpuid_eax(0x80000000); diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c index 6089578..47dfbdb 100644 --- a/src/arch/x86/lib/ebda.c +++ b/src/arch/x86/lib/ebda.c @@ -40,8 +40,8 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) write16(X86_EBDA_SEGMENT, ebda_segment); /* Set up EBDA */ - memset((void *)(ebda_segment << 4), 0, ebda_size); - write16((void*)(ebda_segment << 4), (ebda_size >> 10)); + memset((void *)((uintptr_t)ebda_segment << 4), 0, ebda_size); + write16((void*)((uintptr_t)ebda_segment << 4), (ebda_size >> 10)); } void setup_default_ebda(void) diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index f64b2e7..65181e2 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -494,16 +494,16 @@ void x86_exception(struct eregs *info) info->error_code, info->eflags, info->eax, info->ebx, info->ecx, info->edx, info->edi, info->esi, info->ebp, info->esp); - u8 *code = (u8*)((u32)info->eip - (MDUMP_SIZE >>1)); + u8 *code = (u8*)((uintptr_t)info->eip - (MDUMP_SIZE >>1)); /* Align to 8-byte boundary please, and print eight bytes per row. * This is done to make DRAM burst timing/reordering errors more * evident from the looking at the dump */ - code = (u8*)((u32)code & ~0x7); + code = (u8*)((uintptr_t)code & ~0x7); int i; for(i = 0; i < MDUMP_SIZE; i++) { if( (i & 0x07) == 0 ) - printk(BIOS_EMERG, "\n%.8x:\t", (int)code + i ); + printk(BIOS_EMERG, "\n%p:\t", code + i); printk(BIOS_EMERG, "%.2x ", code[i]); } die(""); diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 4853f6b..e4fa128 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -10,7 +10,7 @@ */ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \ - ((void *)((CONFIG_MMCONF_BASE_ADDRESS |\ + ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\ (((SEGBUS) & 0xFFF) << 20) |\ (((DEVFN) & 0xFF) << 12) |\ ((WHERE) & 0xFFF)) & ~MASK))

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coreboot-gerrit June 2015