the following patch was just integrated into master:
commit 75fcaf9e693824d2135223ed78132b7f28ee273e
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Apr 3 10:16:12 2015 +0200
build system: create proper dependency files
Tell gcc what to use as target part of the generated rule.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: Ie4814143337abb3cf1e9e8db7e96201a517a17b8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9285
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9285 for details.
-gerrit
the following patch was just integrated into master:
commit f1df82a458abfde8aa6d5d72c5f09c98870b0226
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Apr 3 10:12:40 2015 +0200
x86: rename ldscript_failover.ld to failover.ld
The ldscript_ prefix is redundant.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: I0f005c0c2abe2fdd6911a2c579cb7ec49ae5c0b7
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9284
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
See http://review.coreboot.org/9284 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9281
-gerrit
commit de5a54985d58aac475b32d28b6caaf866c179b68
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Dec 10 08:16:43 2014 -0800
broadwell: Enable turbo ratio if available
When turning up the CPU frequency set it to turbo if that is
a possibility. Also only set the frequency on the boot CPU
since that is all we need it on, this will allow the 1-core
turbo ratio.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I573eb7a507305814ec48cc2f624b8e6ddad43f84
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: d408c1b462983c682d61c6c447692391c2b52183
Original-Change-Id: Ib5ad746767ee0a56bc7e59de679a9342f053c0e5
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234401
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/cpu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 1f2ee0d..912f8ae 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -485,7 +485,10 @@ static void set_max_ratio(void)
perf_ctl.hi = 0;
/* Check for configurable TDP option */
- if (cpu_config_tdp_levels()) {
+ if (get_turbo_state() == TURBO_ENABLED) {
+ msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else if (cpu_config_tdp_levels()) {
/* Set to nominal TDP ratio */
msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
perf_ctl.lo = (msr.lo & 0xff) << 8;
@@ -587,9 +590,6 @@ static void cpu_core_init(device_t cpu)
/* Set energy policy */
set_energy_perf_bias(ENERGY_POLICY_NORMAL);
- /* Set Max Ratio */
- set_max_ratio();
-
/* Enable Turbo */
enable_turbo();
}
@@ -692,6 +692,9 @@ void broadwell_init_cpus(device_t dev)
printk(BIOS_ERR, "MP initialization failure.\n");
}
+ /* Set Max Ratio */
+ set_max_ratio();
+
/* Restore the default SMM region. */
restore_default_smm_area(smm_save_area);
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9280
-gerrit
commit 08e8659d7a8c0074885716e0776d1eadea1ab39a
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Thu Nov 20 16:56:44 2014 -0800
Broadwell: Pass TSC value to romstage_main
The romstage_main routine takes three parameters: bist, tsc_low and
tsc_hi. However in cache_as_ram.inc only the bist value is being
passed. This patch adds the two halves of the TSC value.
BRANCH=none
BUG=None
TEST=Build and run on Samus
Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831
Original-Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e
Original-Reviewed-on: https://chromium-review.googlesource.com/231173
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/broadwell/romstage/cache_as_ram.inc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 4e6cf09..a10ca4c 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -180,7 +180,13 @@ clear_mtrrs:
/* Restore the BIST result. */
movl %ebp, %eax
+
+ /* Build the call frame. */
movl %esp, %ebp
+ movd %mm1, %ebx
+ pushl %ebx
+ movd %mm0, %ebx
+ pushl %ebx
pushl %eax
before_romstage:
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9277
-gerrit
commit 998c0d7fd0b79830979d3f9feeaef223a50135a6
Author: Ben Zhang <benzh(a)chromium.org>
Date: Mon Nov 17 17:21:09 2014 -0800
samus: Set codec PDM clock output to 3MHz
Currently the rt5677 codec outputs 6MHz PDM clock which is
out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS
pin is pulled down to PGND with a 47k resistor, so the
expected PDM clock is 64*FS (~3MHz) according to its datasheet.
The corresponding kernel patch that adds the PDM clock config
option is https://chromium-review.googlesource.com/#/c/230303/
BUG=chrome-os-partner:33303
BRANCH=samus
TEST=flash coreboot with this patch and see PDM CLK went
from 6MHz to 3MHz on samus with a scope.
Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648
Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230344
Original-Reviewed-by: Dylan Reid <dgreid(a)chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/samus/acpi/mainboard.asl | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 39797e5..2b6cea0 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -170,6 +170,7 @@ Scope (\_SB.PCI0.I2C0)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
+ Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
Name (IN2, 0) /* IN2 not differential */
Name (OUT1, 1) /* LOUT1 differential */