coreboot-gerrit April 2015

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New patch to review for coreboot: d074843 utils: pool together single-file scripts into a single directory
by Stefan Tauner 06 Apr '15

06 Apr '15

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9322 -gerrit commit d07484398ab2ae2bacc0c5bcc34d3720634abd13 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Apr 6 12:40:17 2015 +0200 utils: pool together single-file scripts into a single directory This will most probably break things - do not commit yet! I want to get consensus about naming and what files to move at all before fixing anything. Shall we move gitconfig/ in there too? Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Change-Id: I17d3f622a9c64724fe3471a92c243e6bd87ff7ca --- util/acpi/acpidump-all | 50 ------- util/dtd_parser/dtd_parser.py | 213 --------------------------- util/exynos/fixed_cksum.py | 59 -------- util/exynos/variable_cksum.py | 59 -------- util/find_usbdebug/find_usbdebug.sh | 149 ------------------- util/genbuild_h/genbuild_h.sh | 64 -------- util/ipqheader/ipqheader.py | 130 ---------------- util/rockchip/LICENSE | 25 ---- util/rockchip/make_idb.py | 124 ---------------- util/scripts/acpidump-all | 50 +++++++ util/scripts/dtd_parser.py | 213 +++++++++++++++++++++++++++ util/scripts/exynos_fixed_cksum.py | 59 ++++++++ util/scripts/exynos_variable_cksum.py | 59 ++++++++ util/scripts/find_usbdebug.sh | 149 +++++++++++++++++++ util/scripts/genbuild_h.sh | 64 ++++++++ util/scripts/ipqheader.py | 130 ++++++++++++++++ util/scripts/rk_make_idb.py | 150 +++++++++++++++++++ util/scripts/xcompile | 269 ++++++++++++++++++++++++++++++++++ util/xcompile/xcompile | 269 ---------------------------------- 19 files changed, 1143 insertions(+), 1142 deletions(-) diff --git a/util/acpi/acpidump-all b/util/acpi/acpidump-all deleted file mode 100755 index aa73a15..0000000 --- a/util/acpi/acpidump-all +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/bash -# -# Copyright (C) 2007-2010 by coresystems GmbH -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA -# - -rm -rf out -mkdir out - -# walk through all ACPI tables with their addresses -# example: -# RSDT @ 0xcf6794ba -# we can not just dump the tables by their names because some -# machines have double ACPI tables - -acpidump | grep "@ 0x" | while read line -do - NAME=$( echo `echo $line|cut -f1 -d@` ) - FNAME=$( echo $NAME | sed s/\ /_/g |sed s/\!/b/g ) - ADDR=$( echo `echo $line|cut -f2 -d@` ) - if [ "${!FNAME}" == "" ]; then - eval $FNAME=0 - else - eval $FNAME=$(( ${!FNAME} + 1 )) - fi - printf "Processing table \"$NAME\" at $ADDR ... " - printf "${!FNAME} tables of that kind found before.\n" - - # acpidump -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.txt - acpidump -b -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.bin - if [ "`file -b out/$FNAME-$ADDR-${!FNAME}.bin`" != "ASCII text" ]; then - iasl -d out/$FNAME-$ADDR-${!FNAME}.bin &>/dev/null - else - printf "Skipping $NAME because it was not dumped correctly.\n\n" - fi - -done - diff --git a/util/dtd_parser/dtd_parser.py b/util/dtd_parser/dtd_parser.py deleted file mode 100755 index 23cc7e7..0000000 --- a/util/dtd_parser/dtd_parser.py +++ /dev/null @@ -1,213 +0,0 @@ -#!/usr/bin/python -# dtd_parser.py - DTD structure parser -# -# Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -''' -DTD string parser/generator. - -Detailed timing descriptor (DTD) is an 18 byte array describing video mode -(screen resolution, display properties, etc.) in EDID and used by Intel Option -ROM. Option ROM can support multiple video modes, specific mode is picked by -the BIOS through the appropriate Option ROM callback function. - -This program allows to interpret the 18 byte hex DTD dump, and/or modify -certain values and generate a new DTD. -''' - -import sys - -# -# The DTD array format description can be found in -# http://en.wikipedia.org/wiki/Extended_display_identification_data, (see the -# EDID Detailed Timing Descriptor section). -# -# The below dictionary describes how different DTD parameters are laid out in -# the array. Note that many parameters span multiple bit fields in the DTD. -# -# The keys in the dictionary are stings (field names), the values are tuples -# of either numbers or tri-tuples. If the element of the tuple is a number, it -# is the offset in DTD, and the entire byte is used in this field. If the -# element is a tri-tuple, its components are (DTD offset, bit shift, field -# width). -# -# The partial values are extracted from the DTD fields and concatenated -# together to form actual parameter value. -# - -dtd_descriptor = { - 'dclck' : (1, 0), - 'hor_active' : ((4, 4, 4), 2), - 'hor_blank' : ((4, 0, 4), 3), - 'vert_act' : ((7, 4, 4), 5), - 'vert_blank' : ((7, 0, 4), 6), - 'hsync_offset' : ((11, 6, 2), 8), - 'hsync_pulse_width' : ((11, 4, 2), 9), - 'vsync_offset' : ((11, 2, 2), (10, 4, 4)), - 'vsync_pulse_width' : ((11, 0, 2), (10, 0, 4)), - 'hor_image_size' : ((14, 4, 4), 12), - 'vert_image_size' : ((14, 0, 4), 13), - 'hor_border' : (15,), - 'vert_border' : (16,), - 'interlaced' : ((17, 7, 1),), - 'reserved' : ((17, 5, 2), (17, 0, 1)), - 'digital_separate' : ((17, 3, 2),), - 'vert_polarity' : ((17, 2, 1),), - 'hor_polarity' : ((17, 1, 1),), - } - -PREFIX = 'attr_' - -class DTD(object): - '''An object containing all DTD information. - - The attributes are created dynamically when the input DTD string is - parsed. For each element of the above dictionary two attributes are added: - - 'attr_<param>' to hold the actual parameter value - 'max_attr_<param>' to hold the maximum allowed value for this parameter. - ''' - - def __init__(self): - for name in dtd_descriptor: - setattr(self, PREFIX + name, 0) - - def init(self, sarray): - '''Initialize the object with values from a DTD array. - - Inputs: - - sarray: a string, an array of ASCII hex representations of the 18 DTD - bytes. - - Raises: implicitly raises ValueError or IndexError exceptions in case - the input string has less than 18 elements, or some of the - elements can not be converted to integer. - ''' - - harray = [int(x, 16) for x in sarray] - for name, desc in dtd_descriptor.iteritems(): - attr_value = 0 - total_width = 0 - for tup in desc: - if isinstance(tup, tuple): - offset, shift, width = tup - else: - offset, shift, width = tup, 0, 8 - - mask = (1 << width) - 1 - attr_value = (attr_value << width) + ( - (harray[offset] >> shift) & mask) - total_width += width - setattr(self, PREFIX + name, attr_value) - setattr(self, 'max_' + PREFIX + name, (1 << total_width) - 1) - - def __str__(self): - text = [] - for name in sorted(dtd_descriptor.keys()): - text.append('%20s: %d' % (name, getattr(self, PREFIX + name))) - return '\n'.join(text) - - def inhex(self): - '''Generate contents of the DTD as a 18 byte ASCII hex array.''' - - result = [0] * 18 - for name, desc in dtd_descriptor.iteritems(): - attr_value = getattr(self, PREFIX + name) - rdesc = list(desc) - rdesc.reverse() - for tup in rdesc: - if isinstance(tup, tuple): - offset, shift, width = tup - else: - offset, shift, width = tup, 0, 8 - - mask = (1 << width) - 1 - value = attr_value & mask - attr_value = attr_value >> width - result[offset] = (result[offset] & ~( - mask << shift)) | (value << shift) - - return ' '.join('%2.2x' % x for x in result) - - def handle_input(self, name): - '''Get user input and set a new parameter value if required. - - Display the parameter name, its current value, and prompt user for a - new value. - - If the user enters a dot, stop processing (return True). - - Empty user input means that this parameter does not have to change, - but the next parameter should be prompted. - - If input is non-empty, it is interpreted as a hex number, checked if - it fits the parameter and the new parameter value is set if checks - pass. - - Inputs: - - name - a string, parameter name, a key in dtd_descriptor - - Returns: - - Boolean, True meaning no more field are required to be modified, False - meaning that more field mods need to be prompted.. - ''' - - param = PREFIX + name - vmax = getattr(self, 'max_' + param) - new_value = raw_input('%s : %d ' % (name, getattr(self, param))) - if new_value == '': - return False - if new_value == '.': - return True - new_int = int(new_value) - if new_int > vmax: - print '%s exceeds maximum for %s (%d)' % (new_value, name, vmax) - else: - setattr(self, param, new_int) - return False - -def main(args): - if args[0] == '-m': - modify = True - base = 1 - else: - modify = False - base = 0 - - d = DTD() - d.init(args[base:]) - if modify: - for line in str(d).splitlines(): - if d.handle_input(line.split(':')[0].strip()): - break - print d - if modify: - print d.inhex() - - -if __name__ == '__main__': - try: - main(sys.argv[1:]) - except (ValueError, IndexError): - print """ -A string of 18 byte values in hex is required. -'-m' preceding the string will allow setting new parameter values. -""" - sys.exit(1) diff --git a/util/exynos/fixed_cksum.py b/util/exynos/fixed_cksum.py deleted file mode 100755 index 66da060..0000000 --- a/util/exynos/fixed_cksum.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python -# -# Copyright (C) 2013 Google Inc. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. - -""" -This utility computes and fills Exynos ROM checksum (for BL1 or BL2). -(Algorithm from U-Boot: tools/mkexynosspl.c) - -Input: IN OUT DATA_SIZE - -Output: - - IN padded out to DATA_SIZE, checksum at the end, written to OUT. -""" - -import struct -import sys - -def main(argv): - if len(argv) != 4: - exit('usage: %s IN OUT DATA_SIZE' % argv[0]) - - in_name, out_name = argv[1:3] - size = int(argv[3], 0) - checksum_format = "<I" - with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file: - data = in_file.read() - checksum_size = struct.calcsize(checksum_format) - data_size = size - checksum_size - assert len(data) <= data_size - checksum = struct.pack(checksum_format, sum(map(ord, data))) - out_file.write(data + bytearray(data_size - len(data)) + checksum) - - -if __name__ == '__main__': - main(sys.argv) diff --git a/util/exynos/variable_cksum.py b/util/exynos/variable_cksum.py deleted file mode 100755 index 75cdc74..0000000 --- a/util/exynos/variable_cksum.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python -# -# Copyright (C) 2013 Google Inc. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. - -""" -This utility computes and fills Exynos ROM checksum (for BL1 or BL2). -(Algorithm from U-Boot: tools/mkexynosspl.c) - -Input: IN OUT - -Output: - - Checksum header added to IN and written to OUT. - Header: uint32_t size, checksum, reserved[2]. -""" - -import struct -import sys - -def main(argv): - if len(argv) != 3: - exit('usage: %s IN OUT' % argv[0]) - - in_name, out_name = argv[1:3] - header_format = "<IIII" - with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file: - data = in_file.read() - header = struct.pack(header_format, - struct.calcsize(header_format) + len(data), - sum(map(ord, data)), - 0, 0) - out_file.write(header + data) - - -if __name__ == '__main__': - main(sys.argv) diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh deleted file mode 100755 index 2f82219..0000000 --- a/util/find_usbdebug/find_usbdebug.sh +++ /dev/null @@ -1,149 +0,0 @@ -#!/bin/sh - -# Copyright 2008 Carl-Daniel Hailfinger -# Copyright 2015 Stefan Tauner -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License version 2 as -# published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc. - -LANG=C -# Some tools emmit errors that don't matter (bugs in lspci/PCI firmware and lsusb). -# To shown them anyway (e.g. for debugging) comment next line. -exec 2>/dev/null - -if [ "$1" = "-h" ]; then - printf "Usage: $0 [-h | path to dmesg log] - -This script tries to find USB ports compatible with USB2/EHCI debug devices and -helps you to find their physical locations. To that end, attach at least one -uniquely identifiable device to a USB port and run this script. The device needs -to be visible in the output of \"lsusb -t\" (debug devices are often *not*!). - -After determining compatibility of the USB controllers the script will print the -devices attached to the debug port as shown by lsusb. If nothing shows up simply -switch ports and repeat the process. - -Note: usually only one port is supported for debugging.\n" - exit 0 -fi -uid=`id -u` -if [ "$uid" -ne 0 ]; then - echo "Must be run as root. Exiting." - exit 1 -fi -dmesgfile=$1 - -find_devs_in_tree () { - bus=$1 - port=$2 - busstr=`printf "Bus %02d" "$bus"` - portstr="Port $port" - - found= - # Iterate over the output of lsusb -t because it contains the physical port names - while IFS='' read -r line; do - # We need to keep track of the current bus "branch" - # Look out for lines starting with /: (that indicate a bus) - if [ "${line#*/:}" != "$line" ]; then - if [ "${line#*$busstr}" != "$line" ]; then - cur_bus=$busstr - else - cur_bus= - fi - continue - fi - - # Skip all lines not belonging to the wanted bus number - if [ "$cur_bus" != "$busstr" ]; then - continue - fi - - # check for matching physical USB port, and take only IF 0 into account - if [ "${line#*$portstr}" != "$line" -a "${line#*If 0}" != "$line" ]; then - dev=`echo ${line#*Dev } | cut -d ',' -f 1` - lsusb -s "$bus":"$dev" - found="yes" - fi - done<< EOF -$(lsusb -t) -EOF - if [ -z "$found" ]; then - echo "none" - fi -} - -debug_lspci_devs=`lspci -nvvD | - grep -i "^[0-9a-f]\|debug port" | - grep -iB1 --no-group-separator "debug port" | - grep -vi "debug port" | - cut -f 1 -d" " | - sort | - xargs echo` - -if [ -z "$debug_lspci_devs" ]; then - printf "No USB controller with debug capability found by lspci.\n -Possible reasons: lspci too old, USB controller does not support a debug device, ... Exiting.\n" - exit 1 -fi -printf "The following PCI devices support a USB debug port (says lspci): $debug_lspci_devs\n" - -debug_dmesg_devs_with_port=`( test -z "$dmesgfile" && - dmesg || - cat "$dmesgfile") | - grep -i "ehci.*debug port" | - sed "s/.* $[0-9a-f]*:*[0-9a-f]\{2\}:[0-9a-f]\{2\}\.[0-9a-f]$.*ebug port /\1 /" | - sort` - -debug_dmesg_devs=`echo "$debug_dmesg_devs_with_port" | - cut -f 1 -d" " | - xargs echo` - -if [ -z "$debug_dmesg_devs" ]; then - printf "dmesg does not show any supported ports.\n -Possible reasons: dmesg scrolled off, kernel too old, USB controller does not support a debug device, ... Exiting.\n -Note: You can specify a file containing kernel messages as an argument to this program (e.g. /var/log/dmesg)." - exit 1 -fi - -if [ "$debug_lspci_devs" != "$debug_dmesg_devs" ]; then - echo "lspci and the kernel do not agree on USB debug device support. Exiting." - exit 1 -fi - -printf "and the kernel agrees, good.\n\n" - -while true; do - for dev in $debug_dmesg_devs; do - bus=`lsusb -v | - grep "^Bus\|iSerial.*" | - grep -B1 --no-group-separator "iSerial.*$dev" | - grep "^Bus" | - sed "s/Bus *0*$[0-9a-f]*$.*/\1/"` - port=`echo "$debug_dmesg_devs_with_port" | - grep "^$dev" | - cut -f 2 -d" "` - - echo "Device(s) currently connected to the debug-capable port $port on PCI device $dev, USB bus $bus:" - - find_devs_in_tree $bus $port - echo - done - - echo "Enter 'q' to abort or anything else to repeat" - read r - if [ $? -ne 0 -o "$r" = "q" ]; then - break; - fi -done - -return 0 diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh deleted file mode 100755 index 55a3b85..0000000 --- a/util/genbuild_h/genbuild_h.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh - -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -DATE="" -GITREV="" -TIMESOURCE="" -if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then - GITREV=$(LANG= git log remotes/origin/master -1 --format=format:%h) - TIMESOURCE=git - DATE=$(git log --pretty=format:%ct -1) -else - GITREV=Unknown - TIMESOURCE="LANG= TZ=UTC date" - DATE=$(date +%s) -fi - -our_date() { -case $(uname) in -NetBSD|OpenBSD|DragonFly|FreeBSD) - TZ=UTC date -r $1 $2 - ;; -*) - TZ=UTC date -d @$1 $2 -esac -} - -#Print out the information that goes into build.h -printf "/* build system definitions (autogenerated) */\n" -printf "#ifndef __BUILD_H\n" -printf "#define __BUILD_H\n\n" -printf "#define COREBOOT_VERSION %s\n" "\"$KERNELVERSION\"" - -#See if the build is running in a git repo and the git command is available -printf "/* timesource: $TIMESOURCE */\n" -printf "#define COREBOOT_VERSION_TIMESTAMP $DATE\n" -printf "#define COREBOOT_ORIGIN_GIT_REVISION \"$GITREV\"\n" - -printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION" -printf "#define COREBOOT_BUILD \"$(LANG= our_date "$DATE")\"\n" -printf "#define COREBOOT_BUILD_YEAR_BCD 0x$(our_date "$DATE" +%y)\n" -printf "#define COREBOOT_BUILD_MONTH_BCD 0x$(our_date "$DATE" +%m)\n" -printf "#define COREBOOT_BUILD_DAY_BCD 0x$(our_date "$DATE" +%d)\n" -printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x$(our_date "$DATE" +%w)\n" -printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%m/%d/%Y)\"\n" -printf "\n" -printf "#define COREBOOT_COMPILE_TIME \"$(our_date "$DATE" +%T)\"\n" -printf "#endif\n" diff --git a/util/ipqheader/ipqheader.py b/util/ipqheader/ipqheader.py deleted file mode 100755 index eb1a316..0000000 --- a/util/ipqheader/ipqheader.py +++ /dev/null @@ -1,130 +0,0 @@ -#!/usr/bin/python -# -# Copyright (c) 2013 The Linux Foundation. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from this -# software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -import os -import struct -import sys - -PROG_NAME = os.path.basename(sys.argv[0]) - -def create_header(base, size): - """Returns a packed MBN header image with the specified base and size. - - @arg base: integer, specifies the image load address in RAM - @arg size: integer, specifies the size of the image - @returns: string, the MBN header - """ - - # SBLs require size to be 4 bytes aligned. - size = (size + 3) & 0xfffffffc - - # We currently do not support appending certificates. Signing GPL - # code might violate the GPL. So U-Boot will never be signed. So - # this is not required for U-Boot. - - header = [ - 0x5, # Type: APPSBL - 0x3, # Version: 3 - 0x0, # Image source pointer - base, # Image destination pointer - size, # Code Size + Cert Size + Signature Size - size, # Code Size - base + size, # Destination + Code Size - 0x0, # Signature Size - base + size, # Destination + Code Size + Signature Size - 0x0, # Cert Size - ] - - header_packed = struct.pack('<10I', *header) - return header_packed - -def mkheader(base_addr, infname, outfname): - """Prepends the image with the MBN header. - - @arg base_addr: integer, specifies the image load address in RAM - @arg infname: string, image filename - @arg outfname: string, output image with header prepended - @raises IOError: if reading/writing input/output file fails - """ - with open(infname, "rb") as infp: - image = infp.read() - insize = len(image) - - if base_addr > 0xFFFFFFFF: - raise ValueError("invalid base address") - - if base_addr + insize > 0xFFFFFFFF: - raise ValueError("invalid destination range") - - header = create_header(base_addr, insize) - with open(outfname, "wb") as outfp: - outfp.write(header) - outfp.write(image) - -def usage(msg=None): - """Print command usage. - - @arg msg: string, error message if any (default: None) - """ - if msg != None: - sys.stderr.write("%s: %s\n" % (PROG_NAME, msg)) - - print "Usage: %s <base-addr> <input-file> <output-file>" % PROG_NAME - - if msg != None: - exit(1) - -def main(): - """Main entry function""" - - if len(sys.argv) != 4: - usage("incorrect number of arguments") - - try: - base_addr = int(sys.argv[1], 0) - infname = sys.argv[2] - outfname = sys.argv[3] - except ValueError as e: - sys.stderr.write("mkheader: invalid base address '%s'\n" % sys.argv[1]) - exit(1) - - try: - mkheader(base_addr, infname, outfname) - except IOError as e: - sys.stderr.write("%s: %s\n" % (PROG_NAME, e)) - exit(1) - except ValueError as e: - sys.stderr.write("%s: %s\n" % (PROG_NAME, e)) - exit(1) - -if __name__ == "__main__": - main() - diff --git a/util/rockchip/LICENSE b/util/rockchip/LICENSE deleted file mode 100644 index cb4d35b..0000000 --- a/util/rockchip/LICENSE +++ /dev/null @@ -1,25 +0,0 @@ -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// -// * Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above -// copyright notice, this list of conditions and the following disclaimer -// in the documentation and/or other materials provided with the -// distribution. -// * Neither the name of Google Inc. nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py deleted file mode 100755 index e95f5c2..0000000 --- a/util/rockchip/make_idb.py +++ /dev/null @@ -1,124 +0,0 @@ -#!/usr/bin/env python -# Copyright (c) 2014 Google Inc. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -import struct -import sys -from io import SEEK_SET, SEEK_END - -class IDBTool: - def __init__(self): - print "Initialize IDBTool" - - def p_rc4(self, buf, length): - key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) - K = key * 16 - S = [i for i in range(256)] - - j = 0 - for i in range(256): - j = (j + S[i] + K[i]) % 256 - temp = S[i]; S[i] = S[j]; S[j] = temp; - - i = j = k = 0 - for x in range(length): - i = (i+1) % 256 - j = (j + S[i]) % 256 - temp = S[i]; S[i] = S[j]; S[j] = temp - k = (S[i] + S[j]) % 256 - buf[x] = struct.pack('B', ord(buf[x]) ^ S[k]) - - def makeIDB(self, from_file, to_file, rc4_flag = False, align_flag = False): - try: - fin = open(from_file, 'rb') - except: - sys.exit("Failed to open file : " + from_file) - - try: - fin.seek(0, SEEK_END) - if (fin.tell() > 4 * 1024 * 1024): - sys.exit("Input file is more than 4MB") - fin.seek(0) - data = fin.read() - finally: - fin.close() - - data_len = len(data) - SECTOR_SIZE = 512 - PAGE_ALIGN = 4 - sectors = (data_len + 4 - 1) / SECTOR_SIZE + 1 - pages = (sectors - 1) / PAGE_ALIGN + 1 - sectors = pages * PAGE_ALIGN; - - buf = [B'\0'] * sectors * SECTOR_SIZE - buf[:4] = "RK32" - buf[4 : 4+data_len] = data - - idblock = [B'\0'] * 4 * SECTOR_SIZE - blank = [B'\0'] * 4 * SECTOR_SIZE - idblock[:4] = ['\x55', '\xAA', '\xF0', '\x0F'] - - if (not rc4_flag): - idblock[8:12] = struct.pack("<I", 1) - else: - for i in range(sectors): - list_tmp = buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] - self.p_rc4(list_tmp, SECTOR_SIZE) - buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] = list_tmp - - idblock[12:16] = struct.pack("<HH", 4, 4); - idblock[506:510] = struct.pack("<HH", sectors, sectors); - self.p_rc4(idblock, SECTOR_SIZE) - - try: - fout = open(to_file, "wb+") - except: - sys.exit("Failed to open output file : " + to_file) - - try: - if (align_flag): - fout.write(''.join(idblock)) - fout.write(''.join(blank)) - - for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): - fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) - fout.write(''.join(blank)) - else: - fout.write(''.join(idblock)) - fout.write(''.join(buf)) - fout.flush() - except: - sys.exit("Failed to write data to : " + to_file) - finally: - fout.close() - print "DONE" - -def usage(): - print "Usage: make_idb.py [--enable-rc4] [--enable-align] [--to=out] --from=in" - -if __name__ == '__main__': - rc4_flag = align_flag = False - to_file = "IDBlock.bin" - - for para in sys.argv[1:]: - if (para == "--enable-rc4"): - rc4_flag = True - elif (para == "--enable-align"): - align_flag = True - elif (para.startswith("--to=")): - to_file = para.split('=')[1] - elif (para.startswith("--from=")): - from_file = para.split('=')[1] - elif (para == "--help" or para == "-h"): - usage() - sys.exit() - else: - usage() - sys.exit() - if ('from_file' not in vars() or to_file == ''): - usage() - sys.exit() - - idbtool = IDBTool() - idbtool.makeIDB(from_file, to_file, rc4_flag, align_flag) diff --git a/util/scripts/acpidump-all b/util/scripts/acpidump-all new file mode 100755 index 0000000..aa73a15 --- /dev/null +++ b/util/scripts/acpidump-all @@ -0,0 +1,50 @@ +#!/bin/bash +# +# Copyright (C) 2007-2010 by coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# + +rm -rf out +mkdir out + +# walk through all ACPI tables with their addresses +# example: +# RSDT @ 0xcf6794ba +# we can not just dump the tables by their names because some +# machines have double ACPI tables + +acpidump | grep "@ 0x" | while read line +do + NAME=$( echo `echo $line|cut -f1 -d@` ) + FNAME=$( echo $NAME | sed s/\ /_/g |sed s/\!/b/g ) + ADDR=$( echo `echo $line|cut -f2 -d@` ) + if [ "${!FNAME}" == "" ]; then + eval $FNAME=0 + else + eval $FNAME=$(( ${!FNAME} + 1 )) + fi + printf "Processing table \"$NAME\" at $ADDR ... " + printf "${!FNAME} tables of that kind found before.\n" + + # acpidump -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.txt + acpidump -b -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.bin + if [ "`file -b out/$FNAME-$ADDR-${!FNAME}.bin`" != "ASCII text" ]; then + iasl -d out/$FNAME-$ADDR-${!FNAME}.bin &>/dev/null + else + printf "Skipping $NAME because it was not dumped correctly.\n\n" + fi + +done + diff --git a/util/scripts/dtd_parser.py b/util/scripts/dtd_parser.py new file mode 100755 index 0000000..23cc7e7 --- /dev/null +++ b/util/scripts/dtd_parser.py @@ -0,0 +1,213 @@ +#!/usr/bin/python +# dtd_parser.py - DTD structure parser +# +# Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +''' +DTD string parser/generator. + +Detailed timing descriptor (DTD) is an 18 byte array describing video mode +(screen resolution, display properties, etc.) in EDID and used by Intel Option +ROM. Option ROM can support multiple video modes, specific mode is picked by +the BIOS through the appropriate Option ROM callback function. + +This program allows to interpret the 18 byte hex DTD dump, and/or modify +certain values and generate a new DTD. +''' + +import sys + +# +# The DTD array format description can be found in +# http://en.wikipedia.org/wiki/Extended_display_identification_data, (see the +# EDID Detailed Timing Descriptor section). +# +# The below dictionary describes how different DTD parameters are laid out in +# the array. Note that many parameters span multiple bit fields in the DTD. +# +# The keys in the dictionary are stings (field names), the values are tuples +# of either numbers or tri-tuples. If the element of the tuple is a number, it +# is the offset in DTD, and the entire byte is used in this field. If the +# element is a tri-tuple, its components are (DTD offset, bit shift, field +# width). +# +# The partial values are extracted from the DTD fields and concatenated +# together to form actual parameter value. +# + +dtd_descriptor = { + 'dclck' : (1, 0), + 'hor_active' : ((4, 4, 4), 2), + 'hor_blank' : ((4, 0, 4), 3), + 'vert_act' : ((7, 4, 4), 5), + 'vert_blank' : ((7, 0, 4), 6), + 'hsync_offset' : ((11, 6, 2), 8), + 'hsync_pulse_width' : ((11, 4, 2), 9), + 'vsync_offset' : ((11, 2, 2), (10, 4, 4)), + 'vsync_pulse_width' : ((11, 0, 2), (10, 0, 4)), + 'hor_image_size' : ((14, 4, 4), 12), + 'vert_image_size' : ((14, 0, 4), 13), + 'hor_border' : (15,), + 'vert_border' : (16,), + 'interlaced' : ((17, 7, 1),), + 'reserved' : ((17, 5, 2), (17, 0, 1)), + 'digital_separate' : ((17, 3, 2),), + 'vert_polarity' : ((17, 2, 1),), + 'hor_polarity' : ((17, 1, 1),), + } + +PREFIX = 'attr_' + +class DTD(object): + '''An object containing all DTD information. + + The attributes are created dynamically when the input DTD string is + parsed. For each element of the above dictionary two attributes are added: + + 'attr_<param>' to hold the actual parameter value + 'max_attr_<param>' to hold the maximum allowed value for this parameter. + ''' + + def __init__(self): + for name in dtd_descriptor: + setattr(self, PREFIX + name, 0) + + def init(self, sarray): + '''Initialize the object with values from a DTD array. + + Inputs: + + sarray: a string, an array of ASCII hex representations of the 18 DTD + bytes. + + Raises: implicitly raises ValueError or IndexError exceptions in case + the input string has less than 18 elements, or some of the + elements can not be converted to integer. + ''' + + harray = [int(x, 16) for x in sarray] + for name, desc in dtd_descriptor.iteritems(): + attr_value = 0 + total_width = 0 + for tup in desc: + if isinstance(tup, tuple): + offset, shift, width = tup + else: + offset, shift, width = tup, 0, 8 + + mask = (1 << width) - 1 + attr_value = (attr_value << width) + ( + (harray[offset] >> shift) & mask) + total_width += width + setattr(self, PREFIX + name, attr_value) + setattr(self, 'max_' + PREFIX + name, (1 << total_width) - 1) + + def __str__(self): + text = [] + for name in sorted(dtd_descriptor.keys()): + text.append('%20s: %d' % (name, getattr(self, PREFIX + name))) + return '\n'.join(text) + + def inhex(self): + '''Generate contents of the DTD as a 18 byte ASCII hex array.''' + + result = [0] * 18 + for name, desc in dtd_descriptor.iteritems(): + attr_value = getattr(self, PREFIX + name) + rdesc = list(desc) + rdesc.reverse() + for tup in rdesc: + if isinstance(tup, tuple): + offset, shift, width = tup + else: + offset, shift, width = tup, 0, 8 + + mask = (1 << width) - 1 + value = attr_value & mask + attr_value = attr_value >> width + result[offset] = (result[offset] & ~( + mask << shift)) | (value << shift) + + return ' '.join('%2.2x' % x for x in result) + + def handle_input(self, name): + '''Get user input and set a new parameter value if required. + + Display the parameter name, its current value, and prompt user for a + new value. + + If the user enters a dot, stop processing (return True). + + Empty user input means that this parameter does not have to change, + but the next parameter should be prompted. + + If input is non-empty, it is interpreted as a hex number, checked if + it fits the parameter and the new parameter value is set if checks + pass. + + Inputs: + + name - a string, parameter name, a key in dtd_descriptor + + Returns: + + Boolean, True meaning no more field are required to be modified, False + meaning that more field mods need to be prompted.. + ''' + + param = PREFIX + name + vmax = getattr(self, 'max_' + param) + new_value = raw_input('%s : %d ' % (name, getattr(self, param))) + if new_value == '': + return False + if new_value == '.': + return True + new_int = int(new_value) + if new_int > vmax: + print '%s exceeds maximum for %s (%d)' % (new_value, name, vmax) + else: + setattr(self, param, new_int) + return False + +def main(args): + if args[0] == '-m': + modify = True + base = 1 + else: + modify = False + base = 0 + + d = DTD() + d.init(args[base:]) + if modify: + for line in str(d).splitlines(): + if d.handle_input(line.split(':')[0].strip()): + break + print d + if modify: + print d.inhex() + + +if __name__ == '__main__': + try: + main(sys.argv[1:]) + except (ValueError, IndexError): + print """ +A string of 18 byte values in hex is required. +'-m' preceding the string will allow setting new parameter values. +""" + sys.exit(1) diff --git a/util/scripts/exynos_fixed_cksum.py b/util/scripts/exynos_fixed_cksum.py new file mode 100755 index 0000000..66da060 --- /dev/null +++ b/util/scripts/exynos_fixed_cksum.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python +# +# Copyright (C) 2013 Google Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. + +""" +This utility computes and fills Exynos ROM checksum (for BL1 or BL2). +(Algorithm from U-Boot: tools/mkexynosspl.c) + +Input: IN OUT DATA_SIZE + +Output: + + IN padded out to DATA_SIZE, checksum at the end, written to OUT. +""" + +import struct +import sys + +def main(argv): + if len(argv) != 4: + exit('usage: %s IN OUT DATA_SIZE' % argv[0]) + + in_name, out_name = argv[1:3] + size = int(argv[3], 0) + checksum_format = "<I" + with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file: + data = in_file.read() + checksum_size = struct.calcsize(checksum_format) + data_size = size - checksum_size + assert len(data) <= data_size + checksum = struct.pack(checksum_format, sum(map(ord, data))) + out_file.write(data + bytearray(data_size - len(data)) + checksum) + + +if __name__ == '__main__': + main(sys.argv) diff --git a/util/scripts/exynos_variable_cksum.py b/util/scripts/exynos_variable_cksum.py new file mode 100755 index 0000000..75cdc74 --- /dev/null +++ b/util/scripts/exynos_variable_cksum.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python +# +# Copyright (C) 2013 Google Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. + +""" +This utility computes and fills Exynos ROM checksum (for BL1 or BL2). +(Algorithm from U-Boot: tools/mkexynosspl.c) + +Input: IN OUT + +Output: + + Checksum header added to IN and written to OUT. + Header: uint32_t size, checksum, reserved[2]. +""" + +import struct +import sys + +def main(argv): + if len(argv) != 3: + exit('usage: %s IN OUT' % argv[0]) + + in_name, out_name = argv[1:3] + header_format = "<IIII" + with open(in_name, "rb") as in_file, open(out_name, "wb") as out_file: + data = in_file.read() + header = struct.pack(header_format, + struct.calcsize(header_format) + len(data), + sum(map(ord, data)), + 0, 0) + out_file.write(header + data) + + +if __name__ == '__main__': + main(sys.argv) diff --git a/util/scripts/find_usbdebug.sh b/util/scripts/find_usbdebug.sh new file mode 100755 index 0000000..2f82219 --- /dev/null +++ b/util/scripts/find_usbdebug.sh @@ -0,0 +1,149 @@ +#!/bin/sh + +# Copyright 2008 Carl-Daniel Hailfinger +# Copyright 2015 Stefan Tauner +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. + +LANG=C +# Some tools emmit errors that don't matter (bugs in lspci/PCI firmware and lsusb). +# To shown them anyway (e.g. for debugging) comment next line. +exec 2>/dev/null + +if [ "$1" = "-h" ]; then + printf "Usage: $0 [-h | path to dmesg log] + +This script tries to find USB ports compatible with USB2/EHCI debug devices and +helps you to find their physical locations. To that end, attach at least one +uniquely identifiable device to a USB port and run this script. The device needs +to be visible in the output of \"lsusb -t\" (debug devices are often *not*!). + +After determining compatibility of the USB controllers the script will print the +devices attached to the debug port as shown by lsusb. If nothing shows up simply +switch ports and repeat the process. + +Note: usually only one port is supported for debugging.\n" + exit 0 +fi +uid=`id -u` +if [ "$uid" -ne 0 ]; then + echo "Must be run as root. Exiting." + exit 1 +fi +dmesgfile=$1 + +find_devs_in_tree () { + bus=$1 + port=$2 + busstr=`printf "Bus %02d" "$bus"` + portstr="Port $port" + + found= + # Iterate over the output of lsusb -t because it contains the physical port names + while IFS='' read -r line; do + # We need to keep track of the current bus "branch" + # Look out for lines starting with /: (that indicate a bus) + if [ "${line#*/:}" != "$line" ]; then + if [ "${line#*$busstr}" != "$line" ]; then + cur_bus=$busstr + else + cur_bus= + fi + continue + fi + + # Skip all lines not belonging to the wanted bus number + if [ "$cur_bus" != "$busstr" ]; then + continue + fi + + # check for matching physical USB port, and take only IF 0 into account + if [ "${line#*$portstr}" != "$line" -a "${line#*If 0}" != "$line" ]; then + dev=`echo ${line#*Dev } | cut -d ',' -f 1` + lsusb -s "$bus":"$dev" + found="yes" + fi + done<< EOF +$(lsusb -t) +EOF + if [ -z "$found" ]; then + echo "none" + fi +} + +debug_lspci_devs=`lspci -nvvD | + grep -i "^[0-9a-f]\|debug port" | + grep -iB1 --no-group-separator "debug port" | + grep -vi "debug port" | + cut -f 1 -d" " | + sort | + xargs echo` + +if [ -z "$debug_lspci_devs" ]; then + printf "No USB controller with debug capability found by lspci.\n +Possible reasons: lspci too old, USB controller does not support a debug device, ... Exiting.\n" + exit 1 +fi +printf "The following PCI devices support a USB debug port (says lspci): $debug_lspci_devs\n" + +debug_dmesg_devs_with_port=`( test -z "$dmesgfile" && + dmesg || + cat "$dmesgfile") | + grep -i "ehci.*debug port" | + sed "s/.* $[0-9a-f]*:*[0-9a-f]\{2\}:[0-9a-f]\{2\}\.[0-9a-f]$.*ebug port /\1 /" | + sort` + +debug_dmesg_devs=`echo "$debug_dmesg_devs_with_port" | + cut -f 1 -d" " | + xargs echo` + +if [ -z "$debug_dmesg_devs" ]; then + printf "dmesg does not show any supported ports.\n +Possible reasons: dmesg scrolled off, kernel too old, USB controller does not support a debug device, ... Exiting.\n +Note: You can specify a file containing kernel messages as an argument to this program (e.g. /var/log/dmesg)." + exit 1 +fi + +if [ "$debug_lspci_devs" != "$debug_dmesg_devs" ]; then + echo "lspci and the kernel do not agree on USB debug device support. Exiting." + exit 1 +fi + +printf "and the kernel agrees, good.\n\n" + +while true; do + for dev in $debug_dmesg_devs; do + bus=`lsusb -v | + grep "^Bus\|iSerial.*" | + grep -B1 --no-group-separator "iSerial.*$dev" | + grep "^Bus" | + sed "s/Bus *0*$[0-9a-f]*$.*/\1/"` + port=`echo "$debug_dmesg_devs_with_port" | + grep "^$dev" | + cut -f 2 -d" "` + + echo "Device(s) currently connected to the debug-capable port $port on PCI device $dev, USB bus $bus:" + + find_devs_in_tree $bus $port + echo + done + + echo "Enter 'q' to abort or anything else to repeat" + read r + if [ $? -ne 0 -o "$r" = "q" ]; then + break; + fi +done + +return 0 diff --git a/util/scripts/genbuild_h.sh b/util/scripts/genbuild_h.sh new file mode 100755 index 0000000..55a3b85 --- /dev/null +++ b/util/scripts/genbuild_h.sh @@ -0,0 +1,64 @@ +#!/bin/sh + +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +DATE="" +GITREV="" +TIMESOURCE="" +if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then + GITREV=$(LANG= git log remotes/origin/master -1 --format=format:%h) + TIMESOURCE=git + DATE=$(git log --pretty=format:%ct -1) +else + GITREV=Unknown + TIMESOURCE="LANG= TZ=UTC date" + DATE=$(date +%s) +fi + +our_date() { +case $(uname) in +NetBSD|OpenBSD|DragonFly|FreeBSD) + TZ=UTC date -r $1 $2 + ;; +*) + TZ=UTC date -d @$1 $2 +esac +} + +#Print out the information that goes into build.h +printf "/* build system definitions (autogenerated) */\n" +printf "#ifndef __BUILD_H\n" +printf "#define __BUILD_H\n\n" +printf "#define COREBOOT_VERSION %s\n" "\"$KERNELVERSION\"" + +#See if the build is running in a git repo and the git command is available +printf "/* timesource: $TIMESOURCE */\n" +printf "#define COREBOOT_VERSION_TIMESTAMP $DATE\n" +printf "#define COREBOOT_ORIGIN_GIT_REVISION \"$GITREV\"\n" + +printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION" +printf "#define COREBOOT_BUILD \"$(LANG= our_date "$DATE")\"\n" +printf "#define COREBOOT_BUILD_YEAR_BCD 0x$(our_date "$DATE" +%y)\n" +printf "#define COREBOOT_BUILD_MONTH_BCD 0x$(our_date "$DATE" +%m)\n" +printf "#define COREBOOT_BUILD_DAY_BCD 0x$(our_date "$DATE" +%d)\n" +printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x$(our_date "$DATE" +%w)\n" +printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%m/%d/%Y)\"\n" +printf "\n" +printf "#define COREBOOT_COMPILE_TIME \"$(our_date "$DATE" +%T)\"\n" +printf "#endif\n" diff --git a/util/scripts/ipqheader.py b/util/scripts/ipqheader.py new file mode 100755 index 0000000..eb1a316 --- /dev/null +++ b/util/scripts/ipqheader.py @@ -0,0 +1,130 @@ +#!/usr/bin/python +# +# Copyright (c) 2013 The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +import os +import struct +import sys + +PROG_NAME = os.path.basename(sys.argv[0]) + +def create_header(base, size): + """Returns a packed MBN header image with the specified base and size. + + @arg base: integer, specifies the image load address in RAM + @arg size: integer, specifies the size of the image + @returns: string, the MBN header + """ + + # SBLs require size to be 4 bytes aligned. + size = (size + 3) & 0xfffffffc + + # We currently do not support appending certificates. Signing GPL + # code might violate the GPL. So U-Boot will never be signed. So + # this is not required for U-Boot. + + header = [ + 0x5, # Type: APPSBL + 0x3, # Version: 3 + 0x0, # Image source pointer + base, # Image destination pointer + size, # Code Size + Cert Size + Signature Size + size, # Code Size + base + size, # Destination + Code Size + 0x0, # Signature Size + base + size, # Destination + Code Size + Signature Size + 0x0, # Cert Size + ] + + header_packed = struct.pack('<10I', *header) + return header_packed + +def mkheader(base_addr, infname, outfname): + """Prepends the image with the MBN header. + + @arg base_addr: integer, specifies the image load address in RAM + @arg infname: string, image filename + @arg outfname: string, output image with header prepended + @raises IOError: if reading/writing input/output file fails + """ + with open(infname, "rb") as infp: + image = infp.read() + insize = len(image) + + if base_addr > 0xFFFFFFFF: + raise ValueError("invalid base address") + + if base_addr + insize > 0xFFFFFFFF: + raise ValueError("invalid destination range") + + header = create_header(base_addr, insize) + with open(outfname, "wb") as outfp: + outfp.write(header) + outfp.write(image) + +def usage(msg=None): + """Print command usage. + + @arg msg: string, error message if any (default: None) + """ + if msg != None: + sys.stderr.write("%s: %s\n" % (PROG_NAME, msg)) + + print "Usage: %s <base-addr> <input-file> <output-file>" % PROG_NAME + + if msg != None: + exit(1) + +def main(): + """Main entry function""" + + if len(sys.argv) != 4: + usage("incorrect number of arguments") + + try: + base_addr = int(sys.argv[1], 0) + infname = sys.argv[2] + outfname = sys.argv[3] + except ValueError as e: + sys.stderr.write("mkheader: invalid base address '%s'\n" % sys.argv[1]) + exit(1) + + try: + mkheader(base_addr, infname, outfname) + except IOError as e: + sys.stderr.write("%s: %s\n" % (PROG_NAME, e)) + exit(1) + except ValueError as e: + sys.stderr.write("%s: %s\n" % (PROG_NAME, e)) + exit(1) + +if __name__ == "__main__": + main() + diff --git a/util/scripts/rk_make_idb.py b/util/scripts/rk_make_idb.py new file mode 100755 index 0000000..26e26b8 --- /dev/null +++ b/util/scripts/rk_make_idb.py @@ -0,0 +1,150 @@ +#!/usr/bin/env python +# +# Copyright (c) 2014 Google Inc. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. + +""" +Creates a Rockchip ID Block (IDB), optionally RC4 encrypted and aligned +""" + +import struct +import sys +from io import SEEK_SET, SEEK_END + +class IDBTool: + def __init__(self): + print "Initialize IDBTool" + + def p_rc4(self, buf, length): + key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) + K = key * 16 + S = [i for i in range(256)] + + j = 0 + for i in range(256): + j = (j + S[i] + K[i]) % 256 + temp = S[i]; S[i] = S[j]; S[j] = temp; + + i = j = k = 0 + for x in range(length): + i = (i+1) % 256 + j = (j + S[i]) % 256 + temp = S[i]; S[i] = S[j]; S[j] = temp + k = (S[i] + S[j]) % 256 + buf[x] = struct.pack('B', ord(buf[x]) ^ S[k]) + + def makeIDB(self, from_file, to_file, rc4_flag = False, align_flag = False): + try: + fin = open(from_file, 'rb') + except: + sys.exit("Failed to open file : " + from_file) + + try: + fin.seek(0, SEEK_END) + if (fin.tell() > 4 * 1024 * 1024): + sys.exit("Input file is more than 4MB") + fin.seek(0) + data = fin.read() + finally: + fin.close() + + data_len = len(data) + SECTOR_SIZE = 512 + PAGE_ALIGN = 4 + sectors = (data_len + 4 - 1) / SECTOR_SIZE + 1 + pages = (sectors - 1) / PAGE_ALIGN + 1 + sectors = pages * PAGE_ALIGN; + + buf = [B'\0'] * sectors * SECTOR_SIZE + buf[:4] = "RK32" + buf[4 : 4+data_len] = data + + idblock = [B'\0'] * 4 * SECTOR_SIZE + blank = [B'\0'] * 4 * SECTOR_SIZE + idblock[:4] = ['\x55', '\xAA', '\xF0', '\x0F'] + + if (not rc4_flag): + idblock[8:12] = struct.pack("<I", 1) + else: + for i in range(sectors): + list_tmp = buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] + self.p_rc4(list_tmp, SECTOR_SIZE) + buf[SECTOR_SIZE*i : SECTOR_SIZE*(i+1)] = list_tmp + + idblock[12:16] = struct.pack("<HH", 4, 4); + idblock[506:510] = struct.pack("<HH", sectors, sectors); + self.p_rc4(idblock, SECTOR_SIZE) + + try: + fout = open(to_file, "wb+") + except: + sys.exit("Failed to open output file : " + to_file) + + try: + if (align_flag): + fout.write(''.join(idblock)) + fout.write(''.join(blank)) + + for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): + fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) + fout.write(''.join(blank)) + else: + fout.write(''.join(idblock)) + fout.write(''.join(buf)) + fout.flush() + except: + sys.exit("Failed to write data to : " + to_file) + finally: + fout.close() + print "DONE" + +def usage(): + print "Usage: make_idb.py [--enable-rc4] [--enable-align] [--to=out] --from=in" + +if __name__ == '__main__': + rc4_flag = align_flag = False + to_file = "IDBlock.bin" + + for para in sys.argv[1:]: + if (para == "--enable-rc4"): + rc4_flag = True + elif (para == "--enable-align"): + align_flag = True + elif (para.startswith("--to=")): + to_file = para.split('=')[1] + elif (para.startswith("--from=")): + from_file = para.split('=')[1] + elif (para == "--help" or para == "-h"): + usage() + sys.exit() + else: + usage() + sys.exit() + if ('from_file' not in vars() or to_file == ''): + usage() + sys.exit() + + idbtool = IDBTool() + idbtool.makeIDB(from_file, to_file, rc4_flag, align_flag) diff --git a/util/scripts/xcompile b/util/scripts/xcompile new file mode 100755 index 0000000..5809ec0 --- /dev/null +++ b/util/scripts/xcompile @@ -0,0 +1,269 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2010 coresystems GmbH +# Copyright (C) 2012 Google Inc +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +TMPFILE="" +XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} + +die() { + echo "ERROR: $*" >&2 + exit 1 +} + +clean_up() { + if [ -n "$TMPFILE" ]; then + rm -f "$TMPFILE" "$TMPFILE.c" "$TMPFILE.o" + fi +} + +# Create temporary file(s). +TMPFILE="$(mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz)" +touch "$TMPFILE" +trap clean_up EXIT + + +program_exists() { + type "$1" >/dev/null 2>&1 +} + + +if [ "$(${XGCCPATH}/iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then + IASL=${XGCCPATH}iasl +elif [ "$(iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then + IASL=iasl +else + die "no iasl found" +fi + +if program_exists gcc; then + HOSTCC=gcc +elif program_exists cc; then + HOSTCC=cc +else + die "no host compiler found" +fi + +cat <<EOF +# platform agnostic and host tools +IASL:=${IASL} +HOSTCC:=${HOSTCC} + +EOF + +testcc() { + local tmp_c="$TMPFILE.c" + local tmp_o="$TMPFILE.o" + rm -f "$tmp_c" "$tmp_o" + echo "void _start(void) {}" >"$tmp_c" + "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 +} + +testas() { + local gccprefixes="$1" + local twidth="$2" + local arch="$3" + local use_dash_twidth="$4" + local obj_file="$TMPFILE.o" + local full_arch="elf$twidth-$arch" + + rm -f "$obj_file" + [ -n "$use_dash_twidth" ] && use_dash_twidth="--$twidth" + ${gccprefixes}as $use_dash_twidth -o "$obj_file" $TMPFILE 2>/dev/null || + return 1 + + # Check output content type. + local obj_type="$(${gccprefixes}objdump -p $obj_file)" + local obj_arch="$(expr "$obj_type" : '.*format $.[a-z0-9-]*$')" + [ "$obj_arch" = "$full_arch" ] || return 1 + + # Architecture matched. + GCCPREFIX="$gccprefixes" + + if [ -z "$use_dash_twidth" ]; then + ASFLAGS="" + CFLAGS="" + LDFLAGS="" + else + ASFLAGS="--$twidth" + CFLAGS="-m$twidth" + LDFLAGS="-b $full_arch" + + fi + + # Special parameters only available in dash_twidth mode. + [ -n "$use_dash_twidth" ] && case "$full_arch" in + "elf32-i386" ) + LDFLAGS="$LDFLAGS -melf_i386" + CFLAGS="$CFLAGS -Wl,-b,elf32-i386 -Wl,-melf_i386" + ;; + esac + + return 0 +} + +detect_special_flags() { + local architecture="$1" + # GCC 4.6 is much more picky about unused variables. + # Turn off it's warnings for now: + testcc "$CC" "$CFLAGS -Wno-unused-but-set-variable " && + CFLAGS="$CFLAGS -Wno-unused-but-set-variable " + + # Use bfd linker instead of gold if available: + testcc "$CC" "$CFLAGS -fuse-ld=bfd" && + CFLAGS="$CFLAGS -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' + + testcc "$CC" "$CFLAGS -fno-stack-protector"&& + CFLAGS="$CFLAGS -fno-stack-protector" + testcc "$CC" "$CFLAGS -Wl,--build-id=none" && + CFLAGS="$CFLAGS -Wl,--build-id=none" + + case "$architecture" in + x86) + testcc "$CC" "$CFLAGS -Wa,--divide" && + CFLAGS="$CFLAGS -Wa,--divide" + # Always build for i686 -- no sse/mmx instructions since SMM + # modules are compiled using these flags. Note that this + # doesn't prevent a project using xcompile to explicitly + # specify -mmsse, etc flags. + CFLAGS="$CFLAGS -march=i686" + ;; + mipsel) + testcc "$CC" "$CFLAGS -mno-abicalls -fno-pic" && \ + CFLAGS+=" -mno-abicalls -fno-pic" + ;; + esac +} + +report_arch_toolchain() { + cat <<EOF +# elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) +ARCH_SUPPORTED+=${TARCH} +SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} +CC_${TARCH}:=${GCCPREFIX}gcc +CFLAGS_${TARCH}:=${CFLAGS} +CPP_${TARCH}:=${GCCPREFIX}cpp +AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} +LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} +NM_${TARCH}:=${GCCPREFIX}nm +OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy +OBJDUMP_${TARCH}:=${GCCPREFIX}objdump +READELF_${TARCH}:=${GCCPREFIX}readelf +STRIP_${TARCH}:=${GCCPREFIX}strip +AR_${TARCH}:=${GCCPREFIX}ar + +EOF +} + +# Architecture definition +SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv mipsel" + +arch_config_arm() { + TARCH="arm" + TBFDARCHS="littlearm" + TCLIST="armv7a armv7-a" + TWIDTH="32" + TSUPP="arm armv4 armv7" + TABI="eabi" +} + +arch_config_arm64() { + TARCH="arm64" + TBFDARCHS="littleaarch64" + TCLIST="aarch64" + TWIDTH="64" + TSUPP="arm64 armv8_64" + TABI="elf" +} + +arch_config_riscv() { + TARCH="riscv" + TBFDARCHS="littleriscv" + TCLIST="riscv" + TWIDTH="64" + TABI="elf" +} + +arch_config_x86() { + TARCH="x86_32" + TBFDARCHS="i386" + TCLIST="i386 x86_64" + TWIDTH="32" + TABI="elf" +} + +arch_config_mipsel() { + TARCH="mips" + TBFDARCHS="tradlittlemips littlemips" + TCLIST="mipsel" + TWIDTH="32" + TSUPP="mips mipsel" + TABI="elf" +} + +test_architecture() { + architecture=$1 + + GCCPREFIX="invalid" + unset TARCH TBFDARCH TCLIST TWIDTH TSUPP TABI + if type arch_config_$architecture > /dev/null; then + arch_config_$architecture + else + die "no architecture definition for $architecture" + fi + + # To override toolchain, define CROSS_COMPILE_$arch or CROSS_COMPILE as + # environment variable. + # Ex: CROSS_COMPILE_arm="armv7a-cros-linux-gnueabi-" + # CROSS_COMPILE_x86="i686-pc-linux-gnu-" + search="$(eval echo \$CROSS_COMPILE_$architecture 2>/dev/null)" + search="$search $CROSS_COMPILE" + for toolchain in $TCLIST; do + search="$search $XGCCPATH$toolchain-$TABI-" + search="$search $toolchain-$TABI-" + search="$search $toolchain-linux-gnu-" + search="$search $toolchain-" + done + echo "# $architecture TARCH_SEARCH=$search" + + # Search toolchain by checking assembler capability. + for TBFDARCH in $TBFDARCHS; do + for gccprefixes in $search ""; do + program_exists "${gccprefixes}as" || continue + testas "$gccprefixes" "$TWIDTH" "$TBFDARCH" "" && break + testas "$gccprefixes" "$TWIDTH" "$TBFDARCH" "TRUE" && break + done + [ "$GCCPREFIX" = "invalid" ] || break + done + + if [ "$GCCPREFIX" = "invalid" ]; then + echo "Warning: no suitable GCC for $architecture." >&2 + continue + fi + CC="${GCCPREFIX}"gcc + + detect_special_flags "$architecture" + report_arch_toolchain +} + +# This loops over all supported architectures. +for architecture in $SUPPORTED_ARCHITECTURE; do + test_architecture $architecture +done + diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile deleted file mode 100755 index 5809ec0..0000000 --- a/util/xcompile/xcompile +++ /dev/null @@ -1,269 +0,0 @@ -#!/bin/bash -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007-2010 coresystems GmbH -# Copyright (C) 2012 Google Inc -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -TMPFILE="" -XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} - -die() { - echo "ERROR: $*" >&2 - exit 1 -} - -clean_up() { - if [ -n "$TMPFILE" ]; then - rm -f "$TMPFILE" "$TMPFILE.c" "$TMPFILE.o" - fi -} - -# Create temporary file(s). -TMPFILE="$(mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz)" -touch "$TMPFILE" -trap clean_up EXIT - - -program_exists() { - type "$1" >/dev/null 2>&1 -} - - -if [ "$(${XGCCPATH}/iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then - IASL=${XGCCPATH}iasl -elif [ "$(iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then - IASL=iasl -else - die "no iasl found" -fi - -if program_exists gcc; then - HOSTCC=gcc -elif program_exists cc; then - HOSTCC=cc -else - die "no host compiler found" -fi - -cat <<EOF -# platform agnostic and host tools -IASL:=${IASL} -HOSTCC:=${HOSTCC} - -EOF - -testcc() { - local tmp_c="$TMPFILE.c" - local tmp_o="$TMPFILE.o" - rm -f "$tmp_c" "$tmp_o" - echo "void _start(void) {}" >"$tmp_c" - "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 -} - -testas() { - local gccprefixes="$1" - local twidth="$2" - local arch="$3" - local use_dash_twidth="$4" - local obj_file="$TMPFILE.o" - local full_arch="elf$twidth-$arch" - - rm -f "$obj_file" - [ -n "$use_dash_twidth" ] && use_dash_twidth="--$twidth" - ${gccprefixes}as $use_dash_twidth -o "$obj_file" $TMPFILE 2>/dev/null || - return 1 - - # Check output content type. - local obj_type="$(${gccprefixes}objdump -p $obj_file)" - local obj_arch="$(expr "$obj_type" : '.*format $.[a-z0-9-]*$')" - [ "$obj_arch" = "$full_arch" ] || return 1 - - # Architecture matched. - GCCPREFIX="$gccprefixes" - - if [ -z "$use_dash_twidth" ]; then - ASFLAGS="" - CFLAGS="" - LDFLAGS="" - else - ASFLAGS="--$twidth" - CFLAGS="-m$twidth" - LDFLAGS="-b $full_arch" - - fi - - # Special parameters only available in dash_twidth mode. - [ -n "$use_dash_twidth" ] && case "$full_arch" in - "elf32-i386" ) - LDFLAGS="$LDFLAGS -melf_i386" - CFLAGS="$CFLAGS -Wl,-b,elf32-i386 -Wl,-melf_i386" - ;; - esac - - return 0 -} - -detect_special_flags() { - local architecture="$1" - # GCC 4.6 is much more picky about unused variables. - # Turn off it's warnings for now: - testcc "$CC" "$CFLAGS -Wno-unused-but-set-variable " && - CFLAGS="$CFLAGS -Wno-unused-but-set-variable " - - # Use bfd linker instead of gold if available: - testcc "$CC" "$CFLAGS -fuse-ld=bfd" && - CFLAGS="$CFLAGS -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' - - testcc "$CC" "$CFLAGS -fno-stack-protector"&& - CFLAGS="$CFLAGS -fno-stack-protector" - testcc "$CC" "$CFLAGS -Wl,--build-id=none" && - CFLAGS="$CFLAGS -Wl,--build-id=none" - - case "$architecture" in - x86) - testcc "$CC" "$CFLAGS -Wa,--divide" && - CFLAGS="$CFLAGS -Wa,--divide" - # Always build for i686 -- no sse/mmx instructions since SMM - # modules are compiled using these flags. Note that this - # doesn't prevent a project using xcompile to explicitly - # specify -mmsse, etc flags. - CFLAGS="$CFLAGS -march=i686" - ;; - mipsel) - testcc "$CC" "$CFLAGS -mno-abicalls -fno-pic" && \ - CFLAGS+=" -mno-abicalls -fno-pic" - ;; - esac -} - -report_arch_toolchain() { - cat <<EOF -# elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) -ARCH_SUPPORTED+=${TARCH} -SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} -CC_${TARCH}:=${GCCPREFIX}gcc -CFLAGS_${TARCH}:=${CFLAGS} -CPP_${TARCH}:=${GCCPREFIX}cpp -AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} -LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} -NM_${TARCH}:=${GCCPREFIX}nm -OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy -OBJDUMP_${TARCH}:=${GCCPREFIX}objdump -READELF_${TARCH}:=${GCCPREFIX}readelf -STRIP_${TARCH}:=${GCCPREFIX}strip -AR_${TARCH}:=${GCCPREFIX}ar - -EOF -} - -# Architecture definition -SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv mipsel" - -arch_config_arm() { - TARCH="arm" - TBFDARCHS="littlearm" - TCLIST="armv7a armv7-a" - TWIDTH="32" - TSUPP="arm armv4 armv7" - TABI="eabi" -} - -arch_config_arm64() { - TARCH="arm64" - TBFDARCHS="littleaarch64" - TCLIST="aarch64" - TWIDTH="64" - TSUPP="arm64 armv8_64" - TABI="elf" -} - -arch_config_riscv() { - TARCH="riscv" - TBFDARCHS="littleriscv" - TCLIST="riscv" - TWIDTH="64" - TABI="elf" -} - -arch_config_x86() { - TARCH="x86_32" - TBFDARCHS="i386" - TCLIST="i386 x86_64" - TWIDTH="32" - TABI="elf" -} - -arch_config_mipsel() { - TARCH="mips" - TBFDARCHS="tradlittlemips littlemips" - TCLIST="mipsel" - TWIDTH="32" - TSUPP="mips mipsel" - TABI="elf" -} - -test_architecture() { - architecture=$1 - - GCCPREFIX="invalid" - unset TARCH TBFDARCH TCLIST TWIDTH TSUPP TABI - if type arch_config_$architecture > /dev/null; then - arch_config_$architecture - else - die "no architecture definition for $architecture" - fi - - # To override toolchain, define CROSS_COMPILE_$arch or CROSS_COMPILE as - # environment variable. - # Ex: CROSS_COMPILE_arm="armv7a-cros-linux-gnueabi-" - # CROSS_COMPILE_x86="i686-pc-linux-gnu-" - search="$(eval echo \$CROSS_COMPILE_$architecture 2>/dev/null)" - search="$search $CROSS_COMPILE" - for toolchain in $TCLIST; do - search="$search $XGCCPATH$toolchain-$TABI-" - search="$search $toolchain-$TABI-" - search="$search $toolchain-linux-gnu-" - search="$search $toolchain-" - done - echo "# $architecture TARCH_SEARCH=$search" - - # Search toolchain by checking assembler capability. - for TBFDARCH in $TBFDARCHS; do - for gccprefixes in $search ""; do - program_exists "${gccprefixes}as" || continue - testas "$gccprefixes" "$TWIDTH" "$TBFDARCH" "" && break - testas "$gccprefixes" "$TWIDTH" "$TBFDARCH" "TRUE" && break - done - [ "$GCCPREFIX" = "invalid" ] || break - done - - if [ "$GCCPREFIX" = "invalid" ]; then - echo "Warning: no suitable GCC for $architecture." >&2 - continue - fi - CC="${GCCPREFIX}"gcc - - detect_special_flags "$architecture" - report_arch_toolchain -} - -# This loops over all supported architectures. -for architecture in $SUPPORTED_ARCHITECTURE; do - test_architecture $architecture -done -

1 0

Patch set updated for coreboot: 3c4092f utils: introduce find_usbdebug.sh to help find USB debug ports
by Stefan Tauner 06 Apr '15

06 Apr '15

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9305 -gerrit commit 3c4092f1279fe3aeb797a6f02d677f8ec80d142f Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Apr 6 12:04:08 2015 +0200 utils: introduce find_usbdebug.sh to help find USB debug ports Carl-Daniel made this script a long time ago but it never was picked up in the tree. Now that USB debugging is way more common it makes sense to include it. I have made a number of changes to the original version: * -h help text * check for running as root * removed bashism * enhanced readability (test -> if) * new execution flow and refined output that better shows the device(s) attached to the debug port(s) * hiding of (bogus) error messages from lspci and lsusb Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Change-Id: Iadf775e990f5c5f91a28d57e3331d1f59acee305 --- util/find_usbdebug/find_usbdebug.sh | 149 ++++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh new file mode 100755 index 0000000..2f82219 --- /dev/null +++ b/util/find_usbdebug/find_usbdebug.sh @@ -0,0 +1,149 @@ +#!/bin/sh + +# Copyright 2008 Carl-Daniel Hailfinger +# Copyright 2015 Stefan Tauner +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. + +LANG=C +# Some tools emmit errors that don't matter (bugs in lspci/PCI firmware and lsusb). +# To shown them anyway (e.g. for debugging) comment next line. +exec 2>/dev/null + +if [ "$1" = "-h" ]; then + printf "Usage: $0 [-h | path to dmesg log] + +This script tries to find USB ports compatible with USB2/EHCI debug devices and +helps you to find their physical locations. To that end, attach at least one +uniquely identifiable device to a USB port and run this script. The device needs +to be visible in the output of \"lsusb -t\" (debug devices are often *not*!). + +After determining compatibility of the USB controllers the script will print the +devices attached to the debug port as shown by lsusb. If nothing shows up simply +switch ports and repeat the process. + +Note: usually only one port is supported for debugging.\n" + exit 0 +fi +uid=`id -u` +if [ "$uid" -ne 0 ]; then + echo "Must be run as root. Exiting." + exit 1 +fi +dmesgfile=$1 + +find_devs_in_tree () { + bus=$1 + port=$2 + busstr=`printf "Bus %02d" "$bus"` + portstr="Port $port" + + found= + # Iterate over the output of lsusb -t because it contains the physical port names + while IFS='' read -r line; do + # We need to keep track of the current bus "branch" + # Look out for lines starting with /: (that indicate a bus) + if [ "${line#*/:}" != "$line" ]; then + if [ "${line#*$busstr}" != "$line" ]; then + cur_bus=$busstr + else + cur_bus= + fi + continue + fi + + # Skip all lines not belonging to the wanted bus number + if [ "$cur_bus" != "$busstr" ]; then + continue + fi + + # check for matching physical USB port, and take only IF 0 into account + if [ "${line#*$portstr}" != "$line" -a "${line#*If 0}" != "$line" ]; then + dev=`echo ${line#*Dev } | cut -d ',' -f 1` + lsusb -s "$bus":"$dev" + found="yes" + fi + done<< EOF +$(lsusb -t) +EOF + if [ -z "$found" ]; then + echo "none" + fi +} + +debug_lspci_devs=`lspci -nvvD | + grep -i "^[0-9a-f]\|debug port" | + grep -iB1 --no-group-separator "debug port" | + grep -vi "debug port" | + cut -f 1 -d" " | + sort | + xargs echo` + +if [ -z "$debug_lspci_devs" ]; then + printf "No USB controller with debug capability found by lspci.\n +Possible reasons: lspci too old, USB controller does not support a debug device, ... Exiting.\n" + exit 1 +fi +printf "The following PCI devices support a USB debug port (says lspci): $debug_lspci_devs\n" + +debug_dmesg_devs_with_port=`( test -z "$dmesgfile" && + dmesg || + cat "$dmesgfile") | + grep -i "ehci.*debug port" | + sed "s/.* $[0-9a-f]*:*[0-9a-f]\{2\}:[0-9a-f]\{2\}\.[0-9a-f]$.*ebug port /\1 /" | + sort` + +debug_dmesg_devs=`echo "$debug_dmesg_devs_with_port" | + cut -f 1 -d" " | + xargs echo` + +if [ -z "$debug_dmesg_devs" ]; then + printf "dmesg does not show any supported ports.\n +Possible reasons: dmesg scrolled off, kernel too old, USB controller does not support a debug device, ... Exiting.\n +Note: You can specify a file containing kernel messages as an argument to this program (e.g. /var/log/dmesg)." + exit 1 +fi + +if [ "$debug_lspci_devs" != "$debug_dmesg_devs" ]; then + echo "lspci and the kernel do not agree on USB debug device support. Exiting." + exit 1 +fi + +printf "and the kernel agrees, good.\n\n" + +while true; do + for dev in $debug_dmesg_devs; do + bus=`lsusb -v | + grep "^Bus\|iSerial.*" | + grep -B1 --no-group-separator "iSerial.*$dev" | + grep "^Bus" | + sed "s/Bus *0*$[0-9a-f]*$.*/\1/"` + port=`echo "$debug_dmesg_devs_with_port" | + grep "^$dev" | + cut -f 2 -d" "` + + echo "Device(s) currently connected to the debug-capable port $port on PCI device $dev, USB bus $bus:" + + find_devs_in_tree $bus $port + echo + done + + echo "Enter 'q' to abort or anything else to repeat" + read r + if [ $? -ne 0 -o "$r" = "q" ]; then + break; + fi +done + +return 0

1 0

Patch set updated for coreboot: 884340f southbridge/amd/agesa/hudson: Fix LPC_DEV definition
by Sergej Ivanov 06 Apr '15

06 Apr '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9292 -gerrit commit 884340fa00832747e729a654aee4de3760ef3ee5 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Fri Apr 3 16:58:19 2015 +0300 southbridge/amd/agesa/hudson: Fix LPC_DEV definition In agesa code for hudson southbridge LPC_DEV is not defined, but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800. This fixes it. Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750 Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/southbridge/amd/agesa/hudson/pci_devs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index cff7dca..ebbc6f4 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -85,6 +85,7 @@ /* LPC BUS */ #define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV /* Define LPC_DEV as in sb800 source code */ #define LPC_FUNC 3 #define LPC_DEVID 0x780E #define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)

1 0

Patch set updated for coreboot: 0b4f876 vendorcode/amd/agesa/f16kb: Enable support for AM1 socket
by Sergej Ivanov 06 Apr '15

06 Apr '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9291 -gerrit commit 0b4f87647e1cf5745c13a15039d4c3a669202472 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Fri Apr 3 16:53:49 2015 +0300 vendorcode/amd/agesa/f16kb: Enable support for AM1 socket Add check for AGESA_AM1_HACK to disable package check. Default agesa for kabini doesn't know about AM1 socket so it returns FALSE, that stops memory config code. With this hack current agesa version will support AM1 Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5 Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c index 348f704..7132ce9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c @@ -489,7 +489,10 @@ MemPIsIdSupported ( return TRUE; } } - return FALSE; + if (IS_ENABLED(CONFIG_AGESA_AM1_HACK)) + return TRUE; + else + return FALSE; } /* -----------------------------------------------------------------------------*/

1 0

Patch set updated for coreboot: b2857a7 Added BIOSTAR AM1ML ver7.x mainboard support
by Sergej Ivanov 06 Apr '15

06 Apr '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9293 -gerrit commit b2857a792fc1884af7ec48919d120adc86f9d387 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Fri Apr 3 18:10:27 2015 +0300 Added BIOSTAR AM1ML ver7.x mainboard support Added am1ml board. This board has AM1 Socket and accept new amd APUs. Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/mainboard/biostar/Kconfig | 6 + src/mainboard/biostar/am1ml/BiosCallOuts.c | 163 ++++++++ src/mainboard/biostar/am1ml/Kconfig | 73 ++++ src/mainboard/biostar/am1ml/Makefile.inc | 26 ++ src/mainboard/biostar/am1ml/OptionsIds.h | 63 ++++ src/mainboard/biostar/am1ml/PlatformGnbPcie.c | 161 ++++++++ src/mainboard/biostar/am1ml/acpi/AmdImc.asl | 114 ++++++ src/mainboard/biostar/am1ml/acpi/flag0.asl | 25 ++ src/mainboard/biostar/am1ml/acpi/gpe.asl | 78 ++++ src/mainboard/biostar/am1ml/acpi/ide.asl | 249 ++++++++++++ src/mainboard/biostar/am1ml/acpi/mainboard.asl | 41 ++ src/mainboard/biostar/am1ml/acpi/routing.asl | 197 ++++++++++ src/mainboard/biostar/am1ml/acpi/sata.asl | 150 ++++++++ src/mainboard/biostar/am1ml/acpi/si.asl | 27 ++ src/mainboard/biostar/am1ml/acpi/sio.asl | 89 +++++ src/mainboard/biostar/am1ml/acpi/sleep.asl | 97 +++++ src/mainboard/biostar/am1ml/acpi/superio.asl | 112 ++++++ src/mainboard/biostar/am1ml/acpi/thermal.asl | 20 + src/mainboard/biostar/am1ml/acpi/usb_oc.asl | 132 +++++++ src/mainboard/biostar/am1ml/acpi_tables.c | 60 +++ src/mainboard/biostar/am1ml/board_info.txt | 6 + src/mainboard/biostar/am1ml/buildOpts.c | 502 +++++++++++++++++++++++++ src/mainboard/biostar/am1ml/cmos.layout | 114 ++++++ src/mainboard/biostar/am1ml/devicetree.cb | 119 ++++++ src/mainboard/biostar/am1ml/dsdt.asl | 99 +++++ src/mainboard/biostar/am1ml/irq_tables.c | 57 +++ src/mainboard/biostar/am1ml/mainboard.c | 128 +++++++ src/mainboard/biostar/am1ml/mptable.c | 169 +++++++++ src/mainboard/biostar/am1ml/romstage.c | 230 +++++++++++ 29 files changed, 3307 insertions(+) diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 7afd6a2..326edd7 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -24,9 +25,14 @@ choice config BOARD_BIOSTAR_M6TBA bool "M6TBA" +config BOARD_BIOSTAR_AM1ML + bool "AM1ML" + endchoice source "src/mainboard/biostar/m6tba/Kconfig" +source "src/mainboard/biostar/am1ml/Kconfig" + config MAINBOARD_VENDOR string diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c new file mode 100644 index 0000000..b110e98 --- /dev/null +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia.h> +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#include <stdlib.h> + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * CODEC Initialization Table for Azalia HD Audio using Realtek ALC662 chip (from linux, running under vendor bios) + */ +const CODEC_ENTRY Alc662_VerbTbl[] = +{ + { 0x14, 0x01014410 }, + { 0x15, 0x411111f0 }, + { 0x16, 0x411111f0 }, + { 0x18, 0x01a19c30 }, + { 0x19, 0x02a19c40 }, + { 0x1a, 0x0181343f }, + { 0x1b, 0x02214c20 }, + { 0x1c, 0x411111f0 }, + { 0x1d, 0x4004c601 }, + { 0x1e, 0x411111f0 }, + { 0xff, 0xffffffff } +}; + + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0662, (CODEC_ENTRY*)&Alc662_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + + + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET \n"); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.SataEnable = 1; + FchParams_reset->FchReset.IdeEnable = 0; + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV\n"); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)(&CodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ + + /* sata configuration */ + printk(BIOS_DEBUG, "Configuring SATA: selected mode = "); + FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { // code from olivehillplus (ft3b) - only one place where sata is configured + case SataLegacyIde: + case SataRaid: + case SataAhci: + case SataAhci7804: + FchParams_env->Sata.SataIdeMode = FALSE; + printk(BIOS_DEBUG, "AHCI or RAID or IDE = %x\n", CONFIG_HUDSON_SATA_MODE); + break; + + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + printk(BIOS_DEBUG, "IDE2AHCI = %x\n", CONFIG_HUDSON_SATA_MODE); + break; + } + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_env->Usb.Xhci1Enable = FALSE; + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig new file mode 100644 index 0000000..e1f1ec2 --- /dev/null +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -0,0 +1,73 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_BIOSTAR_AM1ML + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select SUPERIO_ITE_IT8728F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default biostar/am1ml + +config MAINBOARD_PART_NUMBER + string + default "AM1ML" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 10 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default n + +config AGESA_AM1_HACK + bool + default y + +endif # BOARD_BIOSTAR_AM1ML diff --git a/src/mainboard/biostar/am1ml/Makefile.inc b/src/mainboard/biostar/am1ml/Makefile.inc new file mode 100644 index 0000000..0e63e9b --- /dev/null +++ b/src/mainboard/biostar/am1ml/Makefile.inc @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/biostar/am1ml/OptionsIds.h b/src/mainboard/biostar/am1ml/OptionsIds.h new file mode 100644 index 0000000..4f051a2 --- /dev/null +++ b/src/mainboard/biostar/am1ml/OptionsIds.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED FALSE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED FALSE +//#undef IDSOPT_DEBUG_ENABLED +#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/biostar/am1ml/PlatformGnbPcie.c b/src/mainboard/biostar/am1ml/PlatformGnbPcie.c new file mode 100644 index 0000000..c807a6a --- /dev/null +++ b/src/mainboard/biostar/am1ml/PlatformGnbPcie.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Filecode.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + /* GNB PCIe topology Porting */ + + /* */ + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + /* */ + AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); + InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; + return AGESA_SUCCESS; +} + +static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; + return AGESA_SUCCESS; +} + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, + .InitMid = OemInitMid, +}; diff --git a/src/mainboard/biostar/am1ml/acpi/AmdImc.asl b/src/mainboard/biostar/am1ml/acpi/AmdImc.asl new file mode 100644 index 0000000..074dd7c --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/AmdImc.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/biostar/am1ml/acpi/flag0.asl b/src/mainboard/biostar/am1ml/acpi/flag0.asl new file mode 100644 index 0000000..7ec9c02 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/flag0.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } diff --git a/src/mainboard/biostar/am1ml/acpi/gpe.asl b/src/mainboard/biostar/am1ml/acpi/gpe.asl new file mode 100644 index 0000000..8d4f8a2 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl new file mode 100644 index 0000000..b3b4688 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No IDE functionality */ + + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + /* save total time of primary PIO master timing to PIO spd0 */ + Store(GTTM(PPTM), PSD0) + /* save total time of primary PIO slave Timing to PIO spd1 */ + Store(GTTM(PPTS), PSD1) + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/biostar/am1ml/acpi/mainboard.asl b/src/mainboard/biostar/am1ml/acpi/mainboard.asl new file mode 100644 index 0000000..05523fb --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/mainboard.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/biostar/am1ml/acpi/routing.asl b/src/mainboard/biostar/am1ml/acpi/routing.asl new file mode 100644 index 0000000..a0a53d2 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/routing.asl @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl new file mode 100644 index 0000000..04db609 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No SATA functionality */ + + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} + diff --git a/src/mainboard/biostar/am1ml/acpi/si.asl b/src/mainboard/biostar/am1ml/acpi/si.asl new file mode 100644 index 0000000..3cc2170 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/si.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/biostar/am1ml/acpi/sio.asl b/src/mainboard/biostar/am1ml/acpi/sio.asl new file mode 100644 index 0000000..66503ed --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/sio.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + OperationRegion (IOID, SystemIO, 0x2E, 0x02) + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8728 Config */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) + } + /* Exit the 8728 Config */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB700 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8728F\n") */ + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } diff --git a/src/mainboard/biostar/am1ml/acpi/sleep.asl b/src/mainboard/biostar/am1ml/acpi/sleep.asl new file mode 100644 index 0000000..2fc2efe --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/sleep.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + Store(1,USBS) + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/biostar/am1ml/acpi/superio.asl b/src/mainboard/biostar/am1ml/acpi/superio.asl new file mode 100644 index 0000000..fa08a0a --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/superio.asl @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +// Values, defined here, must match settings in devicetree.cb + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x00, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x00, 0x01) + IRQNoFlags () {12} + }) + Method (_STA, 0, NotSerialized) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x00, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x00, 0x01) + IRQNoFlags () {1} + }) + } + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } + /* This thing is untested, added for Windows + * Define LPT1 port in SPP mode + */ + + Device (LPT1) { + Name (_HID, EISAID ("PNP0400")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) + IRQNoFlags () {5} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) + IRQNoFlags () {5} + }) + } diff --git a/src/mainboard/biostar/am1ml/acpi/thermal.asl b/src/mainboard/biostar/am1ml/acpi/thermal.asl new file mode 100644 index 0000000..0466a1b --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/thermal.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No thermal zone functionality */ diff --git a/src/mainboard/biostar/am1ml/acpi/usb_oc.asl b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl new file mode 100644 index 0000000..7b5b1c6 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi/usb_oc.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ + +#if 0 /* TODO: Update for imba180 */ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} +#endif diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c new file mode 100644 index 0000000..bed62a3 --- /dev/null +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/biostar/am1ml/board_info.txt b/src/mainboard/biostar/am1ml/board_info.txt new file mode 100644 index 0000000..99d00fa --- /dev/null +++ b/src/mainboard/biostar/am1ml/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +Board URL: http://www.biostar.com.tw/app/en/mb/introduction.php?S_ID=694 +ROM package: DIP8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c new file mode 100644 index 0000000..8a0c3dc --- /dev/null +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -0,0 +1,502 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "AGESA.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FS1_SOCKET_SUPPORT TRUE + +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +//#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE +#define INSTALL_FM2_SOCKET_SUPPORT FALSE + + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE + +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled +#define BLDCFG_IOMMU_SUPPORT FALSE +#define OPTION_GFX_INIT_SVIEW FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife + +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL +#define BLDCFG_CFG_ABM_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +#ifdef PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) +#endif + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList + + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +//#define DDR400_FREQUENCY 200 ///< DDR 400 +//#define DDR533_FREQUENCY 266 ///< DDR 533 +//#define DDR667_FREQUENCY 333 ///< DDR 667 +//#define DDR800_FREQUENCY 400 ///< DDR 800 +//#define DDR1066_FREQUENCY 533 ///< DDR 1066 +//#define DDR1333_FREQUENCY 667 ///< DDR 1333 +//#define DDR1600_FREQUENCY 800 ///< DDR 1600 +//#define DDR1866_FREQUENCY 933 ///< DDR 1866 +//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +// +///* QUANDRANK_TYPE*/ +//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +// +///* USER_MEMORY_TIMING_MODE */ +//#define TIMING_MODE_AUTO 0 ///< Use best rate possible +//#define TIMING_MODE_LIMITED 1 ///< Set user top limit +//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +// +///* POWER_DOWN_MODE */ +//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 + +GPIO_CONTROL imba180_gpio[] = { + {183, Function1, GpioIn | GpioOutEnB | PullUpB}, + {-1} +}; +//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS (LAYERS_4), + + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +// Customer table +UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableTN = ARRAY_SIZE(AGESA_MEM_TABLE_TN); diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout new file mode 100644 index 0000000..f6b5806 --- /dev/null +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb new file mode 100644 index 0000000..1ee54dd --- /dev/null +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -0,0 +1,119 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1002 0x439d inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end + device pci 2.1 on end + device pci 2.2 on end + device pci 2.3 on end + device pci 2.4 on end + device pci 2.5 on end + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # there is no legacy ide + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + io 0x62 = 0 + drq 0x74 = 4 + irq 0x70 = 5 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xa40 + io 0x62 = 0xa40 + io 0x64 = 0 + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2} }, + }" + + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl new file mode 100644 index 0000000..40b79b2 --- /dev/null +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* stuff for sio */ + #include "acpi/flag0.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + + /* sio fixup */ + #include "acpi/sio.asl" + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c new file mode 100644 index 0000000..98810c6 --- /dev/null +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 10, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x3, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1002, /* Vendor */ + 0x439d, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xa6, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x00 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xdab8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xdab8}}, 0x0, 0x0}, + {0x00, (0x12 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x13 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x16 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x03, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x11 << 3) | 0x0, {{0x04, 0xdab8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x12, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c new file mode 100644 index 0000000..fed21ba --- /dev/null +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/amd_pci_util.h> +#include <northbridge/amd/agesa/family16kb/pci_devs.h> + +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, // HDA was 1F - now 03 + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-C */ + [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05, + /* SATA & MISSING IDE */ + [0x40] = 0x04, 0x04 +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* SATA & MISSING IDE*/ + [0x40] = 0x11, 0x11 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {LPC_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC }}, /* LPC: 14.3 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ +}; + +const u8 *picr_data = mainboard_picr_data; +const u8 *intr_data = mainboard_intr_data; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c new file mode 100644 index 0000000..b2851ff --- /dev/null +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam16.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); + + /* PCI_SLOT 1 */ + PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); + PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); + PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); + + /* PCI_SLOT 2 */ + PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); + PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); + + PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); + PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); + } + + /* PCIe Lan*/ + //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c new file mode 100644 index 0000000..f9f6ae6 --- /dev/null +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> +#include "cbmem.h" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + + +#define ITE_CONFIG_REG_CC 0x02 +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + + +static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value) +{ + pnp_set_logical_device(dev); + pnp_write_config(dev, reg, value); +} + +static void ite_enter_conf(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void ite_exit_conf(pnp_devfn_t dev) +{ + it_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); +} + +static void ite_evc_conf(pnp_devfn_t dev) +{ + ite_enter_conf(dev); + it_sio_write(dev, 0xf1 , 0x40 ); + it_sio_write(dev, 0xf4 , 0x80 ); + it_sio_write(dev, 0xf5 , 0x00 ); + it_sio_write(dev, 0xf6 , 0xf0 ); + it_sio_write(dev, 0xf9 , 0x48 ); + it_sio_write(dev, 0xfa , 0x00 ); + it_sio_write(dev, 0xfb , 0x00 ); + ite_exit_conf(dev); +} + +static void ite_gpio_conf(pnp_devfn_t dev) +{ + ite_enter_conf (dev); + it_sio_write (dev, 0x25 , 0x80 ); + it_sio_write (dev, 0x26 , 0x07 ); + it_sio_write (dev, 0x28 , 0x81 ); + it_sio_write (dev, 0x2c , 0x06 ); + it_sio_write (dev, 0x72 , 0x00 ); + it_sio_write (dev, 0x73 , 0x00 ); + it_sio_write (dev, 0xb3 , 0x01 ); + it_sio_write (dev, 0xb8 , 0x00 ); + it_sio_write (dev, 0xc0 , 0x00 ); + it_sio_write (dev, 0xc3 , 0x00 ); + it_sio_write (dev, 0xc8 , 0x00 ); + it_sio_write (dev, 0xc9 , 0x07 ); + it_sio_write (dev, 0xcb , 0x01 ); + it_sio_write (dev, 0xf0 , 0x10 ); + it_sio_write (dev, 0xf4 , 0x27 ); + it_sio_write (dev, 0xf8 , 0x20 ); + it_sio_write (dev, 0xf9 , 0x01 ); + ite_exit_conf (dev); +} + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val, t32; + u8 byte; + device_t dev; + u32 *addr32; + + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + amd_initmmio(); + /* Set LPC decode enables. */ + pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev2, 0x44, 0xff03ffd5); + + hudson_lpc_port80(); + + /* Enable the AcpiMmio space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + addr32 = (u32 *)0xfed80e28; + t32 = *addr32; + t32 &= 0xfff8ffff; + *addr32 = t32; + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + addr32 = (u32 *)0xfed80e40; + t32 = *addr32; + t32 &= 0xffffbffb; + *addr32 = t32; + + if (!cpu_init_detectedx && boot_cpu()) { + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + post_code(0x30); + post_code(0x31); + + /* run ite */ + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + } + printk(BIOS_DEBUG, "Console inited!\n"); + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + int i; + for(i = 0; i < 200000; i++) + val = inb(0xcd6); + + post_code(0x37); + agesawrapper_amdinitreset(); + post_code(0x38); + printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); + + post_code(0x39); + + agesawrapper_amdinitearly(); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + post_code(0x41); + agesawrapper_amdinitenv(); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + // try to config SIO GPIOs according to superiotool dump from vendor BIOS_DEBUG + printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); + ite_evc_conf(ENVC_DEV); + printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); + ite_gpio_conf(GPIO_DEV); + printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); + + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: 4b971f8 southbridge/amd/agesa/hudson: Fix LPC_DEV definition
by Sergej Ivanov 06 Apr '15

06 Apr '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9292 -gerrit commit 4b971f82b83a9e7f29fa0208595ed818f921b890 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Fri Apr 3 16:58:19 2015 +0300 southbridge/amd/agesa/hudson: Fix LPC_DEV definition In agesa code for hudson southbridge LPC_DEV is not defined, but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800. This will fix it. Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750 Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/southbridge/amd/agesa/hudson/pci_devs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index cff7dca..ebbc6f4 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -85,6 +85,7 @@ /* LPC BUS */ #define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV /* Define LPC_DEV as in sb800 source code */ #define LPC_FUNC 3 #define LPC_DEVID 0x780E #define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)

1 0

Patch set updated for coreboot: 139e791 mainboard/lenovo/t400: Add initial hybrid graphics support
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9319 -gerrit commit 139e791a0d0c11eb21f50c5684020fcb05d7560c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 18:10:09 2015 -0500 mainboard/lenovo/t400: Add initial hybrid graphics support TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux. Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 8 ++- src/mainboard/lenovo/t400/romstage.c | 125 +++++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 1da4c7c..0fe82b7 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 57dd4d1..fb16ce7 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -85,7 +85,10 @@ entries # coreboot config options: northbridge 939 3 e 11 gfx_uma_size -#942 2 r 0 unused +# coreboot config options: graphics +942 2 e 12 hybrid_graphics_mode + +#944 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -137,6 +140,9 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 5f50f32..b394aa1 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -38,6 +39,110 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 +#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 + +#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 + +#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 +#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 + +static void hybrid_graphics_set_up_gpio(void) +{ + uint32_t tmp; + + /* Enable hybrid graphics GPIO lines */ + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + + /* Set hybrid graphics control GPIO lines to output */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); + + /* Set hybrid graphics detect GPIO lines to input */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); +} + +static bool hybrid_graphics_installed(void) +{ + if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) + return false; + else + return true; +} + +static void hybrid_graphics_switch_to_integrated_graphics(void) +{ + uint32_t tmp; + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_discrete_graphics(void) +{ + uint32_t tmp; + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_configure_switchable_graphics(bool enable) +{ + uint32_t tmp; + + /* Dynamic switching is handled by the OS via ACPI */ + hybrid_graphics_switch_to_integrated_graphics(); + + if (enable) { + /* Disable integrated graphics legacy VGA cycles */ + tmp = pci_read_config32(MCH_DEV, D0F0_GGC); + pci_write_config32(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Enable secondary VGA controller */ + tmp = pci_read_config32(MCH_DEV, D0F0_DEVEN); + pci_write_config32(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); + } + else { + /* Enable integrated graphics legacy VGA cycles */ + tmp = pci_read_config32(MCH_DEV, D0F0_GGC); + pci_write_config32(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Disable secondary VGA controller */ + tmp = pci_read_config32(MCH_DEV, D0F0_DEVEN); + pci_write_config32(MCH_DEV, D0F0_DEVEN, tmp & HYBRID_GRAPHICS_SEC_VGA_EN); + } +} + static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -99,6 +204,26 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); + /* Set up hybrid graphics GPIOs */ + hybrid_graphics_set_up_gpio(); + + if (hybrid_graphics_installed()) { + /* Select appropriate hybrid graphics device */ + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); + if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) + hybrid_graphics_switch_to_integrated_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) + hybrid_graphics_switch_to_discrete_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_configure_switchable_graphics(true); + } + else { + printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); + hybrid_graphics_switch_to_integrated_graphics(); + } + /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10);

1 0

Patch set updated for coreboot: 65fed48 mainboard/lenovo/t400: Add initial ATPX ACPI implementation
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9320 -gerrit commit 65fed48aaf1ccc49130e920f087929a41c23c452 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 23:22:18 2015 -0500 mainboard/lenovo/t400: Add initial ATPX ACPI implementation Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/acpi/graphics.asl | 101 ++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/dsdt.asl | 3 + 2 files changed, 104 insertions(+) diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl new file mode 100644 index 0000000..e928d77 --- /dev/null +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* WARNING + * Switchable graphics not yet tested! + */ + +/* Hybrid graphics enable/disable GPIO bitfields */ +Name (HYG1, 0x004A0000) +Name (HYG2, 0x00020000) + +/* GPIO control port */ +Name (GPCP, DEFAULT_GPIOBASE) + +/* GPIO control map */ +OperationRegion (GPCM, SystemIO, GPCP, 0x3F) +Field (GPCM, ByteAcc, NoLock, Preserve) { + GPUS, 32, + GPIS, 32, + Offset (0x0C), + GPLV, 32, + Offset (0x30), + GQUS, 32, + GQIS, 32, + GQLV, 32 +} + +Method(SHYB, 1) { + /* Switch hybrid graphics */ + if (LEqual(Arg0, One)) + { + /* Discrete graphics requested */ + Or(GPLV, HYG1, GPLV) + Or(GQLV, HYG2, GQLV) + } + else + { + /* Integrated graphics requested */ + Xor(HYG1, 0xFFFFFFFF, Local0) + And(GPLV, Local0, GPLV) + Xor(HYG2, 0xFFFFFFFF, Local0) + And(GQLV, Local0, GQLV) + } +} + +Method (ATPX, 2, NotSerialized) { + /* Create local variables */ + Name (ATPR, Buffer (0x08) { + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 + }) + CreateWordField (ATPR, 0x00, SIZE) + CreateWordField (ATPR, 0x02, VERS) + CreateDWordField (ATPR, 0x02, MASK) + CreateDWordField (ATPR, 0x04, FUNC) + CreateDWordField (ATPR, 0x06, FLAG) + + /* Version request */ + if (LEqual(Arg0, 0x0)) + { + /* Assemble and return version information */ + Store (0x08, SIZE) /* Response length */ + Store (0x01, VERS) /* Version number */ + Store (0x0F, FUNC) /* Supported functions? */ + Return (ATPR) + } + + /* Mux select */ + if (LEqual(Arg0, 0x2)) + { + CreateByteField (Arg1, 0x02, PWST) + Store (PWST, Local0) + And (Local0, 0x01, Local0) + If (Local0) + { + /* Enable discrete graphics */ + SHYB(0x01) + } + else + { + /* Enable integrated graphics */ + SHYB(0x00) + } + } +} diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 0409e66..d2582ce 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -54,6 +54,9 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> + /* Hybrid graphics support code */ + #include "acpi/graphics.asl" + /* Dock support code */ #include "acpi/dock.asl" }

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Patch set updated for coreboot: b32008b mainboard/lenovo/t400: Add initial hybrid graphics support
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9319 -gerrit commit b32008b4f63dca25505f3e5f74bec619dbe4fc88 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 18:10:09 2015 -0500 mainboard/lenovo/t400: Add initial hybrid graphics support TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux. Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 8 ++- src/mainboard/lenovo/t400/romstage.c | 101 +++++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 1da4c7c..0fe82b7 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 57dd4d1..fb16ce7 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -85,7 +85,10 @@ entries # coreboot config options: northbridge 939 3 e 11 gfx_uma_size -#942 2 r 0 unused +# coreboot config options: graphics +942 2 e 12 hybrid_graphics_mode + +#944 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -137,6 +140,9 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 5f50f32..45447d8 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -38,6 +39,86 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 +#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 + +#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 + +static void hybrid_graphics_set_up_gpio(void) +{ + uint32_t tmp; + + /* Enable hybrid graphics GPIO lines */ + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + + /* Set hybrid graphics control GPIO lines to output */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); + + /* Set hybrid graphics detect GPIO lines to input */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); +} + +static bool hybrid_graphics_installed(void) +{ + if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) + return false; + else + return true; +} + +static void hybrid_graphics_switch_to_integrated_graphics(void) +{ + uint32_t tmp; + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_discrete_graphics(void) +{ + uint32_t tmp; + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_enable_switchable_graphics(void) +{ + /* Dynamic switching is handled by the OS via ACPI */ + hybrid_graphics_switch_to_integrated_graphics(); +} + static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -99,6 +180,26 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); + /* Set up hybrid graphics GPIOs */ + hybrid_graphics_set_up_gpio(); + + if (hybrid_graphics_installed()) { + /* Select appropriate hybrid graphics device */ + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); + if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) + hybrid_graphics_switch_to_integrated_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) + hybrid_graphics_switch_to_discrete_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_enable_switchable_graphics(); + } + else { + printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); + hybrid_graphics_switch_to_integrated_graphics(); + } + /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10);

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Patch set updated for coreboot: 29a184e mainboards/lenovo/t400: Enable serial debug option for use with dock
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9317 -gerrit commit 29a184eaf9c682f4766a89736a3643b5dee2bf8c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 17:58:01 2015 -0500 mainboards/lenovo/t400: Enable serial debug option for use with dock Change-Id: I93fcc8147586c7ca32d4805579f4185cad3d61db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 392ce692..a38af5e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO select DRIVERS_ICS_954309 select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC

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coreboot-gerrit April 2015