coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 6654ab0 kbuild: trivial - remove trailing empty lines
by gerrit＠coreboot.org 06 Apr '15

06 Apr '15

the following patch was just integrated into master: commit 6654ab02fc4566ba768cf7b861efb8b4b6ab3b8a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 6 01:26:08 2015 +0200 kbuild: trivial - remove trailing empty lines Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Change-Id: I019ba09f7371cff2699a6c854c478fec53e51126 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9311 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9311 for details. -gerrit

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Patch merged into coreboot/master: f2927e9 kconfig: lxdialog: fix spelling
by gerrit＠coreboot.org 06 Apr '15

06 Apr '15

the following patch was just integrated into master: commit f2927e9470075eb6249a53338bd27d1c50b40d6f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 6 01:22:36 2015 +0200 kconfig: lxdialog: fix spelling Signed-off-by: Brian Norris <computersforpeace(a)gmail.com> Cc: "Yann E. MORIN" <yann.morin.1998(a)free.fr> Signed-off-by: Michal Marek <mmarek(a)suse.cz> Change-Id: I033338a4a3f3a20944feace46b679c85ee32d14e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9310 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9310 for details. -gerrit

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Patch merged into coreboot/master: cce6662 kconfig: use va_end to match corresponding va_start
by gerrit＠coreboot.org 06 Apr '15

06 Apr '15

the following patch was just integrated into master: commit cce666207f23bc57845e0533c1c6f761149e0425 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 6 01:14:21 2015 +0200 kconfig: use va_end to match corresponding va_start Although on some systems va_end is a no-op, it is good practice to use va_end, especially since the manual states: "Each invocation of va_start() must be matched by a corresponding invocation of va_end() in the same function." Signed-off-by: Colin Ian King <colin.king(a)canonical.com> Signed-off-by: Michal Marek <mmarek(a)suse.cz> Change-Id: Ia08a57c37a6294e002cb6ce4c0a010c0d2edf973 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9309 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9309 for details. -gerrit

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Patch merged into coreboot/master: 3ec23b3 kbuild: trivial - use tabs for code indent where possible
by gerrit＠coreboot.org 06 Apr '15

06 Apr '15

the following patch was just integrated into master: commit 3ec23b3d51be35f871a89295fac53002904c3143 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 6 00:59:23 2015 +0200 kbuild: trivial - use tabs for code indent where possible Imported from upstream linux kernel kconfig. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ieed948c6b9c5fc40c1f3d652df11fa70ec6e93a0 Original-Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Original-Signed-off-by: Michal Marek <mmarek(a)suse.cz> Reviewed-on: http://review.coreboot.org/9308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9308 for details. -gerrit

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Patch merged into coreboot/master: 14f72bc kconfig/lxdialog: get ncurses CFLAGS with pkg-config
by gerrit＠coreboot.org 06 Apr '15

06 Apr '15

the following patch was just integrated into master: commit 14f72bc2cc2aa89d9e4cd6efcae3fcc46ea9b59b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 6 01:44:49 2015 +0200 kconfig/lxdialog: get ncurses CFLAGS with pkg-config This makes "make menuconfig" also work on systems where ncurses is not installed in a standard location (such as on NixOS). This patch changes ccflags() so that it tries pkg-config first, and only if pkg-config fails does it go back to the fallback/manual checks. This is the same algorithm that ldflags() already uses. Signed-off-by: Bjørn Forsman <bjorn.forsman(a)gmail.com> Signed-off-by: Michal Marek <mmarek(a)suse.cz> Change-Id: Ie2372ca35546c1fc2d6cf603614683312ee4ea4c Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9315 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9315 for details. -gerrit

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Patch merged into coreboot/master: ec5e5e0 New mechanism to define SRAM/memory map with automatic bounds checking
by gerrit＠coreboot.org 06 Apr '15

06 Apr '15

the following patch was just integrated into master: commit ec5e5e0db2ac923a4f80d24ffa7582c3b821d971 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Aug 20 15:29:56 2014 -0700 New mechanism to define SRAM/memory map with automatic bounds checking This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/9283 for details. -gerrit

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Patch set updated for coreboot: 341f681 mainboard/lenovo/t400: Add initial hybrid graphics support
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9319 -gerrit commit 341f68184df4ffc05dfd171f392a89c5c99a00d1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 18:10:09 2015 -0500 mainboard/lenovo/t400: Add initial hybrid graphics support TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux. Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 8 +- src/mainboard/lenovo/t400/romstage.c | 139 +++++++++++++++++++++++++++++++++ 3 files changed, 147 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 1da4c7c..0fe82b7 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 57dd4d1..fb16ce7 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -85,7 +85,10 @@ entries # coreboot config options: northbridge 939 3 e 11 gfx_uma_size -#942 2 r 0 unused +# coreboot config options: graphics +942 2 e 12 hybrid_graphics_mode + +#944 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -137,6 +140,9 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 5f50f32..6499392 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -38,6 +39,118 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 +#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 + +#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 + +#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 +#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 + +static void hybrid_graphics_configure_switchable_graphics(bool enable) +{ + uint32_t tmp; + + if (enable) { + /* Disable integrated graphics legacy VGA cycles */ + tmp = pci_read_config16(MCH_DEV, D0F0_GGC); + pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Enable secondary VGA controller */ + tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); + pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); + } + else { + /* Enable integrated graphics legacy VGA cycles */ + tmp = pci_read_config16(MCH_DEV, D0F0_GGC); + pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Disable secondary VGA controller */ + tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); + pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); + } +} + +static void hybrid_graphics_set_up_gpio(void) +{ + uint32_t tmp; + + /* Enable hybrid graphics GPIO lines */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + + /* Set hybrid graphics control GPIO lines to output */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); + + /* Set hybrid graphics detect GPIO lines to input */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); +} + +static bool hybrid_graphics_installed(void) +{ + if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) + return false; + else + return true; +} + +static void hybrid_graphics_switch_to_integrated_graphics(void) +{ + uint32_t tmp; + + /* Disable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(false); + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_discrete_graphics(void) +{ + uint32_t tmp; + + /* Disable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(false); + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_dual_graphics(void) +{ + /* Enable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(true); +} + static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -99,6 +212,27 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + + /* Set up hybrid graphics */ + hybrid_graphics_set_up_gpio(); + if (hybrid_graphics_installed()) { + /* Select appropriate hybrid graphics device */ + printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); + if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) + hybrid_graphics_switch_to_integrated_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) + hybrid_graphics_switch_to_discrete_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_switch_to_integrated_graphics(); + /* Switchable graphics are fully enabled after raminit */ + } + else { + printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); + hybrid_graphics_switch_to_integrated_graphics(); + } + /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); @@ -178,6 +312,11 @@ void main(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); + + if (hybrid_graphics_installed()) + if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_switch_to_dual_graphics(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc.

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Patch set updated for coreboot: 8b568a3 mainboard/lenovo/t400: Add initial ATPX ACPI implementation
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9320 -gerrit commit 8b568a3cdc339960fea4b88ac32d02e8557abfed Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 23:22:18 2015 -0500 mainboard/lenovo/t400: Add initial ATPX ACPI implementation Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/acpi/graphics.asl | 101 ++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/dsdt.asl | 3 + 2 files changed, 104 insertions(+) diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl new file mode 100644 index 0000000..e928d77 --- /dev/null +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* WARNING + * Switchable graphics not yet tested! + */ + +/* Hybrid graphics enable/disable GPIO bitfields */ +Name (HYG1, 0x004A0000) +Name (HYG2, 0x00020000) + +/* GPIO control port */ +Name (GPCP, DEFAULT_GPIOBASE) + +/* GPIO control map */ +OperationRegion (GPCM, SystemIO, GPCP, 0x3F) +Field (GPCM, ByteAcc, NoLock, Preserve) { + GPUS, 32, + GPIS, 32, + Offset (0x0C), + GPLV, 32, + Offset (0x30), + GQUS, 32, + GQIS, 32, + GQLV, 32 +} + +Method(SHYB, 1) { + /* Switch hybrid graphics */ + if (LEqual(Arg0, One)) + { + /* Discrete graphics requested */ + Or(GPLV, HYG1, GPLV) + Or(GQLV, HYG2, GQLV) + } + else + { + /* Integrated graphics requested */ + Xor(HYG1, 0xFFFFFFFF, Local0) + And(GPLV, Local0, GPLV) + Xor(HYG2, 0xFFFFFFFF, Local0) + And(GQLV, Local0, GQLV) + } +} + +Method (ATPX, 2, NotSerialized) { + /* Create local variables */ + Name (ATPR, Buffer (0x08) { + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 + }) + CreateWordField (ATPR, 0x00, SIZE) + CreateWordField (ATPR, 0x02, VERS) + CreateDWordField (ATPR, 0x02, MASK) + CreateDWordField (ATPR, 0x04, FUNC) + CreateDWordField (ATPR, 0x06, FLAG) + + /* Version request */ + if (LEqual(Arg0, 0x0)) + { + /* Assemble and return version information */ + Store (0x08, SIZE) /* Response length */ + Store (0x01, VERS) /* Version number */ + Store (0x0F, FUNC) /* Supported functions? */ + Return (ATPR) + } + + /* Mux select */ + if (LEqual(Arg0, 0x2)) + { + CreateByteField (Arg1, 0x02, PWST) + Store (PWST, Local0) + And (Local0, 0x01, Local0) + If (Local0) + { + /* Enable discrete graphics */ + SHYB(0x01) + } + else + { + /* Enable integrated graphics */ + SHYB(0x00) + } + } +} diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 0409e66..d2582ce 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -54,6 +54,9 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> + /* Hybrid graphics support code */ + #include "acpi/graphics.asl" + /* Dock support code */ #include "acpi/dock.asl" }

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Patch set updated for coreboot: 6bca87c nvramtool: fix getopt handling with unsigned char
by Stefan Tauner 06 Apr '15

06 Apr '15

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9307 -gerrit commit 6bca87c70eb52be415a79dc338420d161b9159b4 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Apr 5 23:13:53 2015 +0200 nvramtool: fix getopt handling with unsigned char make failed while executing "OPTION option_table.h" by printing nvramtool's usage message when crosscompiling coreboot on the BBB. The reason is the usage of char for the return value of getopt instead of int and comparing it to -1 later... although char might be unsigned as it is usually on ARM. Change-Id: Ib20fd5ef174d484bbb35f80150b8f898d95d0fe4 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/nvramtool/cli/opts.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/util/nvramtool/cli/opts.c b/util/nvramtool/cli/opts.c index 8e920e8..a128c0b 100644 --- a/util/nvramtool/cli/opts.c +++ b/util/nvramtool/cli/opts.c @@ -51,8 +51,7 @@ static const char getopt_string[] = "-ab:B:c::C:dD:e:hH:iL:l::np:r:tvw:xX:y:Y"; void parse_nvramtool_args(int argc, char *argv[]) { nvramtool_op_modifier_info_t *mod_info; - int i, op_found; - char c; + int i, op_found, c; for (i = 0, mod_info = nvramtool_op_modifiers; i < NVRAMTOOL_NUM_OP_MODIFIERS; i++, mod_info++) {

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Patch set updated for coreboot: 4868b80 mainboard/lenovo/t400: Add initial hybrid graphics support
by Timothy Pearson 06 Apr '15

06 Apr '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9319 -gerrit commit 4868b804ab3a4ff64e88b11487e1fa893c9902a7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 18:10:09 2015 -0500 mainboard/lenovo/t400: Add initial hybrid graphics support TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux. Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 8 +- src/mainboard/lenovo/t400/romstage.c | 136 +++++++++++++++++++++++++++++++++ 3 files changed, 144 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 1da4c7c..0fe82b7 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 57dd4d1..fb16ce7 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -85,7 +85,10 @@ entries # coreboot config options: northbridge 939 3 e 11 gfx_uma_size -#942 2 r 0 unused +# coreboot config options: graphics +942 2 e 12 hybrid_graphics_mode + +#944 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -137,6 +140,9 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 5f50f32..a7b8226 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -38,6 +39,121 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 +#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 + +#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 + +#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 +#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 + +static void hybrid_graphics_configure_switchable_graphics(bool enable) +{ + uint32_t tmp; + + if (enable) { + /* Disable integrated graphics legacy VGA cycles */ + tmp = pci_read_config32(MCH_DEV, D0F0_GGC); + pci_write_config32(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Enable secondary VGA controller */ + tmp = pci_read_config32(MCH_DEV, D0F0_DEVEN); + pci_write_config32(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); + } + else { + /* Enable integrated graphics legacy VGA cycles */ + tmp = pci_read_config32(MCH_DEV, D0F0_GGC); + pci_write_config32(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Disable secondary VGA controller */ + tmp = pci_read_config32(MCH_DEV, D0F0_DEVEN); + pci_write_config32(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); + } +} + +static void hybrid_graphics_set_up_gpio(void) +{ + uint32_t tmp; + + /* Enable hybrid graphics GPIO lines */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + + /* Set hybrid graphics control GPIO lines to output */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); + + /* Set hybrid graphics detect GPIO lines to input */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); +} + +static bool hybrid_graphics_installed(void) +{ + if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) + return false; + else + return true; +} + +static void hybrid_graphics_switch_to_integrated_graphics(void) +{ + uint32_t tmp; + + /* Disable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(false); + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_discrete_graphics(void) +{ + uint32_t tmp; + + /* Disable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(false); + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_dual_graphics(void) +{ + /* Enable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(true); + + /* Dynamic switching is handled by the OS via ACPI */ + hybrid_graphics_switch_to_integrated_graphics(); +} + static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -99,6 +215,26 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); + /* Set up hybrid graphics GPIOs */ + hybrid_graphics_set_up_gpio(); + + if (hybrid_graphics_installed()) { + /* Select appropriate hybrid graphics device */ + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); + if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) + hybrid_graphics_switch_to_integrated_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) + hybrid_graphics_switch_to_discrete_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_switch_to_dual_graphics(); + } + else { + printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); + hybrid_graphics_switch_to_integrated_graphics(); + } + /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10);

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coreboot-gerrit April 2015