April 2015 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: cd3a8a2 cbfstool: allow user to explicitly specify header location
by Patrick Georgi 17 Apr '15

17 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9741 -gerrit commit cd3a8a2fdc09bfaa99319438a6797c05a7189dcb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Dec 23 15:10:12 2014 -0800 cbfstool: allow user to explicitly specify header location There potentially could be multiple CBFS instances present in the firmware image. cbfstool should be able to operate on any of them, not just the first one present. To accomplish that, allow all CBFS commands to accept the -H parameter (which specifies the exact CBFS header location in the image). If this parameter is specified, the image is not searched for the CBFS header, only the specified location is checked for validity, If the location is valid, it is considered to be the CBFS header, if not - the tool exits with an error status. Note, that default behavior of the tool does not change. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=run the following experiments: - examined an image with three CBFS instances, was able to print all of them. - built a rambi coreboot image and tried the following (cbfstool output abbreviated): $ ./util/cbfstool/cbfstool /build/rambi/firmware/coreboot.rom print coreboot.rom: 8192 kB, bootblocksize 2448, romsize 8388608, offset 0x700000 alignment: 64 bytes, architecture: x86 Name Offset Type Size cmos_layout.bin 0x700000 cmos_layout 1164 ... (empty) 0x7ec600 null 77848 $ \od -tx4 -Ax /build/rambi/firmware/coreboot.rom | tail -2 7ffff0 fff67de9 000000ff fff6dfe9 fffff650 800000 $ ./util/cbfstool/cbfstool /build/rambi/firmware/coreboot.rom print -H 0x7ff650 coreboot.rom: 8192 kB, bootblocksize 2448, romsize 8388608, offset 0x700000 alignment: 64 bytes, architecture: x86 Name Offset Type Size cmos_layout.bin 0x700000 cmos_layout 1164 ... (empty) 0x7ec600 null 77848 $ ./util/cbfstool/cbfstool /build/rambi/firmware/coreboot.rom print -H 0x7ff654 E: /build/rambi/firmware/coreboot.rom does not have CBFS master header. E: Could not load ROM image '/build/rambi/firmware/coreboot.rom'. $ Change-Id: I64cbdc79096f3c7a113762b641305542af7bbd60 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 86b88222df6eed25bb176d653305e2e57e18b73a Original-Change-Id: I486092e222c96c65868ae7d41a9e8976ffcc93c4 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237485 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/cbfs_image.c | 40 +++++++++++++++++++++++--------- util/cbfstool/cbfs_image.h | 6 +++-- util/cbfstool/cbfstool.c | 58 ++++++++++++++++++++++++++++------------------ 3 files changed, 69 insertions(+), 35 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 0230d80..621a35d 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -267,7 +267,8 @@ int cbfs_image_create(struct cbfs_image *image, return 0; } -int cbfs_image_from_file(struct cbfs_image *image, const char *filename) +int cbfs_image_from_file(struct cbfs_image *image, + const char *filename, uint32_t offset) { void *header_loc; @@ -275,7 +276,9 @@ int cbfs_image_from_file(struct cbfs_image *image, const char *filename) return -1; DEBUG("read_cbfs_image: %s (%zd bytes)\n", image->buffer.name, image->buffer.size); - header_loc = cbfs_find_header(image->buffer.data, image->buffer.size); + header_loc = cbfs_find_header(image->buffer.data, + image->buffer.size, + offset); if (!header_loc) { ERROR("%s does not have CBFS master header.\n", filename); cbfs_image_delete(image); @@ -767,21 +770,41 @@ int cbfs_walk(struct cbfs_image *image, cbfs_entry_callback callback, return count; } -struct cbfs_header *cbfs_find_header(char *data, size_t size) +static int cbfs_header_valid(struct cbfs_header *header, size_t size) +{ + if ((ntohl(header->magic) == CBFS_HEADER_MAGIC) && + ((ntohl(header->version) == CBFS_HEADER_VERSION1) || + (ntohl(header->version) == CBFS_HEADER_VERSION2)) && + (ntohl(header->romsize) <= size) && + (ntohl(header->offset) < ntohl(header->romsize))) + return 1; + return 0; +} + +struct cbfs_header *cbfs_find_header(char *data, size_t size, + uint32_t forced_offset) { size_t offset; int found = 0; int32_t rel_offset; struct cbfs_header *header, *result = NULL; + if (forced_offset < (size - sizeof(struct cbfs_header))) { + /* Check if the forced header is valid. */ + header = (struct cbfs_header *)(data + forced_offset); + if (cbfs_header_valid(header, size)) + return header; + return NULL; + } + // Try finding relative offset of master header at end of file first. rel_offset = *(int32_t *)(data + size - sizeof(int32_t)); offset = size + rel_offset; DEBUG("relative offset: %#zx(-%#zx), offset: %#zx\n", (size_t)rel_offset, (size_t)-rel_offset, offset); + if (offset >= size - sizeof(*header) || - ntohl(((struct cbfs_header *)(data + offset))->magic) != - CBFS_HEADER_MAGIC) { + !cbfs_header_valid((struct cbfs_header *)(data + offset), size)) { // Some use cases append non-CBFS data to the end of the ROM. DEBUG("relative offset seems wrong, scanning whole image...\n"); offset = 0; @@ -789,13 +812,8 @@ struct cbfs_header *cbfs_find_header(char *data, size_t size) for (; offset + sizeof(*header) < size; offset++) { header = (struct cbfs_header *)(data + offset); - if (ntohl(header->magic) !=(CBFS_HEADER_MAGIC)) - continue; - if (ntohl(header->version) != CBFS_HEADER_VERSION1 && - ntohl(header->version) != CBFS_HEADER_VERSION2) { - // Probably not a real CBFS header? + if (!cbfs_header_valid(header, size)) continue; - } if (!found++) result = header; } diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 0a05eb2..2c1be3d 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -52,7 +52,8 @@ int cbfs_image_create(struct cbfs_image *image, int32_t entries_offset); /* Loads a CBFS image from file. Returns 0 on success, otherwise non-zero. */ -int cbfs_image_from_file(struct cbfs_image *image, const char *filename); +int cbfs_image_from_file(struct cbfs_image *image, + const char *filename, uint32_t offset); /* Writes a CBFS image into file. Returns 0 on success, otherwise non-zero. */ int cbfs_image_write_file(struct cbfs_image *image, const char *filename); @@ -106,7 +107,8 @@ int cbfs_walk(struct cbfs_image *image, cbfs_entry_callback callback, void *arg) * NULL (including when multiple headers were found). If there is a X86 ROM * style signature (pointer at 0xfffffffc) found in ROM, it will be selected as * the only header.*/ -struct cbfs_header *cbfs_find_header(char *data, size_t size); +struct cbfs_header *cbfs_find_header(char *data, size_t size, + uint32_t forced_offset); /* Returns the first cbfs_file entry in CBFS image by CBFS header (no matter if * the entry has valid content or not), otherwise NULL. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 9c61119..20e5e0c 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -66,6 +66,7 @@ static struct param { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, .algo = CBFS_COMPRESS_NONE, + .headeroffset = ~0, }; typedef int (*convert_buffer_t)(struct buffer *buffer, uint32_t *offset); @@ -73,7 +74,8 @@ typedef int (*convert_buffer_t)(struct buffer *buffer, uint32_t *offset); static int cbfs_add_integer_component(const char *cbfs_name, const char *name, uint64_t u64val, - uint32_t offset) { + uint32_t offset, + uint32_t headeroffset) { struct cbfs_image image; struct buffer buffer; int i, ret = 1; @@ -89,7 +91,7 @@ static int cbfs_add_integer_component(const char *cbfs_name, for (i = 0; i < 8; i++) buffer.data[i] = (u64val >> i*8) & 0xff; - if (cbfs_image_from_file(&image, cbfs_name) != 0) { + if (cbfs_image_from_file(&image, cbfs_name, headeroffset) != 0) { ERROR("Could not load ROM image '%s'.\n", cbfs_name); buffer_delete(&buffer); return 1; @@ -119,6 +121,7 @@ static int cbfs_add_component(const char *cbfs_name, const char *name, uint32_t type, uint32_t offset, + uint32_t headeroffset, convert_buffer_t convert) { struct cbfs_image image; @@ -139,7 +142,7 @@ static int cbfs_add_component(const char *cbfs_name, return 1; } - if (cbfs_image_from_file(&image, cbfs_name) != 0) { + if (cbfs_image_from_file(&image, cbfs_name, headeroffset) != 0) { ERROR("Could not load ROM image '%s'.\n", cbfs_name); return 1; } @@ -249,6 +252,7 @@ static int cbfs_add(void) param.name, param.type, param.baseaddress, + param.headeroffset, NULL); } @@ -259,6 +263,7 @@ static int cbfs_add_stage(void) param.name, CBFS_COMPONENT_STAGE, param.baseaddress, + param.headeroffset, cbfstool_convert_mkstage); } @@ -269,6 +274,7 @@ static int cbfs_add_payload(void) param.name, CBFS_COMPONENT_PAYLOAD, param.baseaddress, + param.headeroffset, cbfstool_convert_mkpayload); } @@ -289,6 +295,7 @@ static int cbfs_add_flat_binary(void) param.name, CBFS_COMPONENT_PAYLOAD, param.baseaddress, + param.headeroffset, cbfstool_convert_mkflatpayload); } @@ -297,7 +304,8 @@ static int cbfs_add_integer(void) return cbfs_add_integer_component(param.cbfs_name, param.name, param.u64val, - param.baseaddress); + param.baseaddress, + param.headeroffset); } static int cbfs_remove(void) @@ -309,7 +317,8 @@ static int cbfs_remove(void) return 1; } - if (cbfs_image_from_file(&image, param.cbfs_name) != 0) { + if (cbfs_image_from_file(&image, param.cbfs_name, + param.headeroffset) != 0) { ERROR("Could not load ROM image '%s'.\n", param.cbfs_name); return 1; @@ -433,7 +442,8 @@ static int cbfs_locate(void) return 1; } - if (cbfs_image_from_file(&image, param.cbfs_name) != 0) { + if (cbfs_image_from_file(&image, param.cbfs_name, + param.headeroffset) != 0) { ERROR("Failed to load %s.\n", param.cbfs_name); return 1; } @@ -469,7 +479,8 @@ static int cbfs_locate(void) static int cbfs_print(void) { struct cbfs_image image; - if (cbfs_image_from_file(&image, param.cbfs_name) != 0) { + if (cbfs_image_from_file(&image, param.cbfs_name, + param.headeroffset) != 0) { ERROR("Could not load ROM image '%s'.\n", param.cbfs_name); return 1; @@ -494,7 +505,8 @@ static int cbfs_extract(void) return 1; } - if (cbfs_image_from_file(&image, param.cbfs_name) != 0) { + if (cbfs_image_from_file(&image, param.cbfs_name, + param.headeroffset) != 0) { ERROR("Could not load ROM image '%s'.\n", param.cbfs_name); result = 1; @@ -523,7 +535,8 @@ static int cbfs_update_fit(void) return 1; } - if (cbfs_image_from_file(&image, param.cbfs_name) != 0) { + if (cbfs_image_from_file(&image, param.cbfs_name, + param.headeroffset) != 0) { ERROR("Could not load ROM image '%s'.\n", param.cbfs_name); return 1; @@ -538,17 +551,17 @@ static int cbfs_update_fit(void) } static const struct command commands[] = { - {"add", "f:n:t:b:vh?", cbfs_add}, - {"add-payload", "f:n:t:c:b:vh?C:I:", cbfs_add_payload}, - {"add-stage", "f:n:t:c:b:S:vh?", cbfs_add_stage}, - {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, - {"add-int", "i:n:b:vh?", cbfs_add_integer}, - {"remove", "n:vh?", cbfs_remove}, + {"add", "H;f:n:t:b:vh?", cbfs_add}, + {"add-payload", "H:f:n:t:c:b:vh?C:I:", cbfs_add_payload}, + {"add-stage", "H:f:n:t:c:b:S:vh?", cbfs_add_stage}, + {"add-flat-binary", "H:f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, + {"add-int", "H:i:n:b:vh?", cbfs_add_integer}, + {"remove", "H:n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:P:a:Tvh?", cbfs_locate}, - {"print", "vh?", cbfs_print}, - {"extract", "n:f:vh?", cbfs_extract}, - {"update-fit", "n:x:vh?", cbfs_update_fit}, + {"locate", "H:f:n:P:a:Tvh?", cbfs_locate}, + {"print", "H:vh?", cbfs_print}, + {"extract", "H:n:f:vh?", cbfs_extract}, + {"update-fit", "H:n:x:vh?", cbfs_update_fit}, }; static struct option long_options[] = { @@ -583,9 +596,10 @@ static void usage(char *name) ("cbfstool: Management utility for CBFS formatted ROM images\n\n" "USAGE:\n" " %s [-h]\n" " %s FILE COMMAND [-v] [PARAMETERS]...\n\n" "OPTIONs:\n" - " -T Output top-aligned memory address\n" - " -v Provide verbose output\n" - " -h Display this help message\n\n" + " -H header_offset Do not search for header, use this offset\n" + " -T Output top-aligned memory address\n" + " -v Provide verbose output\n" + " -h Display this help message\n\n" "COMMANDs:\n" " add -f FILE -n NAME -t TYPE [-b base-address] " "Add a component\n"

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Patch set updated for coreboot: 7091b74 cbfstool: add the missing 'break'
by Patrick Georgi 17 Apr '15

17 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9743 -gerrit commit 7091b749c8da14c888656aab7ed63d309808355e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jan 8 16:36:35 2015 -0800 cbfstool: add the missing 'break' The previous patch introduced a bug where the new added case statement was missing the break. There was no problem testing, because an unrelated parameter structure field was being modified as a result. BRANCH=storm BUG=none TEST=compiles and runs Change-Id: Iaeb328048f61ffd57057ebce47f2ac8e00fc5aac Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 27ecc130569e4252e4627052f617130a2017c645 Original-Change-Id: Ib3e6c4c2b5c37588c612b8ab2672f6845c1b4ecb Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239598 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- util/cbfstool/cbfstool.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 3ccc786..b60f199 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -758,6 +758,7 @@ int main(int argc, char **argv) case 'D': param.copyoffset = strtoul(optarg, NULL, 0); param.copyoffset_assigned = 1; + break; case 'a': param.alignment = strtoul(optarg, NULL, 0); break;

1 0

Patch set updated for coreboot: eb072f9 cbfstool: add a command to duplicate a cbfs instance
by Patrick Georgi 17 Apr '15

17 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9742 -gerrit commit eb072f9e48a956b0d88f295b52fba8b70f44d36a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Dec 23 19:26:54 2014 -0800 cbfstool: add a command to duplicate a cbfs instance The new command allows to create a file where the original CBFS image is duplicated at a different offset. The required options of the new command are -D, the offset where the copy CBFS header is placed, and -s, the size of the new CBFS copy. When a CBFS is copied, the bootblock area of the source CBFS is ignored, as well as empty and deleted files in the source CBFS. The size of the destination CBFS is calculated as the rombase size of the source CBFS less the bootblock size. The copy instance can be created in the image only above the original, which rules out the use of this new command for x86 images. If necessary, this limitation could be addressed later. As with other cbfstool commands, unless explicitly specified the lowest CBFS instance in the image is considered the source. If necessary, the user can specify the source CBFS using the -H option. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=run multiple cbfstool commands on a storm image: $ cd /tmp $ cp /build/storm/firmware/image.serial.bin storm.bin $ cbfstool storm.bin print storm.bin: 8192 kB, bootblocksize 34472, romsize 458752, offset 0x8700 alignment: 64 bytes, architecture: arm Name Offset Type Size cdt.mbn 0x8700 raw 416 ddr.mbn 0x8900 raw 25836 rpm.mbn 0xee40 raw 78576 tz.mbn 0x22180 raw 85360 fallback/verstage 0x36f40 stage 41620 fallback/romstage 0x41240 stage 19556 fallback/ramstage 0x45f00 stage 25579 config 0x4c340 raw 2878 fallback/payload 0x4cec0 payload 64811 u-boot.dtb 0x5cc40 (unknown) 2993 (empty) 0x5d840 null 75608 $ cbfstool storm.bin copy -D 0x420000 E: You need to specify -s/--size. $ cbfstool storm.bin copy -D 0x420000 -s 0x70000 $ cbfstool storm.bin print W: Multiple (2) CBFS headers found, using the first one. storm.bin: 8192 kB, bootblocksize 34472, romsize 458752, offset 0x8700 alignment: 64 bytes, architecture: arm Name Offset Type Size cdt.mbn 0x8700 raw 416 ddr.mbn 0x8900 raw 25836 rpm.mbn 0xee40 raw 78576 tz.mbn 0x22180 raw 85360 fallback/verstage 0x36f40 stage 41620 fallback/romstage 0x41240 stage 19556 fallback/ramstage 0x45f00 stage 25579 config 0x4c340 raw 2878 fallback/payload 0x4cec0 payload 64811 u-boot.dtb 0x5cc40 (unknown) 2993 (empty) 0x5d840 null 75608 cbfstool storm.bin print -H 0x420000 storm.bin: 8192 kB, bootblocksize 0, romsize 4784128, offset 0x420040 alignment: 64 bytes, architecture: arm Name Offset Type Size cdt.mbn 0x420040 raw 416 ddr.mbn 0x420240 raw 25836 rpm.mbn 0x426780 raw 78576 tz.mbn 0x439ac0 raw 85360 fallback/verstage 0x44e880 stage 41620 fallback/romstage 0x458b80 stage 19556 fallback/ramstage 0x45d840 stage 25579 config 0x463c80 raw 2878 fallback/payload 0x464800 payload 64811 u-boot.dtb 0x474580 (unknown) 2993 (empty) 0x475180 null 110168 $ cbfstool storm.bin remove -n config -H 0x420000 $ cbfstool storm.bin copy -H 0x420000 -D 0x620000 -s 0x70000 $ cbfstool storm.bin print -H 0x620000 storm.bin: 8192 kB, bootblocksize 0, romsize 6881280, offset 0x620040 alignment: 64 bytes, architecture: arm Name Offset Type Size cdt.mbn 0x620040 raw 416 ddr.mbn 0x620240 raw 25836 rpm.mbn 0x626780 raw 78576 tz.mbn 0x639ac0 raw 85360 fallback/verstage 0x64e880 stage 41620 fallback/romstage 0x658b80 stage 19556 fallback/ramstage 0x65d840 stage 25579 fallback/payload 0x663c80 payload 64811 u-boot.dtb 0x673a00 (unknown) 2993 (empty) 0x674600 null 113112 $ cbfstool /build/storm/firmware/image.serial.bin extract -n fallback/payload -f payload1 [..] $ cbfstool storm.bin extract -H 0x620000 -n fallback/payload -f payload2 [..] $ diff payload1 payload2 Change-Id: Ieb9205848aec361bb870de0d284dff06c597564f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b8d3c1b09a47ca24d2d2effc6de0e89d1b0a8903 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Change-Id: I227e607ccf7a9a8e2a1f3c6bbc506b8d29a35b1b Original-Reviewed-on: https://chromium-review.googlesource.com/237561 --- util/cbfstool/cbfs_image.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++ util/cbfstool/cbfs_image.h | 4 +++ util/cbfstool/cbfstool.c | 36 ++++++++++++++++++++ 3 files changed, 122 insertions(+) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 621a35d..9df2030 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -294,6 +294,88 @@ int cbfs_image_from_file(struct cbfs_image *image, return 0; } +int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, + size_t copy_size) +{ + struct cbfs_file *src_entry, *dst_entry; + struct cbfs_header *copy_header; + size_t align, entry_offset; + ssize_t last_entry_size; + + size_t header_offset, header_end; + size_t cbfs_offset, cbfs_end; + size_t copy_end = copy_offset + copy_size; + + align = htonl(image->header->align); + + header_offset = (char *)image->header - image->buffer.data; + header_end = header_offset + sizeof(image->header); + + cbfs_offset = htonl(image->header->offset); + cbfs_end = htonl(image->header->romsize); + + if (copy_end > image->buffer.size) { + ERROR("Copy offset out of range: [%zx:%zx)\n", + copy_offset, copy_end); + return 1; + } + + /* Range check requested copy region with header and source cbfs. */ + if ((copy_offset >= header_offset && copy_offset < header_end) || + (copy_end >= header_offset && copy_end <= header_end)) { + ERROR("New image would overlap old header.\n"); + } + + if ((copy_offset >= cbfs_offset && copy_offset < cbfs_end) || + (copy_end >= cbfs_offset && copy_end <= cbfs_end)) { + ERROR("New image would overlap old one.\n"); + return 1; + } + + /* This will work, let's create a copy. */ + copy_header = (struct cbfs_header *)(image->buffer.data + copy_offset); + *copy_header = *image->header; + + copy_header->bootblocksize = 0; + /* Romsize is a misnomer. It's the absolute limit of cbfs content.*/ + copy_header->romsize = htonl(copy_end); + entry_offset = align_up(copy_offset + sizeof(*copy_header), align); + copy_header->offset = htonl(entry_offset); + dst_entry = (struct cbfs_file *)(image->buffer.data + entry_offset); + + /* Copy non-empty files */ + for (src_entry = cbfs_find_first_entry(image); + src_entry && cbfs_is_valid_entry(image, src_entry); + src_entry = cbfs_find_next_entry(image, src_entry)) { + size_t entry_size; + + if ((src_entry->type == htonl(CBFS_COMPONENT_NULL)) || + (src_entry->type == htonl(CBFS_COMPONENT_DELETED))) + continue; + + entry_size = htonl(src_entry->len) + htonl(src_entry->offset); + memcpy(dst_entry, src_entry, entry_size); + dst_entry = (struct cbfs_file *)( + (uintptr_t)dst_entry + align_up(entry_size, align)); + + if (((char *)dst_entry - image->buffer.data) >= copy_end) { + ERROR("Ran out of room in copy region.\n"); + return 1; + } + } + + /* Last entry size is all the room above it. */ + last_entry_size = copy_end - ((char *)dst_entry - image->buffer.data) + - cbfs_calculate_file_header_size(""); + + if (last_entry_size < 0) + WARN("No room to create the last entry!\n") + else + cbfs_create_empty_entry(image, dst_entry, last_entry_size, ""); + + return 0; +} + int cbfs_image_write_file(struct cbfs_image *image, const char *filename) { assert(image && image->buffer.data); diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 2c1be3d..1e5a99f 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -55,6 +55,10 @@ int cbfs_image_create(struct cbfs_image *image, int cbfs_image_from_file(struct cbfs_image *image, const char *filename, uint32_t offset); +/* Create a duplicate CBFS image. Returns 0 on success, otherwise non-zero. */ +int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, + size_t copy_size); + /* Writes a CBFS image into file. Returns 0 on success, otherwise non-zero. */ int cbfs_image_write_file(struct cbfs_image *image, const char *filename); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 20e5e0c..3ccc786 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -47,6 +47,8 @@ static struct param { uint32_t baseaddress; uint32_t baseaddress_assigned; uint32_t loadaddress; + uint32_t copyoffset; + uint32_t copyoffset_assigned; uint32_t headeroffset; uint32_t headeroffset_assigned; uint32_t entrypoint; @@ -550,6 +552,32 @@ static int cbfs_update_fit(void) return ret; } +static int cbfs_copy(void) +{ + struct cbfs_image image; + + if (!param.copyoffset_assigned) { + ERROR("You need to specify -D/--copy_offset.\n"); + return 1; + } + + if (!param.size) { + ERROR("You need to specify -s/--size.\n"); + return 1; + } + + if (cbfs_image_from_file(&image, param.cbfs_name, + param.headeroffset) != 0) + return 1; + + if (cbfs_copy_instance(&image, param.copyoffset, param.size)) + return 1; + + /* Save the new image. */ + return buffer_write_file(&image.buffer, param.cbfs_name); + +} + static const struct command commands[] = { {"add", "H;f:n:t:b:vh?", cbfs_add}, {"add-payload", "H:f:n:t:c:b:vh?C:I:", cbfs_add_payload}, @@ -557,6 +585,7 @@ static const struct command commands[] = { {"add-flat-binary", "H:f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"add-int", "H:i:n:b:vh?", cbfs_add_integer}, {"remove", "H:n:vh?", cbfs_remove}, + {"copy", "H:D:s:", cbfs_copy}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, {"locate", "H:f:n:P:a:Tvh?", cbfs_locate}, {"print", "H:vh?", cbfs_print}, @@ -571,6 +600,7 @@ static struct option long_options[] = { {"base-address", required_argument, 0, 'b' }, {"load-address", required_argument, 0, 'l' }, {"top-aligned", required_argument, 0, 'T' }, + {"copy-offset", required_argument, 0, 'D' }, {"entry-point", required_argument, 0, 'e' }, {"size", required_argument, 0, 's' }, {"bootblock", required_argument, 0, 'B' }, @@ -616,6 +646,9 @@ static void usage(char *name) "Add a raw 64-bit integer value\n" " remove -n NAME " "Remove a component\n" + " copy -D new_header_offset -s region size \\\n" + " [-H source header offset] " + "Create a copy (duplicate) cbfs instance\n" " create -s size -m ARCH [-B bootblock] [-b bootblock offset] \\\n" " [-o CBFS offset] [-H header offset] [-a align] " "Create a ROM file\n" @@ -722,6 +755,9 @@ int main(int argc, char **argv) optarg, NULL, 0); param.headeroffset_assigned = 1; break; + case 'D': + param.copyoffset = strtoul(optarg, NULL, 0); + param.copyoffset_assigned = 1; case 'a': param.alignment = strtoul(optarg, NULL, 0); break;

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Patch merged into coreboot/master: e5d5942 cygnus: enable mmu
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit e5d5942e153a54e192644300e8dd94d53bdc2583 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Feb 17 13:43:35 2015 -0800 cygnus: enable mmu this is not only for speed but also preventing the cpu from crashing. the cpu is not happy when cache is cleaned without mmu turned on. BUG=chrome-os-partner:36691 BRANCH=broadcom-firmware TEST=boot purin to romstage. Change-Id: I2445dcc2729798c4fc56fa191cbc8471ef708d08 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9e35c925b75213e1d35bf191f22c39aaf1726eeb Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Icaf8c506df258edb99413949e6e3089a2b1a91af Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199388 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)google.com> Original-Tested-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/251306 Reviewed-on: http://review.coreboot.org/9768 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9768 for details. -gerrit

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Patch merged into coreboot/master: 128de62 cygnus: configure memlayout
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 128de62e8c433b7f9158d53364439d06fa648765 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Feb 6 12:46:38 2015 -0800 cygnus: configure memlayout we also pick no RETURN_FROM_VERSTAGE. BUG=none BRANCH=broadcom-firmware TEST=booted b0 board Change-Id: Iddd95f233a614187ae6b26f351a289c23f25742f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 243598925333982b40297adad878c461990d7d70 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I6ab96628cecb84e061777cc85d6d572823f6d63c Original-Reviewed-on: https://chromium-review.googlesource.com/251303 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9767 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9767 for details. -gerrit

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Patch merged into coreboot/master: fcfd989 cygnus: add timer functions
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit fcfd989774eaffa891666df617e3e424660769d1 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Feb 4 17:23:53 2015 -0800 cygnus: add timer functions this implements udelay. BUG=chrome-os-partner:36011 BRANCH=broadcom-firmware TEST=measured 10 sec of delay by stopwatch Change-Id: I833b71fac98a871bff71478221a55e1ca15c13df Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 137456e63931052f80247b72f98f958afdba8a27 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Ib5e33a19421eae900800fce94e9fd51bc2c665c4 Original-Reviewed-on: https://chromium-review.googlesource.com/251302 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9766 for details. -gerrit

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Patch merged into coreboot/master: 352135e urara: Define UART used for serial console
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 352135e6e8f1206da6b09350a8a356c864f41fd0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 26 07:15:01 2015 -0800 urara: Define UART used for serial console BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara with follow-up patches Change-Id: I0ed55f372e095f6b63a47734c4d223a575f63904 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a013de7daa7bf9d8a5f59e292c2a01401568d738 Original-Change-Id: I8ddf9e65a8ac3d4b09032a741b725c78251f14c9 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243212 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Reviewed-on: http://review.coreboot.org/9778 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/9778 for details. -gerrit

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Patch merged into coreboot/master: b116a1a pistachio: Move console UART to a Kconfig variable
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit b116a1aa9ce289cd27f6eed51d3ce1d7dd35377b Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 26 07:11:01 2015 -0800 pistachio: Move console UART to a Kconfig variable This allows us to define the serial console UART on a per-board basis. BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara w/ follow-up patches Change-Id: Idbb0d39bf8855df4312f7499c60b8b92826fdd07 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ed4cfdd5ed6ccbf87a50f56d3e07f2f1a9d49464 Original-Change-Id: I3faeb92f026062cded390603a610e5b8f7c9bc12 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243211 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Reviewed-on: http://review.coreboot.org/9777 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/9777 for details. -gerrit

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Patch merged into coreboot/master: d82e0cf Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig option
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit d82e0cf331b5f7f3122930808705030ed861b14e Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Feb 17 17:27:23 2015 -0800 Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig option This patch fixes a bug that caused non-x86 boards to use the poor man's assert() version with a lot more instructions per invocation and hexadecimal line numbers in __PRE_RAM__ environments. This was really just an oversight in the ARM port... even x86 uses a proper printk() in most cases (those with CAR) and there's no reason not to do so on the generally even more flexible SRAM-based architectures. Additionally, it adds a new Kconfig option to make failed assertions and BUG() calls halt again. This seems to have been the original intention, but was commented out once out of fear that this might prevent production systems from booting. It is still a useful debugging feature though (since otherwise assertions can easily just scroll past and get overlooked), so the user should be able to decide the this based on his needs. (Also changed error messages for both to include the word "ERROR", since grepping for that is the most sophisticated way we currently have to detect firmware problems. Some automated Chromium OS suspend tests check for that.) BRANCH=veyron BUG=None TEST=Booted Jerry. Compared binary sizes before and after, new version's bootblock is some ~600 bytes smaller. Change-Id: I894da18d77e12bf104e443322e2d58e60564e4b7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6a5343124719c18a1c969477e3d18bda13c0bf26 Original-Change-Id: I0268cfd67d8c894406b18bb3759a577944bcffb1 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250661 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9775 for details. -gerrit

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Patch merged into coreboot/master: f0d038f flash: use two bytes of device ID to identify stmicro chips
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit f0d038f469b1b7aa0e22bc214be1a6c9bc554ae4 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Feb 17 13:35:20 2015 -0800 flash: use two bytes of device ID to identify stmicro chips stmicro flash chips use 2 bytes as a device id: upper byte for memory type and lower byte for capacity. with this change, we will use all 2 bytes to identify a chip. BUG=none BRANCH=broadcom-firmware TEST=booted purin and verified n25q256a was identified. Change-Id: I8f382eddc4fa70d3deceb4f9d2e82026a7025629 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 12f70a1d4b7e1142afec9ce097c4a21b6225f66e Original-Change-Id: Id3378a77318fabb74ddb30f1a9549010636872ba Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199387 Original-Reviewed-by: Corneliu Doban <cdoban(a)broadcom.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)google.com> Original-Tested-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/251305 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/9774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9774 for details. -gerrit

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Patch merged into coreboot/master: 7dcc48b storm: Add STM flash support
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 7dcc48b75d1e2dc67a0543ac58f1a846ad7aadba Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Feb 11 19:16:13 2015 -0800 storm: Add STM flash support Compile in support for the STM flash devices. BRANCH=storm BUG=chrome-os-partner:33489 TEST=verified that both spansion and stm flash devices boot as expected. Change-Id: Ib616b2b52d29b20b4447c92115181a92c524ac39 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 34c0147b45551e9161e3f0e342a753907f27f9ae Original-Change-Id: I922afb91cc3ac5bf459d9746817d7677986b93cd Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248993 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9773 for details. -gerrit

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Patch merged into coreboot/master: 3b1c238 qualcomm/ipq806x: add spi_crop_chunk()
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 3b1c238778916e4fbc48e960e6ceee213da86d4f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 16 17:15:02 2015 +0200 qualcomm/ipq806x: add spi_crop_chunk() That function requirement was added upstream but not in Chromium, so add an implementation. Change-Id: Ie384b315adb205586defa730b843c7c8e96f77fb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/9776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9776 for details. -gerrit

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Patch merged into coreboot/master: e5fd1c9 spi: allow inclusion of Micronix and STM drivers in bootblock
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit e5fd1c9debb9a3c456c973265f2460df473d5a27 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Feb 11 19:13:22 2015 -0800 spi: allow inclusion of Micronix and STM drivers in bootblock Bootblock does not allow using malloc, use statically allocated chip structures instead. BRANCH=storm BUG=chrome-os-partner:33489 TEST=both drivers compile when configured in, also booted whirlwind with an STM compatible SPI NOR flash. Change-Id: I154c33ce5fc278d594205d8b8e62a56edb4e177e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: eedbb959a595e0898e7a1dd551fc7c517a02f370 Original-Change-Id: I29b37107ac1d58a293f531f59ee76b3d8c4b3e7c Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248992 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9772 for details. -gerrit

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Patch merged into coreboot/master: fc08b76 armv7: set CBFS header to zero
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit fc08b76ef5913d6859adc06fbc7bbe598d2bdcd6 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Dec 25 15:26:44 2014 -0800 armv7: set CBFS header to zero This is necessary to make sure that bootblock uses the default CBFS header (as it ought to) when multiple CBFS images support is enabled. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=with the rest of the patches applied storm boots all the way inot the Linux prompt Change-Id: I5e029d95c5cb085794c7bf5f44513b2144661e38 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 75b2c2ef6c8287db7c3e5879cacfd5dcba4391ac Original-Change-Id: I5c352921b4c9b6a3294f4658d174e0842d2ee365 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237661 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9770 for details. -gerrit

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Patch merged into coreboot/master: d6aaca9 pistachio: add DDR2 initialization code
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit d6aaca95f6792a4fd2e33883e91d33b14d9562e6 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Mon Jan 19 01:03:44 2015 +0000 pistachio: add DDR2 initialization code This is the intialization code specific to the Winbond W972GG6JB-25 part using Synopsys DDR uMCTL and DDR Phy. This is DDR2 initialization code only (currently present on the bring up board). DDR3 initialization code will follow for boards having DDR3 memory. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly DDR2 is also tested during chip sort. Corner cases (performace of DDR in different conditions) will be tested after the chip reaches a stable state. BRANCH=none Change-Id: I0093dc175d064aad03052d5281679b008c1bf012 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3d0bacea0fd5bd3b12008b47e80de8398f447785 Original-Change-Id: I8437db6c84d77c4c51a3ee2b09cd3d14913c0d16 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241424 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: http://review.coreboot.org/9769 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9769 for details. -gerrit

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Patch merged into coreboot/master: b7be358 ryu: Add support for EVT board with ID BASE3(1, 1)
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit b7be358e759cfcf9bdd2b0f650c48a3b398871c5 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Feb 23 14:40:18 2015 -0800 ryu: Add support for EVT board with ID BASE3(1,1) BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Ic5c2dafd87641879074f98d023de0379c6e2bfba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3ba476b8a436303603d7205d19f66f06c63118cd Original-Change-Id: I6a1404ff23d62100739919e8f569da2041038f01 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/252352 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/9763 for details. -gerrit

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Patch merged into coreboot/master: 4e158bc armv7: work around hang in bootblock startup code
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 4e158bcbac427b58f09fa94e22014592cf606adb Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Feb 6 19:13:34 2015 -0800 armv7: work around hang in bootblock startup code broadcom cygnus hangs if we clean caches by dcache_clean_invalidate_all at bootblock entry point. this change makes startup code call dcache_invalidate_all instead. other boards theoretically should not be affected as long as maskrom does not hand off execution to bootblock with dirty cache. BUG=chrome-os-partner:36648,chrome-os-partner:36691 BRANCH=broadcom-firmware TEST=boot cygnus b0 board, messages were printed on console: coreboot-688aae9-dirty bootblock Mon Feb 9 13:21:02 PST 2015 starting... Exception handlers installed. Change-Id: I05777ca525c97bb3d7cbb5ea7e872a602dcd5a19 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 59de5328df9d0502a3b3f7c624d3e86e038de50e Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I9b8850846b941e7e62712e90cc28ad14a68da393 Original-Reviewed-on: https://chromium-review.googlesource.com/251304 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9762 for details. -gerrit

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Patch merged into coreboot/master: f61809a storm: handle dual purpose recovery button
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit f61809ab38ddde631586da7c1345c8dc787174f4 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Feb 20 12:49:47 2015 -0800 storm: handle dual purpose recovery button Storm devices' recovery button is overloaded. Pressing it when the system is running is supposed to reset the device. To trigger recovery mode the button must be held pressed for at least 5 seconds after reset. Currently interpreting the recovery button state is the responsibility of the board (vboot gets a consolidated state, which is a combination of several conditions), so the simplest way to implement this feature is to make the board follow the recovery button state. In case the button is not pressed when it is first sampled, its state is saved immediately and no recovery request is reported. In case the button is pressed when it is first sampled, the board code keeps polling it up to 5 seconds and acts accordingly. BRANCH=storm BUG=chrome-os-partner:36059 TEST=tried starting a whirlwind with recovery button pressed for various durations, it entered recovery mode when the button was pressed longer than 5 seconds. Change-Id: Icb3250be7c2a76089c070acd68cb521d1399e245 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 45e7265bc760944f93dd98903d39d2b30aa96365 Original-Change-Id: Iab3609ebce3a74e3d0270775b83f3cf03a8837ca Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251711 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/9761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9761 for details. -gerrit

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Patch merged into coreboot/master: 20557c2 ryu: add support for p4 boards
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 20557c28ceb0117e4a5ae57b043e5e3edd385162 Author: David Riley <davidriley(a)chromium.org> Date: Tue Feb 17 15:28:10 2015 -0800 ryu: add support for p4 boards BUG=none BRANCH=none TEST=P4 board boots and selects correct dts file Change-Id: Icdfdef9b82bd53413e45713f9ceef2e0c2be16a8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0674037b1f00845ffcd129cb54571f185b42af40 Original-Change-Id: If14e2586c4ef5b44af1754b3f06126b79473798b Original-Signed-off-by: David Riley <davidriley(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250634 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9760 for details. -gerrit

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Patch merged into coreboot/master: 8920865 ipq806x: extend GSBI driver to support i2c on any GSBI block
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 89208653320c099e3c4489a43f792633d99cf4c1 Author: Sourabh Banerjee <sbanerje(a)codeaurora.org> Date: Thu Feb 19 16:43:26 2015 +0530 ipq806x: extend GSBI driver to support i2c on any GSBI block The GSBI driver is extended to be able to program the CTRL reg for any given GSBI block. The NS and MD registers programming is made more readable by programming the M, N, D and other bits of the registers individually. Defined configure structs for each QUP block to be able to track the init status for each qup. Configured GPIO8 and GPIO9 for I2C fuction. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:36722 TEST=Booted up storm P0.2, verified that the TPM on GSBI1 still works. Change-Id: I17906beedef5c80267cf114892080b121902210a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 07bc79211770decc1070c3a88874a4e452b8f5bc Original-Change-Id: I841d0d419f7339f5e5cb3385da98786eb18252ad Original-Signed-off-by: Sourabh Banerjee <sbanerje(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250763 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Trybot-Ready: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: http://review.coreboot.org/9759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9759 for details. -gerrit

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Patch merged into coreboot/master: 3cfb6a0 ipq806x: add LPASS clock control driver
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 3cfb6a066b6801186b716a4f789b69655e1e420e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Feb 11 15:13:04 2015 -0800 ipq806x: add LPASS clock control driver Add a clock control driver to initialize the clock tree inside the low-power audio subsystem. Depthcharge builds up on this to enable audio function on storm. The clock is hardcoded for 48KHz frame rate, two 16 bit channels. BRANCH=storm BUG=chrome-os-partner:35247 TEST=with depthcharge patches applied and Using depthcharge CLI audio test program verified that the target generates sensible sounds audio 100 100 audio 1000 5000 Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760 Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f Original-Signed-off-by: Kenneth Westfield <kwestfie(a)codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248830 Original-Reviewed-by: Dylan Reid <dgreid(a)chromium.org> Reviewed-on: http://review.coreboot.org/9758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9758 for details. -gerrit

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Patch merged into coreboot/master: 7f70ad6 rk3288: Add software I2C support
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 7f70ad610b23ef389c73b61a73d0920b77da4460 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Feb 9 17:40:58 2015 -0800 rk3288: Add software I2C support This patch adds the necessary platform glue to allow the use of software-driven I2C bit banging on the RK3288. This is just a debugging feature that can be used to reproduce certain I2C failure cases. Also fix Makefile verstage linking for the feature and add some new rk3288 IOMUX macros as needed. BRANCH=None BUG=None TEST=Added "CONFIG_SOFTWARE_I2C=y" to configs/config.veyron_jerry, wrapped Jerry's bootblock and verstage in software_i2c_attach/detach() calls, confirmed that both PMIC and TPM could be driven correctly with software I2C driver. Tried out different combinations of software_i2c_wedge_ack() and software_i2c_wedge_read() on the PMIC and observed transfer results with the hardware controller after reboot... the worst that would happen is that the first register read-modify-write (DCDC_ILMAX) would fail to read, but all later transfers would be fine. Since that register is written twice (due to current BUCK1 ramp implementation) and is not terribily important anyway, I think we don't need to worry about wedging problems. Change-Id: Iba801ee61d30fb1fd3aef8300612c67fa50c441b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 24dfca9bab38a20c40ef0c2dd4c775b8d8f47487 Original-Change-Id: I96777300a57c85471bad20e23a455551e9970222 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247890 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9757 for details. -gerrit

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Patch merged into coreboot/master: 1c2748d ipq806x: Add support for mmu in bootblock.
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 1c2748d113014e7e675e6ece17c6e916a6a4ec7d Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Mon Jan 12 11:57:09 2015 -0800 ipq806x: Add support for mmu in bootblock. move mmu setup from RAM stage to boot block Enabling mmu earlier, helps speed up the boot time. BRANCH=storm BUG=chrome-os-partner:35024 TEST=Verified the mmu table dump matches the programmed values. Change-Id: I8f581538d5dfd0d78538c9fe50f689d54b740685 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fb799a6d61f9c2f478434a71584d0edb94af4b59 Original-Change-Id: I110497875002a88add7eb4312a70c0de8c28bc4f Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247120 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Trevor Bourget <tbourget(a)codeaurora.org> Reviewed-on: http://review.coreboot.org/9756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9756 for details. -gerrit

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Patch merged into coreboot/master: efe279d veyron_{brain, danger, rialto}: Enable eventlogging
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit efe279d422fcdae72f9ad54b348aa445a8e45666 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 2 17:23:29 2015 -0800 veyron_{brain,danger,rialto}: Enable eventlogging This brings brain, danger, and rialto up to parity with other veyron platforms as far as eventlog functionality is concerned. BUG=chrome-os-partner:34436 BRANCH=none TEST="mosys eventlog list" shows events (tested on Brain) Change-Id: I186c5d18e5351c0eaf08ffecfd87506283c44b19 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1764bc53147718031231a6d125a4a1a96c4c6a8f Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Ief09299965f6f21bc5a40cef31cde61344025c2a Original-Reviewed-on: https://chromium-review.googlesource.com/239979 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9755 for details. -gerrit

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Patch merged into coreboot/master: 44004b3 veyron_{brain, danger, rialto}: Use common watchdog reboot
by gerrit＠coreboot.org 17 Apr '15

17 Apr '15

the following patch was just integrated into master: commit 44004b370860146409f4b099c0a1f26afafefffe Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 2 17:17:29 2015 -0800 veyron_{brain,danger,rialto}: Use common watchdog reboot This applies a previous patch ("chromeos: Provide common watchdog reboot support") to some veyron platforms that were missing it. BUG=none BRANCH=none TEST=built and booted on Brain Change-Id: I3eb431a57367b8f885844e4353a78f77515f5195 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b0c87dd4217917a35817c719efe43dd4ec442df0 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I2861939655a995d309847f64cecd974a740fae37 Original-Reviewed-on: https://chromium-review.googlesource.com/245633 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9754 for details. -gerrit

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