coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 3905cae dmp/vortex86: fix missing cpu Kconfig guards
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 3905caec3222a7ea9734be5ba202bd5b538dd609 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:35:57 2015 -0500 dmp/vortex86: fix missing cpu Kconfig guards Commit e2c2bb9 (dmp/vortex86: move PLL config to cpu Kconfig) failed to properly restrict the PLL config selection to that cpu, resulting in the selection option being present/required for all CPUs. Fix by guarding the Kconfig options with if/endif. Change-Id: Ifecf291b985ab9d0d13d6b1264d3bc9a314b8546 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: http://review.coreboot.org/10038 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10038 for details. -gerrit

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Patch merged into coreboot/master: c95ebcc vendorcode/intel: Add EDK2 header files
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit c95ebccd9a26fec56397756b98de1955fe9da556 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:13:55 2015 -0700 vendorcode/intel: Add EDK2 header files As the first step in adding support for FSP 1.1, add common header files for EDK2. Internally FSP is based upon EDK2 and uses the defines and data structures within these files for its interface. These files come from revision 16227 of the open source EDK2 tree at https://svn.code.sf.net/p/edk2/code/trunk/edk2. These files are provided in an EDK2 style tree to allow direct comparison with the EDK2 tree. Updates may be done manually to these files but only to support FSP 1.1 on UEFI 2.4. A uefi_2.5 tree should be added in the future as FSP binaries migrate to UEFI 2.5. Note: All the files were modified to use Linux line termination. BRANCH=none BUG=None TEST=Build for Braswell or Skylake boards using FSP 1.1. Change-Id: Ide5684b7eb6392e12f9f2f24215f5370c2d47c70 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/9943 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9943 for details. -gerrit

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Patch merged into coreboot/master: 405bd69 intel/broadwell: Allow using non-fake IFD descriptor
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 405bd698a6c69c2812c90c31e6ada60f63e253b7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 21:31:17 2015 +0200 intel/broadwell: Allow using non-fake IFD descriptor Change-Id: I3091437444ffd9ca3e103c41c37a5374805b1231 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10045 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10045 for details. -gerrit

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New patch to review for coreboot: 93cafd2 intel/broadwell: Allow using non-fake IFD descriptor
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10045 -gerrit commit 93cafd20094a6fea0e05b34cc3953e5f021eb0c7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 21:31:17 2015 +0200 intel/broadwell: Allow using non-fake IFD descriptor Change-Id: I3091437444ffd9ca3e103c41c37a5374805b1231 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 695e495..6cec3db 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -222,7 +222,7 @@ config ME_BIN_PATH default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" config HAVE_IFD_BIN - bool + bool "Use Intel Firmware Descriptor from existing binary" default n config BUILD_WITH_FAKE_IFD

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Patch merged into coreboot/master: 31769d9 cpu/intel/haswell: remove dependency on socket_rpga989
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 31769d99da7f97150ddc30174c7cc315ca6e7b1f Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:19:16 2015 -0500 cpu/intel/haswell: remove dependency on socket_rpga989 Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: http://review.coreboot.org/10037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10037 for details. -gerrit

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Patch set updated for coreboot: 64cfb4c cpu/intel/haswell: remove dependency on socket_rpga989
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10037 -gerrit commit 64cfb4c688007d084c10cecf2ac4314639c3888f Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:19:16 2015 -0500 cpu/intel/haswell: remove dependency on socket_rpga989 Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 2 ++ src/cpu/intel/haswell/Makefile.inc | 8 ++++++++ src/mainboard/google/bolt/Kconfig | 2 +- src/mainboard/google/bolt/devicetree.cb | 4 +--- src/mainboard/google/falco/Kconfig | 2 +- src/mainboard/google/falco/devicetree.cb | 4 +--- src/mainboard/google/panther/Kconfig | 2 +- src/mainboard/google/panther/devicetree.cb | 4 +--- src/mainboard/google/peppy/Kconfig | 2 +- src/mainboard/google/peppy/devicetree.cb | 4 +--- src/mainboard/google/slippy/Kconfig | 2 +- src/mainboard/google/slippy/devicetree.cb | 4 +--- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/baskingridge/devicetree.cb | 4 +--- 14 files changed, 22 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 741b677..00fb1d7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select SMP + select MMX + select SSE select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 82d3bec..0db0475 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -14,3 +14,11 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index c901b8f..1ec399e 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_BOLT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index f514bb4..1d1eab5 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index c836110..0f020f5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_FALCO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index 428a060..7a8e757 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 6fdb46c..f172166 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_PANTHER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index d37b622..2032fd4 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -10,10 +10,8 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 05234d0..6affd34 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_PEPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 4c0d02d..894d3ef 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 48e5825..2857c0a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_SLIPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 06ca93c..f50882c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 485ff75..b636e5b 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,7 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a173aaa..cd341d1 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -10,10 +10,8 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end

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Patch set updated for coreboot: ed48145 cpu/intel/haswell: remove dependency on socket_rpga989
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10037 -gerrit commit ed481450a4ef29403315f59bd51f5f5bf8cb0ce5 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:19:16 2015 -0500 cpu/intel/haswell: remove dependency on socket_rpga989 Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 2 ++ src/cpu/intel/haswell/Makefile.inc | 8 ++++++++ src/mainboard/google/bolt/Kconfig | 2 +- src/mainboard/google/bolt/devicetree.cb | 4 +--- src/mainboard/google/falco/Kconfig | 2 +- src/mainboard/google/falco/devicetree.cb | 4 +--- src/mainboard/google/panther/Kconfig | 2 +- src/mainboard/google/panther/devicetree.cb | 4 +--- src/mainboard/google/peppy/Kconfig | 2 +- src/mainboard/google/peppy/devicetree.cb | 4 +--- src/mainboard/google/slippy/Kconfig | 2 +- src/mainboard/google/slippy/devicetree.cb | 4 +--- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/baskingridge/devicetree.cb | 4 +--- 14 files changed, 22 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 741b677..00fb1d7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select SMP + select MMX + select SSE select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 82d3bec..0db0475 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -14,3 +14,11 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index c901b8f..1ec399e 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_BOLT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index f514bb4..1d1eab5 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index c836110..0f020f5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_FALCO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index 428a060..7a8e757 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 6fdb46c..f172166 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_PANTHER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index d37b622..c30e8f5 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -10,11 +10,9 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell # Magic APIC ID to locate this chip + device lapic 0 on end device lapic 0xACAC off end register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 05234d0..6affd34 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_PEPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 4c0d02d..894d3ef 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 48e5825..2857c0a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_SLIPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 06ca93c..f50882c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 485ff75..b636e5b 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,7 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a173aaa..cd341d1 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -10,10 +10,8 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end

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Patch merged into coreboot/master: 40e2004 intel/broadwell: bootstate mechanism only exists in ramstage
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 40e2004abf4f763f38bfb12069b683554644734a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 19:11:30 2015 +0200 intel/broadwell: bootstate mechanism only exists in ramstage So don't try to use it elsewhere. Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10030 for details. -gerrit

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Patch set updated for coreboot: d791055 dmp/vortex86: fix missing cpu Kconfig guards
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10038 -gerrit commit d79105510fbcf4b0bc6ac3eb4967df7c5e2b61c8 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:35:57 2015 -0500 dmp/vortex86: fix missing cpu Kconfig guards Commit e2c2bb9 (dmp/vortex86: move PLL config to cpu Kconfig) failed to properly restrict the PLL config selection to that cpu, resulting in the selection option being present/required for all CPUs. Fix by guarding the Kconfig options with if/endif. Change-Id: Ifecf291b985ab9d0d13d6b1264d3bc9a314b8546 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/dmp/vortex86ex/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index b14be7d..544dc09 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -19,6 +19,11 @@ config CPU_DMP_VORTEX86EX bool + +if CPU_DMP_VORTEX86EX + +config CPU_SPECIFIC_OPTIONS + def_bool y select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -71,3 +76,5 @@ config PLL_500_375_33 bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz" endchoice + +endif

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Patch set updated for coreboot: 890a099 intel/broadwell: bootstate mechanism only exists in ramstage
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10030 -gerrit commit 890a099d3107073b92ab7602aa86645be94588f0 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 19:11:30 2015 +0200 intel/broadwell: bootstate mechanism only exists in ramstage So don't try to use it elsewhere. Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 0fca059..36558a1 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,12 +312,14 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } +#if ENV_RAMSTAGE static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); +#endif int spi_claim_bus(struct spi_slave *slave) {

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coreboot-gerrit April 2015