coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 122c03d libpayload arm64: Remove the DONT_USE_DC macro
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8787 -gerrit commit 122c03db54bcda1c60dd00d8be112a4a0fc0656b Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Sep 4 15:05:03 2014 -0700 libpayload arm64: Remove the DONT_USE_DC macro By default we dont want to use the special DC instruction. Thus getting rid of the DONT_USE_DC macro and enabling code appropriately in memset.S BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and memset works fine for mmu init Change-Id: Icb3193f4f0d122726dcdacbdcacbf53eba30e235 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 54f639ef2348acab54e32b18f6826a67bf52bc14 Original-Change-Id: Id89ec2c1731d21496eca617a3c03abaf48062908 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216820 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/arch/arm64/memset.S | 106 -------------------------------- 1 file changed, 106 deletions(-) diff --git a/payloads/libpayload/arch/arm64/memset.S b/payloads/libpayload/arch/arm64/memset.S index ee8f818..15ab590 100644 --- a/payloads/libpayload/arch/arm64/memset.S +++ b/payloads/libpayload/arch/arm64/memset.S @@ -31,16 +31,6 @@ * */ -/* By default we assume that the DC instruction can be used to zero - data blocks more efficiently. In some circumstances this might be - unsafe, for example in an asymmetric multiprocessor environment with - different DC clear lengths (neither the upper nor lower lengths are - safe to use). The feature can be disabled by defining DONT_USE_DC. - - If code may be run in a virtualized environment, then define - MAYBE_VIRT. This will cause the code to cache the system register - values rather than re-reading them each call. */ - #define dstin x0 #define val w1 #define count x2 @@ -57,7 +47,6 @@ #define dst x8 #define tmp3w w9 - .macro def_fn f p2align=0 .text .p2align \p2align @@ -70,9 +59,6 @@ def_fn memset p2align=6 mov dst, dstin /* Preserve return value. */ ands A_lw, val, #255 -#ifndef DONT_USE_DC - b.eq .Lzero_mem -#endif orr A_lw, A_lw, A_lw, lsl #8 orr A_lw, A_lw, A_lw, lsl #16 orr A_l, A_l, A_l, lsl #32 @@ -148,95 +134,3 @@ def_fn memset p2align=6 add dst, dst, #16 b.ne .Ltail63 ret - -#ifndef DONT_USE_DC - /* For zeroing memory, check to see if we can use the ZVA feature to - * zero entire 'cache' lines. */ -.Lzero_mem: - mov A_l, #0 - cmp count, #63 - b.le .Ltail_maybe_tiny - neg tmp2, dst - ands tmp2, tmp2, #15 - b.eq 1f - sub count, count, tmp2 - stp A_l, A_l, [dst] - add dst, dst, tmp2 - cmp count, #63 - b.le .Ltail63 -1: - /* For zeroing small amounts of memory, it's not worth setting up - * the line-clear code. */ - cmp count, #128 - b.lt .Lnot_short -#ifdef MAYBE_VIRT - /* For efficiency when virtualized, we cache the ZVA capability. */ - adrp tmp2, .Lcache_clear - ldr zva_len, [tmp2, #:lo12:.Lcache_clear] - tbnz zva_len, #31, .Lnot_short - cbnz zva_len, .Lzero_by_line - mrs tmp1, dczid_el0 - tbz tmp1, #4, 1f - /* ZVA not available. Remember this for next time. */ - mov zva_len, #~0 - str zva_len, [tmp2, #:lo12:.Lcache_clear] - b .Lnot_short -1: - mov tmp3w, #4 - and zva_len, tmp1w, #15 /* Safety: other bits reserved. */ - lsl zva_len, tmp3w, zva_len - str zva_len, [tmp2, #:lo12:.Lcache_clear] -#else - mrs tmp1, dczid_el0 - tbnz tmp1, #4, .Lnot_short - mov tmp3w, #4 - and zva_len, tmp1w, #15 /* Safety: other bits reserved. */ - lsl zva_len, tmp3w, zva_len -#endif - -.Lzero_by_line: - /* Compute how far we need to go to become suitably aligned. We're - * already at quad-word alignment. */ - cmp count, zva_len_x - b.lt .Lnot_short /* Not enough to reach alignment. */ - sub zva_bits_x, zva_len_x, #1 - neg tmp2, dst - ands tmp2, tmp2, zva_bits_x - b.eq 1f /* Already aligned. */ - /* Not aligned, check that there's enough to copy after alignment. */ - sub tmp1, count, tmp2 - cmp tmp1, #64 - ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */ - b.lt .Lnot_short - /* We know that there's at least 64 bytes to zero and that it's safe - * to overrun by 64 bytes. */ - mov count, tmp1 -2: - stp A_l, A_l, [dst] - stp A_l, A_l, [dst, #16] - stp A_l, A_l, [dst, #32] - subs tmp2, tmp2, #64 - stp A_l, A_l, [dst, #48] - add dst, dst, #64 - b.ge 2b - /* We've overrun a bit, so adjust dst downwards. */ - add dst, dst, tmp2 -1: - sub count, count, zva_len_x -3: - dc zva, dst - add dst, dst, zva_len_x - subs count, count, zva_len_x - b.ge 3b - ands count, count, zva_bits_x - b.ne .Ltail_maybe_long - ret - .size memset, .-memset -#ifdef MAYBE_VIRT - .bss - .p2align 2 - .Lcache_clear: - .space 4 -#endif -#endif /* DONT_USE_DC */ -

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Patch set updated for coreboot: c750dc2 libpayload arm64: Add support for read and write registers at current EL in assembly
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8801 -gerrit commit c750dc24182412479d15e54ff1b39569c9bcbce6 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Aug 27 15:57:47 2014 -0700 libpayload arm64: Add support for read and write registers at current EL in assembly In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully for ryu Change-Id: I79241a944b68ebb24865e745a9835f54ab6d1a8f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2b55fbde466126c4de7f5f7bb2d1427196be842f Original-Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214576 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- .../libpayload/include/arm64/arch/lib_helpers.h | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h index f8d9546..abb08a4 100644 --- a/payloads/libpayload/include/arm64/arch/lib_helpers.h +++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h @@ -33,6 +33,61 @@ #ifndef __ARCH_LIB_HELPERS_H__ #define __ARCH_LIB_HELPERS_H__ +#ifdef __ASSEMBLY__ + +/* Macro to switch to label based on current el */ +.macro switch_el xreg label1 label2 label3 + mrs \xreg, CurrentEL + /* Currently at EL1 */ + cmp \xreg, 0x4 + b.eq \label1 + /* Currently at EL2 */ + cmp \xreg, 0x8 + b.eq \label2 + /* Currently at EL3 */ + cmp \xreg, 0xc + b.eq \label3 +.endm + +/* Macro to read sysreg at current EL + xreg - reg in which read value needs to be stored + sysreg - system reg that is to be read +*/ +.macro read_current xreg sysreg + switch_el \xreg, 101f, 102f, 103f +101: + mrs \xreg, \sysreg\()_el1 + b 104f +102: + mrs \xreg, \sysreg\()_el2 + b 104f +103: + mrs \xreg, \sysreg\()_el3 + b 104f +104: +.endm + +/* Macro to write sysreg at current EL + xreg - reg from which value needs to be written + sysreg - system reg that is to be written + temp - temp reg that can be used to read current EL +*/ +.macro write_current sysreg xreg temp + switch_el \temp, 101f, 102f, 103f +101: + msr \sysreg\()_el1, \xreg + b 104f +102: + msr \sysreg\()_el2, \xreg + b 104f +103: + msr \sysreg\()_el3, \xreg + b 104f +104: +.endm + +#else + #define EL0 0 #define EL1 1 #define EL2 2 @@ -316,4 +371,6 @@ void tlbivaa_el1(uint64_t va); /* Clock */ void set_cntfrq(uint32_t freq); +#endif // __ASSEMBLY__ + #endif //__ARCH_LIB_HELPERS_H__

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Patch set updated for coreboot: 1b7e44f libpayload arm64: Allow board to define upper address limit on DMA
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8800 -gerrit commit 1b7e44ff73b43aca65bc6a1ab6b00a7c4157362b Author: Furquan Shaikh <furquan(a)google.com> Date: Sat Jan 31 23:24:32 2015 -0800 libpayload arm64: Allow board to define upper address limit on DMA Instead of forcing boards to have DMA region below 4GiB, provide Kconfig option DMA_LIM_EXCL that a board can use to set the upper limit in MiB units on the address range reserved by DMA. By default, this value is 0x1000 i.e. 4GiB limit on the DMA upper address. BUG=None BRANCH=None TEST=Compiles successfully for rush. Default value is seen as 0x1000. Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3 Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245250 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/arch/arm64/Config.in | 4 ++++ payloads/libpayload/arch/arm64/mmu.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/arm64/Config.in b/payloads/libpayload/arch/arm64/Config.in index 0f2596c..d2f8e56 100644 --- a/payloads/libpayload/arch/arm64/Config.in +++ b/payloads/libpayload/arch/arm64/Config.in @@ -33,4 +33,8 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config DMA_LIM_EXCL + hex "DMA address limit(exclusive) in MiB units" + default 0x1000 + endif diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index da2127d..adbee0f 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -609,7 +609,7 @@ static struct mmu_memrange *mmu_add_dma_range(struct mmu_ranges *mmu_ranges) /* DMA_DEFAULT_SIZE is multiple of GRANULE_SIZE */ assert((DMA_DEFAULT_SIZE % GRANULE_SIZE) == 0); prop.size = DMA_DEFAULT_SIZE; - prop.lim_excl = MIN_64_BIT_ADDR; + prop.lim_excl = (uint64_t)CONFIG_LP_DMA_LIM_EXCL * MiB; prop.align = GRANULE_SIZE; prop.is_valid_range = NULL; prop.src_type = TYPE_NORMAL_MEM;

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Patch set updated for coreboot: 8c00055 libpayload arm64: Add console_init to enable console logs
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8781 -gerrit commit 8c000551929d6627b635671d48808c7f80ca640a Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Aug 25 15:11:57 2014 -0700 libpayload arm64: Add console_init to enable console logs BUG=None BRANCH=None TEST=Compiles sucessfully and hello libpayload seen on screen Change-Id: If312e005e306f7f70138aa27d2ef5b39620ec91e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6d6aa84d7255d33e085f12c609f32309521ff58e Original-Change-Id: I73f888a7b8aa0065c1ca0bf7857c445cc5678cdc Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214073 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/arch/arm64/main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c index ba4fc60..864e3ca 100644 --- a/payloads/libpayload/arch/arm64/main.c +++ b/payloads/libpayload/arch/arm64/main.c @@ -55,11 +55,13 @@ void start_main(void) { extern int main(int argc, char **argv); - printf("hello libpayload world"); /* Gather system information. */ lib_get_sysinfo(); - +#ifndef CONFIG_LP_SKIP_CONSOLE_INIT + console_init(); +#endif + printf("ARM64: Libpayload %s\n",__func__); exception_init(); test_exception();

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New patch to review for coreboot: 7f4d8ad libpayload arm64: Add support for read and write registers at current EL in assembly
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8801 -gerrit commit 7f4d8ada54659b86fc17333d3a32f0a933871f84 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Aug 27 15:57:47 2014 -0700 libpayload arm64: Add support for read and write registers at current EL in assembly In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully for ryu Change-Id: I79241a944b68ebb24865e745a9835f54ab6d1a8f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2b55fbde466126c4de7f5f7bb2d1427196be842f Original-Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214576 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- .../libpayload/include/arm64/arch/lib_helpers.h | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h index a8eb396..ca68435 100644 --- a/payloads/libpayload/include/arm64/arch/lib_helpers.h +++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h @@ -33,6 +33,61 @@ #ifndef __ARCH_LIB_HELPERS_H__ #define __ARCH_LIB_HELPERS_H__ +#ifdef __ASSEMBLY__ + +/* Macro to switch to label based on current el */ +.macro switch_el xreg label1 label2 label3 + mrs \xreg, CurrentEL + /* Currently at EL1 */ + cmp \xreg, 0x4 + b.eq \label1 + /* Currently at EL2 */ + cmp \xreg, 0x8 + b.eq \label2 + /* Currently at EL3 */ + cmp \xreg, 0xc + b.eq \label3 +.endm + +/* Macro to read sysreg at current EL + xreg - reg in which read value needs to be stored + sysreg - system reg that is to be read +*/ +.macro read_current xreg sysreg + switch_el \xreg, 101f, 102f, 103f +101: + mrs \xreg, \sysreg\()_el1 + b 104f +102: + mrs \xreg, \sysreg\()_el2 + b 104f +103: + mrs \xreg, \sysreg\()_el3 + b 104f +104: +.endm + +/* Macro to write sysreg at current EL + xreg - reg from which value needs to be written + sysreg - system reg that is to be written + temp - temp reg that can be used to read current EL +*/ +.macro write_current sysreg xreg temp + switch_el \temp, 101f, 102f, 103f +101: + msr \sysreg\()_el1, \xreg + b 104f +102: + msr \sysreg\()_el2, \xreg + b 104f +103: + msr \sysreg\()_el3, \xreg + b 104f +104: +.endm + +#else + #define EL0 0 #define EL1 1 #define EL2 2 @@ -347,4 +402,6 @@ void tlbivaa_el1(uint64_t va); /* Clock */ void set_cntfrq(uint32_t freq); +#endif // __ASSEMBLY__ + #endif //__ARCH_LIB_HELPERS_H__

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New patch to review for coreboot: 59512d0 libpayload arm64: Allow board to define upper address limit on DMA
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8800 -gerrit commit 59512d055a87f01fb839257bbdf5a8d31c4ca071 Author: Furquan Shaikh <furquan(a)google.com> Date: Sat Jan 31 23:24:32 2015 -0800 libpayload arm64: Allow board to define upper address limit on DMA Instead of forcing boards to have DMA region below 4GiB, provide Kconfig option DMA_LIM_EXCL that a board can use to set the upper limit in MiB units on the address range reserved by DMA. By default, this value is 0x1000 i.e. 4GiB limit on the DMA upper address. BUG=None BRANCH=None TEST=Compiles successfully for rush. Default value is seen as 0x1000. Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3 Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245250 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/arch/arm64/Config.in | 4 ++++ payloads/libpayload/arch/arm64/mmu.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/arm64/Config.in b/payloads/libpayload/arch/arm64/Config.in index 0f2596c..d2f8e56 100644 --- a/payloads/libpayload/arch/arm64/Config.in +++ b/payloads/libpayload/arch/arm64/Config.in @@ -33,4 +33,8 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config DMA_LIM_EXCL + hex "DMA address limit(exclusive) in MiB units" + default 0x1000 + endif diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index da2127d..adbee0f 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -609,7 +609,7 @@ static struct mmu_memrange *mmu_add_dma_range(struct mmu_ranges *mmu_ranges) /* DMA_DEFAULT_SIZE is multiple of GRANULE_SIZE */ assert((DMA_DEFAULT_SIZE % GRANULE_SIZE) == 0); prop.size = DMA_DEFAULT_SIZE; - prop.lim_excl = MIN_64_BIT_ADDR; + prop.lim_excl = (uint64_t)CONFIG_LP_DMA_LIM_EXCL * MiB; prop.align = GRANULE_SIZE; prop.is_valid_range = NULL; prop.src_type = TYPE_NORMAL_MEM;

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New patch to review for coreboot: ada54a9 libpayload arm64: fix mmu_disable() cache problem
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8799 -gerrit commit ada54a9805586db1ff33107f9537d9a1d313a3ce Author: HC Yen <hc.yen(a)mediatek.com> Date: Mon Jan 12 18:53:01 2015 +0800 libpayload arm64: fix mmu_disable() cache problem The raw_write_sctlr_current() cannot be used in mmu_disable() because it pushes some registers to cached stack, and then just after cache disabled, the value was gone. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee Original-Signed-off-by: HC Yen <hc.yen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240323 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm64/mmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 86d9fc5..da2127d 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -332,9 +332,10 @@ static uint32_t is_mmu_enabled(void) */ void mmu_disable(void) { + uint32_t el = get_current_el(); uint32_t sctlr; - sctlr = raw_read_sctlr_current(); + sctlr = raw_read_sctlr(el); sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I); tlbiall_current(); @@ -343,7 +344,7 @@ void mmu_disable(void) dsb(); isb(); - raw_write_sctlr_current(sctlr); + raw_write_sctlr(sctlr, el); dcache_clean_invalidate_all(); dsb();

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New patch to review for coreboot: fac8d6d libpayload arm64: Add helper functions with el argument
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8798 -gerrit commit fac8d6d1debb385f9bb7811cf51f7ec717ed5ac8 Author: HC Yen <hc.yen(a)mediatek.com> Date: Tue Jan 13 11:36:14 2015 +0800 libpayload arm64: Add helper functions with el argument Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24 Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0 Original-Signed-off-by: HC Yen <hc.yen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240322 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm64/lib/pstate.c | 32 +++- payloads/libpayload/arch/arm64/lib/sysctrl.c | 208 ++++++++++++++++++--- payloads/libpayload/arch/arm64/lib/tlb.c | 16 +- .../libpayload/include/arm64/arch/lib_helpers.h | 107 +++++++---- 4 files changed, 292 insertions(+), 71 deletions(-) diff --git a/payloads/libpayload/arch/arm64/lib/pstate.c b/payloads/libpayload/arch/arm64/lib/pstate.c index 27554f7..3215607 100644 --- a/payloads/libpayload/arch/arm64/lib/pstate.c +++ b/payloads/libpayload/arch/arm64/lib/pstate.c @@ -179,12 +179,24 @@ void raw_write_elr_el3(uint64_t elr_el3) uint64_t raw_read_elr_current(void) { - SWITCH_CASE_READ(raw_read_elr,elr,uint64_t); + uint32_t el = get_current_el(); + return raw_read_elr(el); } void raw_write_elr_current(uint64_t elr) { - SWITCH_CASE_WRITE(raw_write_elr,elr); + uint32_t el = get_current_el(); + raw_write_elr(elr, el); +} + +uint64_t raw_read_elr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_elr, elr, uint64_t, el); +} + +void raw_write_elr(uint64_t elr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_elr, elr, el); } /* FPCR */ @@ -380,12 +392,24 @@ void raw_write_spsr_el3(uint32_t spsr_el3) uint32_t raw_read_spsr_current(void) { - SWITCH_CASE_READ(raw_read_spsr,spsr,uint32_t); + uint32_t el = get_current_el(); + return raw_read_spsr(el); } void raw_write_spsr_current(uint32_t spsr) { - SWITCH_CASE_WRITE(raw_write_spsr,spsr); + uint32_t el = get_current_el(); + raw_write_spsr(spsr, el); +} + +uint32_t raw_read_spsr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_spsr, spsr, uint32_t, el); +} + +void raw_write_spsr(uint32_t spsr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_spsr, spsr, el); } uint32_t raw_read_spsr_fiq(void) diff --git a/payloads/libpayload/arch/arm64/lib/sysctrl.c b/payloads/libpayload/arch/arm64/lib/sysctrl.c index 13c9309..c9d80ff 100644 --- a/payloads/libpayload/arch/arm64/lib/sysctrl.c +++ b/payloads/libpayload/arch/arm64/lib/sysctrl.c @@ -80,12 +80,24 @@ void raw_write_actlr_el3(uint32_t actlr_el3) uint32_t raw_read_actlr_current(void) { - SWITCH_CASE_READ(raw_read_actlr,actlr,uint32_t); + uint32_t el = get_current_el(); + return raw_read_actlr(el); } void raw_write_actlr_current(uint32_t actlr) { - SWITCH_CASE_WRITE(raw_write_actlr,actlr); + uint32_t el = get_current_el(); + raw_write_actlr(actlr, el); +} + +uint32_t raw_read_actlr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_actlr, actlr, uint32_t, el); +} + +void raw_write_actlr(uint32_t actlr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_actlr, actlr, el); } /* AFSR0 */ @@ -133,12 +145,24 @@ void raw_write_afsr0_el3(uint32_t afsr0_el3) uint32_t raw_read_afsr0_current(void) { - SWITCH_CASE_READ(raw_read_afsr0,afsr0,uint32_t); + uint32_t el = get_current_el(); + return raw_read_afsr0(el); } void raw_write_afsr0_current(uint32_t afsr0) { - SWITCH_CASE_WRITE(raw_write_afsr0,afsr0); + uint32_t el = get_current_el(); + raw_write_afsr0(afsr0, el); +} + +uint32_t raw_read_afsr0(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_afsr0, afsr0, uint32_t, el); +} + +void raw_write_afsr0(uint32_t afsr0, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_afsr0, afsr0, el); } /* AFSR1 */ @@ -186,12 +210,24 @@ void raw_write_afsr1_el3(uint32_t afsr1_el3) uint32_t raw_read_afsr1_current(void) { - SWITCH_CASE_READ(raw_read_afsr1,afsr1,uint32_t); + uint32_t el = get_current_el(); + return raw_read_afsr1(el); } void raw_write_afsr1_current(uint32_t afsr1) { - SWITCH_CASE_WRITE(raw_write_afsr1,afsr1); + uint32_t el = get_current_el(); + raw_write_afsr1(afsr1, el); +} + +uint32_t raw_read_afsr1(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_afsr1, afsr1, uint32_t, el); +} + +void raw_write_afsr1(uint32_t afsr1, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_afsr1, afsr1, el); } /* AIDR */ @@ -249,12 +285,24 @@ void raw_write_amair_el3(uint64_t amair_el3) uint64_t raw_read_amair_current(void) { - SWITCH_CASE_READ(raw_read_amair,amair,uint64_t); + uint32_t el = get_current_el(); + return raw_read_amair(el); } void raw_write_amair_current(uint64_t amair) { - SWITCH_CASE_WRITE(raw_write_amair,amair); + uint32_t el = get_current_el(); + raw_write_amair(amair, el); +} + +uint64_t raw_read_amair(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_amair, amair, uint64_t, el); +} + +void raw_write_amair(uint64_t amair, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_amair, amair, el); } /* CCSIDR */ @@ -391,12 +439,24 @@ void raw_write_esr_el3(uint32_t esr_el3) uint32_t raw_read_esr_current(void) { - SWITCH_CASE_READ(raw_read_esr,esr,uint32_t); + uint32_t el = get_current_el(); + return raw_read_esr(el); } void raw_write_esr_current(uint32_t esr) { - SWITCH_CASE_WRITE(raw_write_esr,esr); + uint32_t el = get_current_el(); + raw_write_esr(esr, el); +} + +uint32_t raw_read_esr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_esr, esr, uint32_t, el); +} + +void raw_write_esr(uint32_t esr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_esr, esr, el); } /* FAR */ @@ -444,12 +504,24 @@ void raw_write_far_el3(uint64_t far_el3) uint64_t raw_read_far_current(void) { - SWITCH_CASE_READ(raw_read_far,far,uint64_t); + uint32_t el = get_current_el(); + return raw_read_far(el); } void raw_write_far_current(uint64_t far) { - SWITCH_CASE_WRITE(raw_write_far,far); + uint32_t el = get_current_el(); + raw_write_far(far, el); +} + +uint64_t raw_read_far(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_far, far, uint64_t, el); +} + +void raw_write_far(uint64_t far, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_far, far, el); } /* HCR */ @@ -522,12 +594,24 @@ void raw_write_mair_el3(uint64_t mair_el3) uint64_t raw_read_mair_current(void) { - SWITCH_CASE_READ(raw_read_mair,mair,uint64_t); + uint32_t el = get_current_el(); + return raw_read_mair(el); } void raw_write_mair_current(uint64_t mair) { - SWITCH_CASE_WRITE(raw_write_mair,mair); + uint32_t el = get_current_el(); + raw_write_mair(mair, el); +} + +uint64_t raw_read_mair(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_mair, mair, uint64_t, el); +} + +void raw_write_mair(uint64_t mair, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_mair, mair, el); } /* MPIDR */ @@ -585,12 +669,24 @@ void raw_write_rmr_el3(uint32_t rmr_el3) uint32_t raw_read_rmr_current(void) { - SWITCH_CASE_READ(raw_read_rmr,rmr,uint32_t); + uint32_t el = get_current_el(); + return raw_read_rmr(el); } void raw_write_rmr_current(uint32_t rmr) { - SWITCH_CASE_WRITE(raw_write_rmr,rmr); + uint32_t el = get_current_el(); + raw_write_rmr(rmr, el); +} + +uint32_t raw_read_rmr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_rmr, rmr, uint32_t, el); +} + +void raw_write_rmr(uint32_t rmr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_rmr, rmr, el); } /* RVBAR */ @@ -638,12 +734,24 @@ void raw_write_rvbar_el3(uint64_t rvbar_el3) uint64_t raw_read_rvbar_current(void) { - SWITCH_CASE_READ(raw_read_rvbar,rvbar,uint64_t); + uint32_t el = get_current_el(); + return raw_read_rvbar(el); } void raw_write_rvbar_current(uint64_t rvbar) { - SWITCH_CASE_WRITE(raw_write_rvbar,rvbar); + uint32_t el = get_current_el(); + raw_write_rvbar(rvbar, el); +} + +uint64_t raw_read_rvbar(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_rvbar, rvbar, uint64_t, el); +} + +void raw_write_rvbar(uint64_t rvbar, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_rvbar, rvbar, el); } /* SCR */ @@ -706,12 +814,24 @@ void raw_write_sctlr_el3(uint32_t sctlr_el3) uint32_t raw_read_sctlr_current(void) { - SWITCH_CASE_READ(raw_read_sctlr,sctlr,uint32_t); + uint32_t el = get_current_el(); + return raw_read_sctlr(el); } void raw_write_sctlr_current(uint32_t sctlr) { - SWITCH_CASE_WRITE(raw_write_sctlr,sctlr); + uint32_t el = get_current_el(); + raw_write_sctlr(sctlr, el); +} + +uint32_t raw_read_sctlr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_sctlr, sctlr, uint32_t, el); +} + +void raw_write_sctlr(uint32_t sctlr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_sctlr, sctlr, el); } /* TCR */ @@ -759,12 +879,24 @@ void raw_write_tcr_el3(uint32_t tcr_el3) uint64_t raw_read_tcr_current(void) { - SWITCH_CASE_READ(raw_read_tcr, tcr, uint64_t); + uint32_t el = get_current_el(); + return raw_read_tcr(el); } void raw_write_tcr_current(uint64_t tcr) { - SWITCH_CASE_WRITE(raw_write_tcr, tcr); + uint32_t el = get_current_el(); + raw_write_tcr(tcr, el); +} + +uint64_t raw_read_tcr(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_tcr, tcr, uint64_t, el); +} + +void raw_write_tcr(uint64_t tcr, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_tcr, tcr, el); } /* TTBR0 */ @@ -812,12 +944,24 @@ void raw_write_ttbr0_el3(uint64_t ttbr0_el3) uint64_t raw_read_ttbr0_current(void) { - SWITCH_CASE_READ(raw_read_ttbr0,ttbr0,uint64_t); + uint32_t el = get_current_el(); + return raw_read_ttbr0(el); } void raw_write_ttbr0_current(uint64_t ttbr0) { - SWITCH_CASE_WRITE(raw_write_ttbr0,ttbr0); + uint32_t el = get_current_el(); + raw_write_ttbr0(ttbr0, el); +} + +uint64_t raw_read_ttbr0(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_ttbr0, ttbr0, uint64_t, el); +} + +void raw_write_ttbr0(uint64_t ttbr0, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_ttbr0, ttbr0, el); } /* TTBR1 */ @@ -880,10 +1024,22 @@ void raw_write_vbar_el3(uint64_t vbar_el3) uint64_t raw_read_vbar_current(void) { - SWITCH_CASE_READ(raw_read_vbar,vbar,uint64_t); + uint32_t el = get_current_el(); + return raw_read_vbar(el); } void raw_write_vbar_current(uint64_t vbar) { - SWITCH_CASE_WRITE(raw_write_vbar,vbar); + uint32_t el = get_current_el(); + raw_write_vbar(vbar, el); +} + +uint64_t raw_read_vbar(uint32_t el) +{ + SWITCH_CASE_READ(raw_read_vbar, vbar, uint64_t, el); +} + +void raw_write_vbar(uint64_t vbar, uint32_t el) +{ + SWITCH_CASE_WRITE(raw_write_vbar, vbar, el); } diff --git a/payloads/libpayload/arch/arm64/lib/tlb.c b/payloads/libpayload/arch/arm64/lib/tlb.c index d5afc17..d80783d 100644 --- a/payloads/libpayload/arch/arm64/lib/tlb.c +++ b/payloads/libpayload/arch/arm64/lib/tlb.c @@ -52,7 +52,13 @@ void tlbiall_el3(void) void tlbiall_current(void) { - SWITCH_CASE_TLBI(tlbiall); + uint32_t el = get_current_el(); + tlbiall(el); +} + +void tlbiall(uint32_t el) +{ + SWITCH_CASE_TLBI(tlbiall, el); } /* TLBIALLIS */ @@ -73,7 +79,13 @@ void tlbiallis_el3(void) void tlbiallis_current(void) { - SWITCH_CASE_TLBI(tlbiallis); + uint32_t el = get_current_el(); + tlbiallis(el); +} + +void tlbiallis(uint32_t el) +{ + SWITCH_CASE_TLBI(tlbiallis, el); } /* TLBIVAA */ diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h index 3adba81..a8eb396 100644 --- a/payloads/libpayload/include/arm64/arch/lib_helpers.h +++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h @@ -41,57 +41,56 @@ #define CURRENT_EL_MASK 0x3 #define CURRENT_EL_SHIFT 2 +#include <stdint.h> + #define DAIF_DBG_BIT (1<<3) #define DAIF_ABT_BIT (1<<2) #define DAIF_IRQ_BIT (1<<1) #define DAIF_FIQ_BIT (1<<0) -#define SWITCH_CASE_READ(func,var,type) do { \ - type var = -1; \ - uint8_t current_el = get_current_el(); \ - switch(current_el) { \ - case EL1: \ - var = func##_el1(); \ - break; \ - case EL2: \ - var = func##_el2(); \ - break; \ - case EL3: \ - var = func##_el3(); \ - break; \ - } \ - return var; \ - } while(0) +#define SWITCH_CASE_READ(func, var, type, el) do { \ + type var = -1; \ + switch (el) { \ + case EL1: \ + var = func##_el1(); \ + break; \ + case EL2: \ + var = func##_el2(); \ + break; \ + case EL3: \ + var = func##_el3(); \ + break; \ + } \ + return var; \ + } while (0) -#define SWITCH_CASE_WRITE(func,var) do { \ - uint8_t current_el = get_current_el(); \ - switch(current_el) { \ - case EL1: \ - func##_el1(var); \ - break; \ - case EL2: \ - func##_el2(var); \ - break; \ - case EL3: \ - func##_el3(var); \ - break; \ - } \ - } while(0) +#define SWITCH_CASE_WRITE(func, var, el) do { \ + switch (el) { \ + case EL1: \ + func##_el1(var); \ + break; \ + case EL2: \ + func##_el2(var); \ + break; \ + case EL3: \ + func##_el3(var); \ + break; \ + } \ + } while (0) -#define SWITCH_CASE_TLBI(func) do { \ - uint8_t current_el = get_current_el(); \ - switch(current_el) { \ - case EL1: \ +#define SWITCH_CASE_TLBI(func, el) do { \ + switch (el) { \ + case EL1: \ func##_el1(); \ break; \ - case EL2: \ + case EL2: \ func##_el2(); \ break; \ - case EL3: \ + case EL3: \ func##_el3(); \ break; \ } \ - } while(0) + } while (0) /* PSTATE and special purpose register access functions */ uint32_t raw_read_current_el(void); @@ -118,6 +117,8 @@ uint64_t raw_read_elr_el3(void); void raw_write_elr_el3(uint64_t elr_el3); uint64_t raw_read_elr_current(void); void raw_write_elr_current(uint64_t elr); +uint64_t raw_read_elr(uint32_t el); +void raw_write_elr(uint64_t elr, uint32_t el); uint32_t raw_read_fpcr(void); void raw_write_fpcr(uint32_t fpcr); uint32_t raw_read_fpsr(void); @@ -144,6 +145,8 @@ uint32_t raw_read_spsr_el3(void); void raw_write_spsr_el3(uint32_t spsr_el3); uint32_t raw_read_spsr_current(void); void raw_write_spsr_current(uint32_t spsr); +uint32_t raw_read_spsr(uint32_t el); +void raw_write_spsr(uint32_t spsr, uint32_t el); uint32_t raw_read_spsr_fiq(void); void raw_write_spsr_fiq(uint32_t spsr_fiq); uint32_t raw_read_spsr_irq(void); @@ -160,6 +163,8 @@ uint32_t raw_read_actlr_el3(void); void raw_write_actlr_el3(uint32_t actlr_el3); uint32_t raw_read_actlr_current(void); void raw_write_actlr_current(uint32_t actlr); +uint32_t raw_read_actlr(uint32_t el); +void raw_write_actlr(uint32_t actlr, uint32_t el); uint32_t raw_read_afsr0_el1(void); void raw_write_afsr0_el1(uint32_t afsr0_el1); uint32_t raw_read_afsr0_el2(void); @@ -168,6 +173,8 @@ uint32_t raw_read_afsr0_el3(void); void raw_write_afsr0_el3(uint32_t afsr0_el3); uint32_t raw_read_afsr0_current(void); void raw_write_afsr0_current(uint32_t afsr0); +uint32_t raw_read_afsr0(uint32_t el); +void raw_write_afsr0(uint32_t afsr0, uint32_t el); uint32_t raw_read_afsr1_el1(void); void raw_write_afsr1_el1(uint32_t afsr1_el1); uint32_t raw_read_afsr1_el2(void); @@ -176,6 +183,8 @@ uint32_t raw_read_afsr1_el3(void); void raw_write_afsr1_el3(uint32_t afsr1_el3); uint32_t raw_read_afsr1_current(void); void raw_write_afsr1_current(uint32_t afsr1); +uint32_t raw_read_afsr1(uint32_t el); +void raw_write_afsr1(uint32_t afsr1, uint32_t el); uint32_t raw_read_aidr_el1(void); uint64_t raw_read_amair_el1(void); void raw_write_amair_el1(uint64_t amair_el1); @@ -185,6 +194,8 @@ uint64_t raw_read_amair_el3(void); void raw_write_amair_el3(uint64_t amair_el3); uint64_t raw_read_amair_current(void); void raw_write_amair_current(uint64_t amair); +uint64_t raw_read_amair(uint32_t el); +void raw_write_amair(uint64_t amair, uint32_t el); uint32_t raw_read_ccsidr_el1(void); uint32_t raw_read_clidr_el1(void); uint32_t raw_read_cpacr_el1(void); @@ -193,8 +204,6 @@ uint32_t raw_read_cptr_el2(void); void raw_write_cptr_el2(uint32_t cptr_el2); uint32_t raw_read_cptr_el3(void); void raw_write_cptr_el3(uint32_t cptr_el3); -uint32_t raw_read_cptr_current(void); -void raw_write_cptr_current(uint32_t cptr); uint32_t raw_read_csselr_el1(void); void raw_write_csselr_el1(uint32_t csselr_el1); uint32_t raw_read_ctr_el0(void); @@ -206,6 +215,8 @@ uint32_t raw_read_esr_el3(void); void raw_write_esr_el3(uint32_t esr_el3); uint32_t raw_read_esr_current(void); void raw_write_esr_current(uint32_t esr); +uint32_t raw_read_esr(uint32_t el); +void raw_write_esr(uint32_t esr, uint32_t el); uint64_t raw_read_far_el1(void); void raw_write_far_el1(uint64_t far_el1); uint64_t raw_read_far_el2(void); @@ -214,6 +225,8 @@ uint64_t raw_read_far_el3(void); void raw_write_far_el3(uint64_t far_el3); uint64_t raw_read_far_current(void); void raw_write_far_current(uint64_t far); +uint64_t raw_read_far(uint32_t el); +void raw_write_far(uint64_t far, uint32_t el); uint64_t raw_read_hcr_el2(void); void raw_write_hcr_el2(uint64_t hcr_el2); uint64_t raw_read_aa64pfr0_el1(void); @@ -225,6 +238,8 @@ uint64_t raw_read_mair_el3(void); void raw_write_mair_el3(uint64_t mair_el3); uint64_t raw_read_mair_current(void); void raw_write_mair_current(uint64_t mair); +uint64_t raw_read_mair(uint32_t el); +void raw_write_mair(uint64_t mair, uint32_t el); uint64_t raw_read_mpidr_el1(void); uint32_t raw_read_rmr_el1(void); void raw_write_rmr_el1(uint32_t rmr_el1); @@ -234,6 +249,8 @@ uint32_t raw_read_rmr_el3(void); void raw_write_rmr_el3(uint32_t rmr_el3); uint32_t raw_read_rmr_current(void); void raw_write_rmr_current(uint32_t rmr); +uint32_t raw_read_rmr(uint32_t el); +void raw_write_rmr(uint32_t rmr, uint32_t el); uint64_t raw_read_rvbar_el1(void); void raw_write_rvbar_el1(uint64_t rvbar_el1); uint64_t raw_read_rvbar_el2(void); @@ -242,6 +259,8 @@ uint64_t raw_read_rvbar_el3(void); void raw_write_rvbar_el3(uint64_t rvbar_el3); uint64_t raw_read_rvbar_current(void); void raw_write_rvbar_current(uint64_t rvbar); +uint64_t raw_read_rvbar(uint32_t el); +void raw_write_rvbar(uint64_t rvbar, uint32_t el); uint32_t raw_read_scr_el3(void); void raw_write_scr_el3(uint32_t scr_el3); uint32_t raw_read_sctlr_el1(void); @@ -252,6 +271,8 @@ uint32_t raw_read_sctlr_el3(void); void raw_write_sctlr_el3(uint32_t sctlr_el3); uint32_t raw_read_sctlr_current(void); void raw_write_sctlr_current(uint32_t sctlr); +uint32_t raw_read_sctlr(uint32_t el); +void raw_write_sctlr(uint32_t sctlr, uint32_t el); uint64_t raw_read_tcr_el1(void); void raw_write_tcr_el1(uint64_t tcr_el1); uint32_t raw_read_tcr_el2(void); @@ -260,6 +281,8 @@ uint32_t raw_read_tcr_el3(void); void raw_write_tcr_el3(uint32_t tcr_el3); uint64_t raw_read_tcr_current(void); void raw_write_tcr_current(uint64_t tcr); +uint64_t raw_read_tcr(uint32_t el); +void raw_write_tcr(uint64_t tcr, uint32_t el); uint64_t raw_read_ttbr0_el1(void); void raw_write_ttbr0_el1(uint64_t ttbr0_el1); uint64_t raw_read_ttbr0_el2(void); @@ -268,6 +291,8 @@ uint64_t raw_read_ttbr0_el3(void); void raw_write_ttbr0_el3(uint64_t ttbr0_el3); uint64_t raw_read_ttbr0_current(void); void raw_write_ttbr0_current(uint64_t ttbr0); +uint64_t raw_read_ttbr0(uint32_t el); +void raw_write_ttbr0(uint64_t ttbr0, uint32_t el); uint64_t raw_read_ttbr1_el1(void); void raw_write_ttbr1_el1(uint64_t ttbr1_el1); uint64_t raw_read_vbar_el1(void); @@ -278,6 +303,8 @@ uint64_t raw_read_vbar_el3(void); void raw_write_vbar_el3(uint64_t vbar_el3); uint64_t raw_read_vbar_current(void); void raw_write_vbar_current(uint64_t vbar); +uint64_t raw_read_vbar(uint32_t el); +void raw_write_vbar(uint64_t vbar, uint32_t el); /* Cache maintenance system instructions */ void dccisw(uint64_t cisw); @@ -297,10 +324,12 @@ void tlbiall_el1(void); void tlbiall_el2(void); void tlbiall_el3(void); void tlbiall_current(void); +void tlbiall(uint32_t el); void tlbiallis_el1(void); void tlbiallis_el2(void); void tlbiallis_el3(void); void tlbiallis_current(void); +void tlbiallis(uint32_t el); void tlbivaa_el1(uint64_t va); /* Memory barrier */

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New patch to review for coreboot: d20bf12 libpayload arm64: don't modify cbtable entries
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8797 -gerrit commit d20bf12bb93519f46cca415988d210cab94b0c80 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 18 11:55:33 2014 -0600 libpayload arm64: don't modify cbtable entries The framebuffer structure lives in the coreboot tables. Those tables have a checksum calculation applied over all the entries. Therefore, one shouldnot be modifying fields within the coreboot table entries because the calculated checksum would be wrong. BRANCH=none BUG=chrome-os-partner:31936 TEST=On ryu, confirmed dev screen still works as well as cbmem utility once booted. Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16 Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230471 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/arch/arm64/mmu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 41fb10b..86d9fc5 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -675,6 +675,7 @@ static void mmu_extract_ranges(struct memrange *cb_ranges, static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) { struct mmu_memrange *fb_range; + static struct cb_framebuffer modified_fb; struct cb_framebuffer *framebuffer = lib_sysinfo.framebuffer; uint32_t fb_size; @@ -695,8 +696,16 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) if (fb_range == NULL) mmu_error(); - /* Set framebuffer address */ - framebuffer->physical_address = fb_range->base; + /* + * Set framebuffer address. However, one needs to use a freshly + * allocated framebuffer structure because the one in the coreboot + * table is part of a checksum calculation. Therefore, one cannot + * modify a field without recomputing the necessary checksum + * calcuation. + */ + modified_fb = *framebuffer; + modified_fb.physical_address = fb_range->base; + lib_sysinfo.framebuffer = &modified_fb; } /*

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New patch to review for coreboot: 021f48b libpayload arm64: Allocate framebuffer range
by Patrick Georgi 20 Mar '15

20 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8796 -gerrit commit 021f48bc02a3b89547cd7f2ee1aead7c2a7e09a3 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Thu Oct 9 18:42:00 2014 -0700 libpayload arm64: Allocate framebuffer range Allocate noncacheable memory for frame buffer and save base address to sys_libinfo. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I19a8079616376dc7c1a8ecdbd7499c2553b8c6c3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cebb5650167264902548339bb1a2b428f3b7f4ed Original-Change-Id: I7bfbfefb92001632ce3d572a50e46188795c4ab8 Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226404 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm64/mmu.c | 49 ++++++++++++++++++++++++++++ payloads/libpayload/include/arm64/arch/mmu.h | 2 ++ 2 files changed, 51 insertions(+) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index b69dac2..41fb10b 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -616,6 +616,25 @@ static struct mmu_memrange *mmu_add_dma_range(struct mmu_ranges *mmu_ranges) return mmu_alloc_range(mmu_ranges, &prop); } +static struct mmu_memrange *_mmu_add_fb_range( + uint32_t size, + struct mmu_ranges *mmu_ranges) +{ + struct mmu_new_range_prop prop; + + prop.type = TYPE_DMA_MEM; + + /* make sure to allocate a size of multiple of GRANULE_SIZE */ + size = ALIGN_UP(size, GRANULE_SIZE); + prop.size = size; + prop.lim_excl = MIN_64_BIT_ADDR; + prop.align = MB_SIZE; + prop.is_valid_range = NULL; + prop.src_type = TYPE_NORMAL_MEM; + + return mmu_alloc_range(mmu_ranges, &prop); +} + /* * Func: mmu_extract_ranges * Desc: Assumption is that coreboot tables have memranges in sorted @@ -653,6 +672,33 @@ static void mmu_extract_ranges(struct memrange *cb_ranges, } } +static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) +{ + struct mmu_memrange *fb_range; + struct cb_framebuffer *framebuffer = lib_sysinfo.framebuffer; + uint32_t fb_size; + + /* + * Check whether framebuffer is needed + * or framebuffer address has been set already + */ + if (framebuffer == NULL) + return; + if (framebuffer->physical_address) + return; + fb_size = framebuffer->bytes_per_line * framebuffer->y_resolution; + if (!fb_size) + return; + + /* Allocate framebuffer */ + fb_range = _mmu_add_fb_range(fb_size, mmu_ranges); + if (fb_range == NULL) + mmu_error(); + + /* Set framebuffer address */ + framebuffer->physical_address = fb_range->base; +} + /* * Func: mmu_init_ranges * Desc: Initialize mmu_memranges based on the memranges obtained from coreboot @@ -673,6 +719,9 @@ struct mmu_memrange *mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges, /* Get a range for dma */ dma_range = mmu_add_dma_range(mmu_ranges); + /* Get a range for framebuffer */ + mmu_add_fb_range(mmu_ranges); + if (dma_range == NULL) mmu_error(); diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h index fdb1cc8..abd29f5 100644 --- a/payloads/libpayload/include/arm64/arch/mmu.h +++ b/payloads/libpayload/include/arm64/arch/mmu.h @@ -181,6 +181,8 @@ extern char _start[], _end[]; #define DMA_DEFAULT_SIZE (0x20 * GRANULE_SIZE) #define TTB_DEFAULT_SIZE 0x100000 +#define MB_SIZE (1UL << 20) + /* Initialize the MMU TTB tables using the mmu_ranges */ uint64_t mmu_init(struct mmu_ranges *mmu_ranges);

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coreboot-gerrit March 2015