coreboot-gerrit February 2015

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Patch set updated for coreboot: 72050d5 AMD K8 fam10: Add ht_route_link()
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8556 -gerrit commit 72050d556757f7c7889ad7d8f17418083d2e1a96 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 12:05:33 2015 +0200 AMD K8 fam10: Add ht_route_link() Change-Id: I41aeb80121f120641b65759c8502150ce89caa30 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 29 +++++++++++----------- src/northbridge/amd/amdk8/northbridge.c | 40 ++++++++++++++++-------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 49a28de..709bd0e 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -155,6 +155,20 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link) return !!(link_type & NonCoherent); } +static void ht_route_link(struct bus *link) +{ + u32 busses; + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xffff00ff; + busses |= ((u32)(link->secondary) << 8); + pci_write_config32(link->dev, link->cap + 0x14, busses); +} + static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, u32 max) { @@ -166,7 +180,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - u32 busses; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 u32 busn = max&0xff; #endif @@ -215,19 +228,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool link->secondary = min_bus; link->subordinate = max_bus; - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xffff00ff; - busses |= ((u32)(link->secondary) << 8); - pci_write_config32(dev, link->cap + 0x14, busses); - + ht_route_link(link); /* set the config map space */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a17aa65..086a008 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -96,6 +96,22 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link) return !!(link_type & NonCoherent); } +static void ht_route_link(struct bus *link) +{ + u32 busses; + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xff000000; + busses |= (((unsigned int)(link->dev->bus->secondary) << 0) | + ((unsigned int)(link->secondary) << 8) | + ((unsigned int)(link->subordinate) << 16)); + pci_write_config32(link->dev, link->cap + 0x14, busses); +} + static u32 amdk8_nodeid(device_t dev) { return (dev->path.pci.devfn >> 3) - 0x18; @@ -105,7 +121,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 max) { int i; - u32 busses, config_busses; + u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; @@ -172,22 +188,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ link->secondary = min_bus; link->subordinate = max_bus; - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - config_busses = f1_read_config32(config_reg); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xff000000; - busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(link->secondary) << 8) | - ((unsigned int)(link->subordinate) << 16)); - pci_write_config32(dev, link->cap + 0x14, busses); + ht_route_link(link); + config_busses = f1_read_config32(config_reg); config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ @@ -215,9 +218,8 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * subordinate bus number to it's real value */ link->subordinate = max; - busses = (busses & 0xff00ffff) | - ((unsigned int) (link->subordinate) << 16); - pci_write_config32(dev, link->cap + 0x14, busses); + + ht_route_link(link); config_busses = (config_busses & 0x00ffffff) | (link->subordinate << 24);

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Patch set updated for coreboot: afae9e6 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8352 -gerrit commit afae9e6b2bc208e16c4ab8d43f89da0dfd661626 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:24:59 2015 +0200 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0 Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 36 +++++++++++++----------------- src/northbridge/amd/amdk8/northbridge.c | 28 +++++++++-------------- 2 files changed, 26 insertions(+), 38 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 34d96de..dad4d11 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -197,29 +197,25 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if (is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. - else { + + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { + min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + // second chain will be on 0x40, third 0x80, forth 0xc0 + // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 + // >4 will use more segments, + // We can have 16 segmment and every segment have 256 bus, + // For that case need the kernel support mmio pci config. + /* One node can have 8 link and segn is the same. */ min_bus = (((max & 0xff) >> 3) + 1) << 3; + max = min_bus; } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif -#else - min_bus = ++max; -#endif link->secondary = min_bus; link->subordinate = 0xfc; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5c67744..6c7bfda 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -162,26 +162,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if(is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + min_bus = (max & ~0x3f) + 0x40; + max = min_bus; } - #endif -#else - min_bus = ++max; -#endif link->secondary = min_bus; link->subordinate = 0xff;

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Patch set updated for coreboot: faa2c71 AMD K8: Refactor calls for HT configuration
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8559 -gerrit commit faa2c71e6dbf666300a68f561ef8f50d8ec32c57 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 11:19:01 2015 +0200 AMD K8: Refactor calls for HT configuration Change-Id: I24ca1dce025e00064f9209affa27586292c7650e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/northbridge.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 3c9feea..d47669f 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -213,19 +213,16 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ (link->subordinate << 24); f1_write_config32(config_reg, config_busses); - { - // use config_reg and ht_unitid_base to update hcdn_reg - int index; - u32 temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } - sysconf.hcdn_reg[index] = temp; + // use config_reg and ht_unitid_base to update hcdn_reg + link->hcdn_reg = 0; + for (i = 0; i < 4; i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); - } - return max; + int index = (config_reg-0xe0) >> 2; + sysconf.hcdn_reg[index] = link->hcdn_reg; + + return max; } static unsigned amdk8_scan_chains(device_t dev, unsigned max)

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Patch set updated for coreboot: 0c8312e AMD fam10: Refactor calls for HT configuration
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8558 -gerrit commit 0c8312ea27617bb17a460f4d86a02255e6179e1c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 11:19:01 2015 +0200 AMD fam10: Refactor calls for HT configuration Change-Id: Ic8fbafdfadbc4ef0896d93e61c8a54ce69297e07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/ht_config.c | 71 +++++++++++++++++------------- src/northbridge/amd/amdfam10/ht_config.h | 15 +++---- src/northbridge/amd/amdfam10/northbridge.c | 39 +++++++--------- 3 files changed, 61 insertions(+), 64 deletions(-) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index efb3148..57b2d0a 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -47,54 +47,51 @@ struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } - -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes) +void set_config_map_reg(struct bus *link) { u32 tempreg; u32 i; + u32 ht_c_index = get_ht_c_index(link); + u32 linkn = link->link_num & 0x0f; + u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; + u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; + u32 nodeid = amdfam10_nodeid(link->dev); - busn_min>>=segbit; - busn_max>>=segbit; + tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; + tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } } -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes) +void clear_config_map_reg(struct bus *link) { u32 i; + u32 ht_c_index = get_ht_c_index(link); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } } -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) +static u32 ht_c_key(struct bus *link) { - u32 tempreg; - u32 ht_c_index = 0; + u32 nodeid = amdfam10_nodeid(link->dev); + u32 linkn = link->link_num & 0x0f; + u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; + return val; +} -#if 0 - tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); +static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) +{ + u32 ht_c_index = 0; - for (ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); - if (((reg & 0xffff) == 0x0000)) { /*found free*/ - break; - } - } -#endif - tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { + if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } } @@ -108,14 +105,26 @@ u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) return -1; } -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo) +u32 get_ht_c_index(struct bus *link) { - u32 val; - val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same + u32 val = ht_c_key(link); + return get_ht_c_index_by_key(val, &sysconf); +} + +void store_ht_c_conf_bus(struct bus *link) +{ + u32 val = ht_c_key(link); + u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); + + u32 segn = (link->subordinate >> 8) & 0x0f; + u32 busn_min = link->secondary & 0xff; + u32 busn_max = link->subordinate & 0xff; + + val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); + sysconf.ht_c_conf_bus[ht_c_index] = val; + sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; + sysconf.ht_c_num++; } u32 get_io_addr_index(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index 54356c1..c2d6c4c 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -20,6 +20,7 @@ typedef struct amdfam10_sysconf_t sys_info_conf_t; /* FIXME */ +u32 amdfam10_nodeid(device_t dev); extern device_t __f1_dev[]; struct dram_base_mask_t { @@ -29,17 +30,11 @@ struct dram_base_mask_t { struct dram_base_mask_t get_dram_base_mask(u32 nodeid); -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes); -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes); +u32 get_ht_c_index(struct bus *link); +void store_ht_c_conf_bus(struct bus *link); -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo); - -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo); +void set_config_map_reg(struct bus *link); +void clear_config_map_reg(struct bus *link); void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index dfa1316..1c1dcf4 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -111,7 +111,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +u32 amdfam10_nodeid(device_t dev) { #if NODE_NUMS == 64 unsigned busn; @@ -176,7 +176,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; - u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; @@ -188,9 +187,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link->link_num, &sysconf); - - if(ht_c_index>=4) return max; + if (get_ht_c_index(link) >= 4) + return max; /* Set up the primary, secondary and subordinate bus numbers. * We have no idea how many busses are behind this bridge yet, @@ -218,8 +216,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool ht_route_link(link); /* set the config map space */ - - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(link); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -239,26 +236,22 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link->link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); - } - link->subordinate = max; - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); - sysconf.ht_c_num++; - { - // use ht_unitid_base to update hcdn_reg - u32 temp = 0; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } + if (0) { + /* Clear the extend reg. */ + clear_config_map_reg(link); + } - sysconf.hcdn_reg[ht_c_index] = temp; + set_config_map_reg(link); - } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); - return max; + /* Use ht_unitid_base to update hcdn_reg. */ + link->hcdn_reg = 0; + for (i = 0; i < 4;i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + store_ht_c_conf_bus(link); + return max; } static unsigned amdfam10_scan_chains(device_t dev, unsigned max)

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Patch set updated for coreboot: cf8aeed AMD K8 fam10: Eliminate local variable min_bus
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8364 -gerrit commit cf8aeed0db2d8275f433e53134c902952634c9a6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 08:12:20 2015 +0200 AMD K8 fam10: Eliminate local variable min_bus Some cases of max==0xff wrapping around the 8-bit link->secondary register remain to be solved. Change-Id: I01e2ab6b2f23a03dbac49207ab584eccd1ca9b1f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 19 +++++++------------ src/northbridge/amd/amdk8/northbridge.c | 16 +++++++--------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index dad4d11..dfa1316 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -178,7 +178,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 min_bus; u32 max_devfn; /* Check for connected link. */ @@ -199,25 +198,21 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool */ if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - min_bus = ++max; + max++; } else if (is_sblink) { - // first chain will on bus 0 - min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - min_bus = ++max; + max++; } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, // We can have 16 segmment and every segment have 256 bus, // For that case need the kernel support mmio pci config. /* One node can have 8 link and segn is the same. */ - min_bus = (((max & 0xff) >> 3) + 1) << 3; - max = min_bus; + max++; + max = ALIGN_UP(max, 8); } - link->secondary = min_bus; + link->secondary = max; link->subordinate = 0xfc; ht_route_link(link); @@ -234,7 +229,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool } //if ext conf is enabled, only need use 0x1f - if (min_bus == 0) + if (link->secondary == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 6c7bfda..3c9feea 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -124,7 +124,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 min_bus; u32 max_devfn; link->cap = 0x80 + (link->link_num * 0x20); @@ -163,19 +162,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - min_bus = ++max; + max++; } else if (is_sblink) { - // first chain will on bus 0 - min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - min_bus = ++max; + max++; } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - min_bus = (max & ~0x3f) + 0x40; - max = min_bus; + max++; + max = ALIGN_UP(max, 0x40); } - link->secondary = min_bus; + link->secondary = max; link->subordinate = 0xff; ht_route_link(link); @@ -197,7 +195,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ ht_unitid_base[i] = 0x20; } - if (min_bus == 0) + if (link->secondary == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7;

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Patch set updated for coreboot: 919ff94 AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8365 -gerrit commit 919ff9436c84184ef9cd1b3031b11811b5e6402c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 13:36:54 2015 +0200 AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0 Change-Id: I452a93af452073eeac4e6cb9bbc232dc59e911c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 14 +++----------- src/northbridge/amd/amdk8/northbridge.c | 12 ++++-------- 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1c1dcf4..8e6fe45 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -195,20 +195,12 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) max++; - } else if (is_sblink) { - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - max++; - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // We can have 16 segmment and every segment have 256 bus, - // For that case need the kernel support mmio pci config. - - /* One node can have 8 link and segn is the same. */ - max++; + /* One node can have 8 link and segn is the same. */ + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) max = ALIGN_UP(max, 8); - } link->secondary = max; link->subordinate = 0xfc; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d47669f..2adbccf 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -161,17 +161,13 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ - if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - max++; - } else if (is_sblink) { - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - max++; - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) max++; + + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) max = ALIGN_UP(max, 0x40); - } link->secondary = max; link->subordinate = 0xff;

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Patch set updated for coreboot: 5c8b74b AMD K8 fam10: Eliminate local variables busn and max_bus
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8362 -gerrit commit 5c8b74bc24c0cb0c71bc91e53ff41552f4f34028 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:22:55 2015 +0200 AMD K8 fam10: Eliminate local variables busn and max_bus Change-Id: I297de09dcf93511acece4441593ef958a390fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 10 +++------- src/northbridge/amd/amdk8/northbridge.c | 4 +--- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 709bd0e..34d96de 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -178,11 +178,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - u32 busn = max&0xff; -#endif u32 max_devfn; /* Check for connected link. */ @@ -211,7 +207,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. else { - min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same + /* One node can have 8 link and segn is the same. */ + min_bus = (((max & 0xff) >> 3) + 1) << 3; } max = min_bus; #else @@ -223,10 +220,9 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #else min_bus = ++max; #endif - max_bus = 0xfc; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = 0xfc; ht_route_link(link); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 086a008..5c67744 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -124,7 +124,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; u32 max_devfn; @@ -183,10 +182,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ #else min_bus = ++max; #endif - max_bus = 0xff; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = 0xff; ht_route_link(link);

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New patch to review for coreboot: 2e6358f AMD K8: Refactor calls for HT configuration
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8559 -gerrit commit 2e6358f8883f1ef4f62026bb4e6665090cbf4990 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 11:19:01 2015 +0200 AMD K8: Refactor calls for HT configuration Change-Id: I24ca1dce025e00064f9209affa27586292c7650e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/northbridge.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 3696f5d..208a725 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -213,19 +213,16 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ (link->subordinate << 24); f1_write_config32(config_reg, config_busses); - { - // use config_reg and ht_unitid_base to update hcdn_reg - int index; - u32 temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } - sysconf.hcdn_reg[index] = temp; + // use config_reg and ht_unitid_base to update hcdn_reg + link->hcdn_reg = 0; + for (i = 0; i < 4; i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); - } - return max; + int index = (config_reg-0xe0) >> 2; + sysconf.hcdn_reg[index] = link->hcdn_reg; + + return max; } static unsigned amdk8_scan_chains(device_t dev, unsigned max)

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New patch to review for coreboot: 7d85121 AMD fam10: Refactor calls for HT configuration
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8558 -gerrit commit 7d8512135555b9ec82fd890b68158e7db305ae6f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 11:19:01 2015 +0200 AMD fam10: Refactor calls for HT configuration Change-Id: Ic8fbafdfadbc4ef0896d93e61c8a54ce69297e07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/ht_config.c | 71 +++++++++++++++++------------- src/northbridge/amd/amdfam10/ht_config.h | 15 +++---- src/northbridge/amd/amdfam10/northbridge.c | 39 +++++++--------- 3 files changed, 61 insertions(+), 64 deletions(-) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index efb3148..57b2d0a 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -47,54 +47,51 @@ struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } - -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes) +void set_config_map_reg(struct bus *link) { u32 tempreg; u32 i; + u32 ht_c_index = get_ht_c_index(link); + u32 linkn = link->link_num & 0x0f; + u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; + u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; + u32 nodeid = amdfam10_nodeid(link->dev); - busn_min>>=segbit; - busn_max>>=segbit; + tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; + tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } } -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes) +void clear_config_map_reg(struct bus *link) { u32 i; + u32 ht_c_index = get_ht_c_index(link); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } } -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) +static u32 ht_c_key(struct bus *link) { - u32 tempreg; - u32 ht_c_index = 0; + u32 nodeid = amdfam10_nodeid(link->dev); + u32 linkn = link->link_num & 0x0f; + u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; + return val; +} -#if 0 - tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); +static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) +{ + u32 ht_c_index = 0; - for (ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); - if (((reg & 0xffff) == 0x0000)) { /*found free*/ - break; - } - } -#endif - tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { + if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } } @@ -108,14 +105,26 @@ u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) return -1; } -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo) +u32 get_ht_c_index(struct bus *link) { - u32 val; - val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same + u32 val = ht_c_key(link); + return get_ht_c_index_by_key(val, &sysconf); +} + +void store_ht_c_conf_bus(struct bus *link) +{ + u32 val = ht_c_key(link); + u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); + + u32 segn = (link->subordinate >> 8) & 0x0f; + u32 busn_min = link->secondary & 0xff; + u32 busn_max = link->subordinate & 0xff; + + val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); + sysconf.ht_c_conf_bus[ht_c_index] = val; + sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; + sysconf.ht_c_num++; } u32 get_io_addr_index(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index 54356c1..c2d6c4c 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -20,6 +20,7 @@ typedef struct amdfam10_sysconf_t sys_info_conf_t; /* FIXME */ +u32 amdfam10_nodeid(device_t dev); extern device_t __f1_dev[]; struct dram_base_mask_t { @@ -29,17 +30,11 @@ struct dram_base_mask_t { struct dram_base_mask_t get_dram_base_mask(u32 nodeid); -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes); -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes); +u32 get_ht_c_index(struct bus *link); +void store_ht_c_conf_bus(struct bus *link); -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo); - -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo); +void set_config_map_reg(struct bus *link); +void clear_config_map_reg(struct bus *link); void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index dfa1316..1c1dcf4 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -111,7 +111,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +u32 amdfam10_nodeid(device_t dev) { #if NODE_NUMS == 64 unsigned busn; @@ -176,7 +176,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; - u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; @@ -188,9 +187,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link->link_num, &sysconf); - - if(ht_c_index>=4) return max; + if (get_ht_c_index(link) >= 4) + return max; /* Set up the primary, secondary and subordinate bus numbers. * We have no idea how many busses are behind this bridge yet, @@ -218,8 +216,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool ht_route_link(link); /* set the config map space */ - - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(link); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -239,26 +236,22 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link->link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); - } - link->subordinate = max; - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); - sysconf.ht_c_num++; - { - // use ht_unitid_base to update hcdn_reg - u32 temp = 0; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } + if (0) { + /* Clear the extend reg. */ + clear_config_map_reg(link); + } - sysconf.hcdn_reg[ht_c_index] = temp; + set_config_map_reg(link); - } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); - return max; + /* Use ht_unitid_base to update hcdn_reg. */ + link->hcdn_reg = 0; + for (i = 0; i < 4;i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + store_ht_c_conf_bus(link); + return max; } static unsigned amdfam10_scan_chains(device_t dev, unsigned max)

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New patch to review for coreboot: a67944d devicetree: Add fields for HyperTransport scans
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8557 -gerrit commit a67944d5a3ce2e67976fec367024cf983e518494 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 11:38:49 2015 +0200 devicetree: Add fields for HyperTransport scans Change-Id: I3b00e5e4e45089fbd7d0d6243d5e441bd8929c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/device/device.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/device/device.h b/src/include/device/device.h index 30226bf..43a6796 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -85,6 +85,8 @@ struct bus { uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ + uint32_t hcdn_reg; /* For HyperTransport link */ + unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; };

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coreboot-gerrit February 2015