Patch set updated for coreboot: afae9e6 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8352

-gerrit

commit afae9e6b2bc208e16c4ab8d43f89da0dfd661626
Author: Kyösti Mälkki 
Date:   Sun Feb 22 09:24:59 2015 +0200

AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0

Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5
    Signed-off-by: Kyösti Mälkki 
---
 src/northbridge/amd/amdfam10/northbridge.c | 36 +++++++++++++-----------------
 src/northbridge/amd/amdk8/northbridge.c    | 28 +++++++++--------------
 2 files changed, 26 insertions(+), 38 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 34d96de..dad4d11 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -197,29 +197,25 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
    	 * We have no idea how many busses are behind this bridge yet,
    	 * so we set the subordinate bus number to 0xff for the moment.
    	 */
-#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
-		// first chain will on bus 0
-		if (is_sblink) { // actually max is 0 here
-			min_bus = max;
-		}
-	#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
-		// second chain will be on 0x40, third 0x80, forth 0xc0
-		// i would refined that to  2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0
-		//			    >4 will use	 more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config.
-		else {
+
+		if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) {
+			min_bus = ++max;
+		} else if (is_sblink) {
+			// first chain will on bus 0
+			min_bus = max;  /* actually max is 0 here */
+		} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) {
+			min_bus = ++max;
+		} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) {
+			// second chain will be on 0x40, third 0x80, forth 0xc0
+			// i would refined that to  2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0
+			//   >4 will use more segments,
+			// We can have 16 segmment and every segment have 256 bus,
+			// For that case need the kernel support mmio pci config.
+
    		/* One node can have 8 link and segn is the same. */
    		min_bus = (((max & 0xff) >> 3) + 1) << 3;
+			max = min_bus;
    	}
-		max = min_bus;
-	#else
-		//other ...
-		else {
-			min_bus = ++max;
-		}
-	#endif
-#else
-		min_bus = ++max;
-#endif

link->secondary = min_bus;
    	link->subordinate = 0xfc;
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 5c67744..6c7bfda 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -162,26 +162,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
    	 * We have no idea how many busses are behind this bridge yet,
    	 * so we set the subordinate bus number to 0xff for the moment.
    	 */
-#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
-		// first chain will on bus 0
-		if(is_sblink) { // actually max is 0 here
-			min_bus = max;
-		}
-	#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
-		// second chain will be on 0x40, third 0x80, forth 0xc0
-		else {
-			min_bus = ((max>>6) + 1) * 0x40;
-		}
-		max = min_bus;
-	#else
-		//other ...
-		else {
+		if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) {
+			min_bus = ++max;
+		} else if (is_sblink) {
+			// first chain will on bus 0
+			min_bus = max;  /* actually max is 0 here */
+		} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) {
    		min_bus = ++max;
+		} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) {
+			/* Second chain will be on 0x40, third 0x80, forth 0xc0. */
+			min_bus = (max & ~0x3f) + 0x40;
+			max = min_bus;
    	}
-	#endif
-#else
-		min_bus = ++max;
-#endif

link->secondary = min_bus;
    	link->subordinate = 0xff;