coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

1 participants
509 discussions

Patch set updated for coreboot: 8ae9b7b pcengines/apu1: Fix PCI device 16 interrupts
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8327 -gerrit commit 8ae9b7b9dc82547fc99487c003483a39b20d508d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 14 12:58:53 2015 +0200 pcengines/apu1: Fix PCI device 16 interrupts Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed in PIC mode. The only affected peripheral was the SD card reader. This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz. Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 01a0bd2..1ba0e23 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -63,7 +63,7 @@ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* IMC INT0 - 5 */ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x1F,0x1F,0x0A, + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* IDE, SATA */ [0x40] = 0x0B,0x0B, /* GPPInt0 - 3 */

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Patch set updated for coreboot: 7be1731 pcengines/apu1: Fix 0:15.x PCIe root ports
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8388 -gerrit commit 7be17317e0e632d9ab39e91082ce7c0fdf4f52bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 17 18:08:40 2015 +0200 pcengines/apu1: Fix 0:15.x PCIe root ports Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done to only advertise x1 lane width for PCIe link 0:15.0. Hide functions of PCIe links that have no slots connected. Our PCI infrastructure does not support bridge devices that are set off in devicetree but remain visible in the PCI hardware tree. Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/devicetree.cb | 2 +- src/mainboard/pcengines/apu1/platform_cfg.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 0886bc6..4e977cf 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -83,7 +83,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 15.3 off end # PCIe PortD device pci 16.0 on end # OHCI USB 10-13 device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "0" + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 # end # device pci 18.0 diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 2efe905..6d40663 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -186,7 +186,7 @@ * GPP_CFGMODE_X2110 * GPP_CFGMODE_X1111 */ -#define GPP_CFGMODE GPP_CFGMODE_X4000 +#define GPP_CFGMODE GPP_CFGMODE_X1111 /** * @def NB_SB_GEN2 @@ -207,7 +207,7 @@ * TRUE - ports visible always, even port empty * FALSE - ports invisible if port empty */ -#define SB_GPP_UNHIDE_PORTS TRUE +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG

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Patch set updated for coreboot: 89eeec7 AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration [NOTFORMERGE]
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8389 -gerrit commit 89eeec743ff8b9656c129d436d923edd09326ee0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 7 12:27:27 2015 +0200 AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration [NOTFORMERGE] Now that PCI subsystem properly configures PCI bridges that are marked disabled, fix devicetree entries for the boards that do not implement PCI slots or integrated PCI devices. Change-Id: Icef85af051567a3da0ec429469fb3ecaccb83a48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asrock/e350m1/devicetree.cb | 2 +- src/mainboard/gizmosphere/gizmo/devicetree.cb | 2 +- src/mainboard/pcengines/apu1/devicetree.cb | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 0690664..7f44869 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -94,7 +94,7 @@ chip northbridge/amd/agesa/family14/root_complex device pnp 2e.f off end # GPIO_PP_OD end end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.4 off end # PCIB 0x4384 device pci 14.5 on end # USB 2 device pci 15.0 on end # PCIe PortA device pci 15.1 on end # PCIe PortB: NIC diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 8cd4cd3..baa10b3 100644 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed + device pci 14.4 off end # PCIB 0x4384 device pci 14.5 off end # USB 2 device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 4e977cf..2620d1b 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -74,7 +74,7 @@ chip northbridge/amd/agesa/family14/root_complex device pnp 2e.e off end end end #LPC - device pci 14.4 on end # PCIB 0x4384 + device pci 14.4 off end # PCIB 0x4384 device pci 14.5 off end # OHCI FS/LS USB #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) device pci 15.0 on end # PCIe PortA diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ccb33b9..510bf23 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -400,7 +400,7 @@ static void sb800_enable(device_t dev) * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins * to function as GPIO {GPIO 35:0}. */ - if (!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU1) && dev->enabled) + if (dev->enabled) RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); else RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);

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Patch set updated for coreboot: 032b925 pcengines/apu1: Fix and clean up devicetree
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8328 -gerrit commit 032b925b19a6cf237cea23433745507d503d1571 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 17 18:08:40 2015 +0200 pcengines/apu1: Fix and clean up devicetree Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware. Disable 0:14.1 IDE controller, as it would only be used with SATA ports 4 and 5 that are not populated with connectors in the hardware. Disable 0:14.2 HD audio, as it is not implemented in the hardware Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller are not populated in the hardware. Fix some alignment and whitespace. To my knowledge these changes are not included with SAGE release pcengines.apu_139_osp.tar.gz, but that tarball does not contain either devicetree.cb or a pre-compiled static.c file so I cannot tell for sure. Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/devicetree.cb | 67 ++++++++++++++---------------- src/mainboard/pcengines/apu1/mptable.c | 11 ----- 2 files changed, 32 insertions(+), 46 deletions(-) diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 5f6f9c9..0886bc6 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -26,29 +26,26 @@ chip northbridge/amd/agesa/family14/root_complex device domain 0 on subsystemid 0x1022 0x1510 inherit chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 on end # PCIE P2P bridge - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.1 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.1 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on end # SMBus + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" @@ -76,19 +73,19 @@ chip northbridge/amd/agesa/family14/root_complex device pnp 2e.607 off end device pnp 2e.e off end end - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # OHCI FS/LS USB - #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "0" - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 + end #LPC + device pci 14.4 on end # PCIB 0x4384 + device pci 14.5 off end # OHCI FS/LS USB + #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "0" + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary device pci 18.0 on end diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 4686d62..c0553b4 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -114,17 +114,6 @@ static void *smp_write_config_table(void *v) PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ - /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ - PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ - PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ - PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ - } - /* PCIe PortA */ PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ /* PCIe PortB */

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Patch set updated for coreboot: e05c484 pcengines/apu1: Work around PCI reset issue [NOTFORMERGE]
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8330 -gerrit commit e05c4846aa284add92a7ce3b5218fcb484fe27b1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 28 16:36:28 2015 +0200 pcengines/apu1: Work around PCI reset issue [NOTFORMERGE] This patch is extracted from SAGE release pcengines.apu_139_osp.tar.gz. Change-Id: Ie5653fce2614066f735e497f835c77d09e8b6b22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/reset.h | 6 ++++++ src/southbridge/amd/cimx/sb800/bootblock.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/include/reset.h b/src/include/reset.h index 9430ffe..56f703d 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -10,3 +10,9 @@ void soft_reset(void); void cpu_reset(void); #endif + +#define PCI_RESET_REGISTER 0xcf9 +#define SYS_RST_BIT (1 << 1) +#define RST_CPU_BIT (1 << 2) +#define PCI_COLD_RESET ( SYS_RST_BIT | RST_CPU_BIT ) +#define PCI_WARM_RESET RST_CPU_BIT diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 188ba29..b1119cc 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -18,6 +18,7 @@ */ #include <arch/io.h> +#include <reset.h> static void enable_rom(void) { @@ -111,6 +112,21 @@ static void enable_clocks(void) static void bootblock_southbridge_init(void) { + u32 dword; + device_t dev; + + /* Check the value of index 0x44 of BDF 0:14.3. + * A non-zero value indicates that a improper reset + * occurred and that a hard-reset should be performed. + */ + dev = PCI_DEV(0, 0x14, 0x03); + dword = pci_io_read_config32(dev, 0x44); + if (dword != 0x00000000) { + outb( 0x00, PCI_RESET_REGISTER); + outb( PCI_COLD_RESET, PCI_RESET_REGISTER); + while(1) ; + } + /* Setup the rom access for 2M */ enable_rom(); enable_prefetch();

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Patch merged into coreboot/master: 04a5b48 Use ALIGN_UP instead of manual alignment
by gerrit＠coreboot.org 12 Feb '15

12 Feb '15

the following patch was just integrated into master: commit 04a5b48902fa118ba8113ff9f915f48719a921ec Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Jan 21 17:37:34 2015 +0100 Use ALIGN_UP instead of manual alignment BUG=none BRANCH=none TEST=none Change-Id: I56f357db6d37120772a03a1f7f84ce2a5b5620e9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/241855 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Commit-Queue: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/8396 Tested-by: build bot (Jenkins) See http://review.coreboot.org/8396 for details. -gerrit

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Patch set updated for coreboot: 01a56f4 fsp_baytrail: Add new microcode for Bay Trail M
by Werner Zeh 12 Feb '15

12 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8399 -gerrit commit 01a56f4ea0ff442252dbd211b5b9179e26b7e6bb Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 10:16:12 2015 +0100 fsp_baytrail: Add new microcode for Bay Trail M Add a new microcode for Bay Trail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has been added (I or M/D) which allows to use only the really needed microcode for a given CPU type. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 9 +++++++++ src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 15 ++++++++++----- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 6 +++++- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 639071a..54ce836 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -51,6 +51,15 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT +choice + prompt "Bay Trail CPU type" + default SOC_INTEL_FSP_BAYTRAIL_I +config SOC_INTEL_FSP_BAYTRAIL_I + bool "I" +config SOC_INTEL_FSP_BAYTRAIL_MD + bool "M/D" +endchoice + config BOOTBLOCK_CPU_INIT string default "soc/intel/fsp_baytrail/bootblock/bootblock.c" diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 709ff92..7ac1e7e 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,12 +19,17 @@ unsigned microcode[] = { -/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ -#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 -#include "M0130679901.h" // M0130679: Baytrail I D0 +#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I) + /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ + #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1 + #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3 + #include "M0130679901.h" // M0130679: Bay Trail I D0 +#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */ + #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping +#endif - /* Dummy terminator */ + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec55314..213fc17 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,6 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I) + #define MICROCODE_REGION_LENGTH 0x30000 +#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + #define MICROCODE_REGION_LENGTH 0x10000 +#endif

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Patch set updated for coreboot: 1f29181 AMD cimx/sb800: Move cimx init for ramstage
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8386 -gerrit commit 1f291815cc692c9f55fcf6eeae988a6d5d538dff Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 7 11:20:54 2015 +0200 AMD cimx/sb800: Move cimx init for ramstage This has nothing to do with SATA controller. We only need to fill the table with defaults before we parse devicetree for changes to device configuration. Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb800/cfg.c | 7 ------- src/southbridge/amd/cimx/sb800/cfg.h | 12 ------------ src/southbridge/amd/cimx/sb800/late.c | 13 +++++++++++-- 3 files changed, 11 insertions(+), 21 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index ac6e6ae..c614240 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -132,11 +132,4 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06 sb_config->GecConfig = GEC_CONFIG; - -#ifndef __PRE_RAM__ - /* ramstage cimx config here */ - if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { - sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; - } -#endif //!__PRE_RAM__ } diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h index f6a3ab0..385333f 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.h +++ b/src/southbridge/amd/cimx/sb800/cfg.h @@ -29,16 +29,4 @@ */ void sb800_cimx_config(AMDSBCFG *sb_cfg); -/** - * @brief Entry point of Southbridge CIMx callout - * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) - * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. - * @param[in] config Southbridge configuration structure pointer. - * - */ -u32 sb800_callout_entry(u32 func, u32 data, void* config); - #endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 19d7fb5..9a08121 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -59,7 +59,7 @@ static AMDSBCFG *sb_config = &sb_late_cfg; * @param[in] config Southbridge configuration structure pointer. * */ -u32 sb800_callout_entry(u32 func, u32 data, void* config) +static u32 sb800_callout_entry(u32 func, u32 data, void* config) { u32 ret = 0; printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); @@ -260,6 +260,15 @@ static const struct pci_driver gec_driver __pci_driver = { }; /** + * Fill build time defaults. + */ +static void sb800_init(void *chip_info) +{ + sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; + sb800_cimx_config(sb_config); +} + +/** * South Bridge CIMx ramstage entry point wrapper. */ void sb_Before_Pci_Init(void) @@ -346,7 +355,6 @@ static void sb800_enable(device_t dev) abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ break; } - sb800_cimx_config(sb_config); if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; @@ -477,5 +485,6 @@ static void sb800_enable(device_t dev) struct chip_operations southbridge_amd_cimx_sb800_ops = { CHIP_NAME("ATI SB800") + .init = sb800_init, .enable_dev = sb800_enable, };

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Patch set updated for coreboot: 73712aa AMD cimx/sb800: Initially enable all GPP ports
by Kyösti Mälkki 12 Feb '15

12 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8387 -gerrit commit 73712aac5125775706609085c86cac6d6a14e3c4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 7 17:38:45 2015 +0200 AMD cimx/sb800: Initially enable all GPP ports PCIe root ports on devices 0:15.0 to 0:15.3 should at first all appear visible in hardware. The real configuration will be done by vendorcode once we call sb_Before_Pci_Init(). Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb800/late.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 9a08121..510bf23 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -266,6 +266,8 @@ static void sb800_init(void *chip_info) { sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; sb800_cimx_config(sb_config); + + abcfg_reg(0xc0, 0x01FF, 0x0F4); } /** @@ -339,23 +341,6 @@ static void sb800_enable(device_t dev) switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ - /* the first sb800 device */ - switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ - case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ - break; - case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ - break; - case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ - break; - case GPP_CFGMODE_X4000: - default: - abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ - break; - } - if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide)

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Patch merged into coreboot/master: f129756 lint: exclude *.hex files from whitespace checking
by gerrit＠coreboot.org 12 Feb '15

12 Feb '15

the following patch was just integrated into master: commit f129756ac95bf7accd1e840bea882f1b6edac8af Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 14:34:17 2015 +0100 lint: exclude *.hex files from whitespace checking If one needs raw binary files, .bin extension cannot be used due to settings in .gitignore. This patch allows to use .hex files. To avoid lint checks on these files, exclude the .hex extension from the test. Change-Id: I4b503229d63694c48cce12ca8cd33ea58172af01 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/8403 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8403 for details. -gerrit

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coreboot-gerrit February 2015