coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 84fd0ec cbfstool: Add the MIPS architecture
by Marc Jones 23 Feb '15

23 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8519 -gerrit commit 84fd0ecef2d6a5da131018f1fbd8c2abf8b9b40f Author: Paul Burton <paul.burton(a)imgtec.com> Date: Fri Jun 13 23:56:45 2014 +0100 cbfstool: Add the MIPS architecture Specify a CBFS architecture value for MIPS & allow cbfstool to make use of it. Original-Change-Id: I604d61004596b65c9903d444e030241f712202bd Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207971 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 7c4df61715df3767673841789d02fe5d1bd1d4a0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib30524f5e7e8c7891cb69fc8ed8f6a7e44ac3325 --- util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfstool.c | 2 +- util/cbfstool/common.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 9af801c..6aa4060 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -54,6 +54,7 @@ struct cbfs_header { #define CBFS_ARCHITECTURE_ARM 0x00000010 #define CBFS_ARCHITECTURE_AARCH64 0x0000aa64 #define CBFS_ARCHITECTURE_RISCV 0xc001d0de +#define CBFS_ARCHITECTURE_MIPS 0x00000100 #define CBFS_FILE_MAGIC "LARCHIVE" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 4628499..41df157 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -590,7 +590,7 @@ static void usage(char *name) "Updates the FIT table with microcode entries\n" "\n" "ARCHes:\n" - " arm64, arm, x86\n" + " arm64, arm, mips, x86\n" "TYPEs:\n", name, name ); print_supported_filetypes(); diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index d990ddd..bd9cdc0 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -132,6 +132,7 @@ static struct { } arch_names[] = { { CBFS_ARCHITECTURE_AARCH64, "arm64" }, { CBFS_ARCHITECTURE_ARM, "arm" }, + { CBFS_ARCHITECTURE_MIPS, "mips" }, { CBFS_ARCHITECTURE_RISCV, "riscv" }, { CBFS_ARCHITECTURE_X86, "x86" }, { CBFS_ARCHITECTURE_UNKNOWN, "unknown" }

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New patch to review for coreboot: b52a9ef build: mipsel cross compiler support
by Marc Jones 23 Feb '15

23 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8518 -gerrit commit b52a9ef952a4d37eb8c38ed5bb995bff2dcdc2dd Author: Paul Burton <paul.burton(a)imgtec.com> Date: Tue May 27 15:18:42 2014 +0100 build: mipsel cross compiler support This patch introduces support for building a MIPS cross compiler targetting little endian machines by default. Original-Change-Id: I116f6f431cdf80f5f5f58d2743357a9f70a7347d Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207970 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit d6c9603c41b3d11400cee7b5b409203af0632aa2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I543cd2276d2f63ed2036a1c1259c9a07cb8a4ba8 --- toolchain.inc | 3 +++ util/crossgcc/Makefile | 2 ++ util/xcompile/xcompile | 10 +++++++++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index f8c7ea4..51f5410 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -58,11 +58,14 @@ ARCHDIR-x86_32 := x86 ARCHDIR-arm := arm ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv +ARCHDIR-mipsel := mips CFLAGS_arm := -mno-unaligned-access -ffunction-sections -fdata-sections CFLAGS_arm64 := -ffunction-sections -fdata-sections +CFLAGS_mipsel := -mips32r2 -G 0 + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \ diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 4aa6bdc..c429e03 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -8,6 +8,7 @@ build-armv7a: build-aarch64: bash ./buildgcc -G -p aarch64-elf + bash ./buildgcc -G -p mipsel-elf .PHONY: build-i386-without-gdb build-i386-without-gdb: @@ -20,6 +21,7 @@ build-armv7a-without-gdb: .PHONY: build-aarch64-without-gdb build-aarch64-without-gdb: bash ./buildgcc -p aarch64-elf + bash ./buildgcc -p mipsel-elf clean: rm -rf xgcc diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ea2eb47..29cad28 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -168,7 +168,7 @@ EOF } # Architecture definition -SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv" +SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv mipsel" arch_config_arm() { TARCH="arm" @@ -204,6 +204,14 @@ arch_config_x86() { TABI="elf" } +arch_config_mipsel() { + TARCH="mipsel" + TBFDARCH="littlemips" + TCLIST="mipsel" + TWIDTH="32" + TABI="elf" +} + test_architecture() { architecture=$1

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New patch to review for coreboot: 103dbbb tegra132: Enable bootblock support in tegra132 including UART support
by Marc Jones 23 Feb '15

23 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8517 -gerrit commit 103dbbb9059cda440d8f54e851677eeaae9df6a1 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 9 13:20:04 2014 -0700 tegra132: Enable bootblock support in tegra132 including UART support BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203143 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3) This cherry-pick was modified to match the tegra124 uart.c, which uses the idx and base address calculations instead of Kconfig settings. Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/nvidia/tegra132/Kconfig | 32 ++ src/soc/nvidia/tegra132/Kconfig.orig | 103 +++++ src/soc/nvidia/tegra132/Makefile.inc | 16 + src/soc/nvidia/tegra132/Makefile.inc.orig | 68 +++ src/soc/nvidia/tegra132/bootblock.c | 59 +++ src/soc/nvidia/tegra132/bootblock_asm.S | 89 ++++ src/soc/nvidia/tegra132/clk_rst.h | 551 +++++++++++++++++++++++ src/soc/nvidia/tegra132/clock.c | 662 ++++++++++++++++++++++++++++ src/soc/nvidia/tegra132/flow.h | 79 ++++ src/soc/nvidia/tegra132/include/soc/clock.h | 43 +- src/soc/nvidia/tegra132/maincpu.S | 55 +++ src/soc/nvidia/tegra132/maincpu.h | 29 ++ src/soc/nvidia/tegra132/pinmux.h | 260 +++++++++++ src/soc/nvidia/tegra132/pmc.h | 389 ++++++++++++++++ src/soc/nvidia/tegra132/power.h | 29 ++ src/soc/nvidia/tegra132/sysctr.h | 55 +++ src/soc/nvidia/tegra132/uart.c | 148 +++++++ 17 files changed, 2659 insertions(+), 8 deletions(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index d90b8aa..23f7c6e 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -7,9 +7,21 @@ config SOC_NVIDIA_TEGRA132 select ARCH_RAMSTAGE_ARMV8_64 select ARM_LPAE select DYNAMIC_CBMEM + select BOOTBLOCK_CONSOLE + select HAVE_UART_SPECIAL + select HAVE_UART_MEMORY_MAPPED + select ARM_BOOTBLOCK_CUSTOM if SOC_NVIDIA_TEGRA132 +config BOOTBLOCK_CPU_INIT + string + default "soc/nvidia/tegra132/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + config BOOTBLOCK_ROM_OFFSET hex default 0x0 @@ -22,4 +34,24 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x40080 +config BOOTBLOCK_BASE + hex + default 0x40020000 + +config ROMSTAGE_BASE + hex + default 0x4002c000 + +config RAMSTAGE_BASE + hex + default 0x80200000 + +config STACK_TOP + hex + default 0x40020000 + +config STACK_BOTTOM + hex + default 0x4001c000 + endif diff --git a/src/soc/nvidia/tegra132/Kconfig.orig b/src/soc/nvidia/tegra132/Kconfig.orig new file mode 100644 index 0000000..437a36f --- /dev/null +++ b/src/soc/nvidia/tegra132/Kconfig.orig @@ -0,0 +1,103 @@ +config SOC_NVIDIA_TEGRA132 + bool + default n + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_VERSTAGE_ARMV4 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM_LPAE +<<<<<<< HEAD + select DYNAMIC_CBMEM +======= + select BOOTBLOCK_CONSOLE + select HAVE_UART_SPECIAL + select HAVE_UART_MEMORY_MAPPED + select ARM_BOOTBLOCK_CUSTOM +>>>>>>> a1037f2... coreboot tegra132: Enable bootblock support in tegra132 including UART support + +if SOC_NVIDIA_TEGRA132 + +config BOOTBLOCK_CPU_INIT + string + default "soc/nvidia/tegra132/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x40000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x40080 + +config BOOTBLOCK_BASE + hex + default 0x40020000 + +config ROMSTAGE_BASE + hex + default 0x4002c000 + +config RAMSTAGE_BASE + hex + default 0x80200000 + +config STACK_TOP + hex + default 0x40020000 + +config STACK_BOTTOM + hex + default 0x4001c000 + +choice CONSOLE_SERIAL_TEGRA132_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UARTA + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_UARTA + bool "UARTA" + help + Serial console on UART A. + +config CONSOLE_SERIAL_UARTB + bool "UARTB" + help + Serial console on UART B. + +config CONSOLE_SERIAL_UARTC + bool "UARTC" + help + Serial console on UART C. + +config CONSOLE_SERIAL_UARTD + bool "UARTD" + help + Serial console on UART D. + +config CONSOLE_SERIAL_UARTE + bool "UARTE" + help + Serial console on UART E. + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x70006000 if CONSOLE_SERIAL_UARTA + default 0x70006040 if CONSOLE_SERIAL_UARTB + default 0x70006200 if CONSOLE_SERIAL_UARTC + default 0x70006300 if CONSOLE_SERIAL_UARTD + default 0x70006400 if CONSOLE_SERIAL_UARTE + help + Map the UART names to the respective MMIO addres. + +endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index b038339..10479b0 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -1,13 +1,29 @@ +bootblock-y += bootblock.c +bootblock-y += bootblock_asm.S bootblock-y += cbfs.c bootblock-y += timer.c +bootblock-y += clock.c +bootblock-y += ../tegra/gpio.c +bootblock-y += ../tegra/pingroup.c +bootblock-y += ../tegra/pinmux.c +bootblock-y += ../tegra/apbmisc.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c +endif romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += timer.c +romstage-y += ../tegra/gpio.c +romstage-y += ../tegra/pinmux.c +romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += timer.c +ramstage-y += ../tegra/gpio.c +ramstage-y += ../tegra/pinmux.c +ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/Makefile.inc.orig b/src/soc/nvidia/tegra132/Makefile.inc.orig new file mode 100644 index 0000000..8170dd6 --- /dev/null +++ b/src/soc/nvidia/tegra132/Makefile.inc.orig @@ -0,0 +1,68 @@ +CBOOTIMAGE = cbootimage + +bootblock-y += bootblock.c +bootblock-y += bootblock_asm.S +bootblock-y += cbfs.c +bootblock-y += timer.c +bootblock-y += clock.c +bootblock-y += ../tegra/gpio.c +bootblock-y += ../tegra/i2c.c +bootblock-y += ../tegra/pingroup.c +bootblock-y += ../tegra/pinmux.c +bootblock-y += ../tegra/apbmisc.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +endif + +romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += ../tegra/gpio.c +romstage-y += ../tegra/i2c.c +romstage-y += ../tegra/pinmux.c +ifeq ($(CONFIG_EARLY_CONSOLE),y) +romstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +endif + +ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += ../tegra/gpio.c +ramstage-y += ../tegra/i2c.c +ramstage-y += ../tegra/pinmux.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c + +<<<<<<< HEAD +CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ + +# We want to grab the bootblock right before it goes into the image and wrap +# it inside a BCT, but ideally we would do that without making special, one +# use modifications to the main ARM Makefile. We do this in two ways. First, +# we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf +# template rule to turn it into bootblock.raw.bin. This makes sure whatever +# processing is supposed to happen to turn an .elf into a .bin happens. +# +# Second, we add our own rule for creating bootblock.bin from +# bootblock.raw.bin which displaces the template rule. When other rules that +# package up the image pull in bootblock.bin, it will be this wrapped version +# instead of the raw bootblock. + +$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf + cp $< $@ + +$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE) + @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" + $(CBOOTIMAGE) -gbct --soc tegra132 $< $@ + +BCT_BIN = $(obj)/generated/bct.bin +BCT_WRAPPER = $(obj)/generated/bct.wrapper +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) + echo "Version = 1;" > $(BCT_WRAPPER) + echo "Redundancy = 1;" >> $(BCT_WRAPPER) + echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) + echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER) + @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" + $(CBOOTIMAGE) $(BCT_WRAPPER) $@ +======= +INCLUDES += -Isrc/soc/nvidia/tegra132/include/ +>>>>>>> a1037f2... coreboot tegra132: Enable bootblock support in tegra132 including UART support diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c new file mode 100644 index 0000000..2d8c10f --- /dev/null +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/exception.h> +#include <arch/hlt.h> +#include <bootblock_common.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/apbmisc.h> + +#include "pinmux.h" +#include "power.h" + +void main(void) +{ + // enable pinmux clamp inputs + clamp_tristate_inputs(); + + // enable JTAG at the earliest stage + enable_jtag(); + + clock_early_uart(); + + // Serial out, tristate off. + pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); + // Serial in, tristate_on. + pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 | + PINMUX_PULL_UP | + PINMUX_INPUT_ENABLE); + // Mux some pins away from uart A. + pinmux_set_config(PINMUX_UART2_CTS_N_INDEX, + PINMUX_UART2_CTS_N_FUNC_UB3 | + PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_UART2_RTS_N_INDEX, + PINMUX_UART2_RTS_N_FUNC_UB3); + + if (CONFIG_BOOTBLOCK_CONSOLE) { + console_init(); + exception_init(); + printk(BIOS_INFO, "Tegra132: Bootblock here\n"); + } +} diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S new file mode 100644 index 0000000..ebd64a7 --- /dev/null +++ b/src/soc/nvidia/tegra132/bootblock_asm.S @@ -0,0 +1,89 @@ +/* + * Early initialization code for ARM architecture. + * + * This file is based off of the OMAP3530/ARM Cortex start.S file from Das + * U-Boot, which itself got the file from armboot. + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> + * Copyright (c) 2013 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/asm.h> + +ENTRY(_start) + /* + * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. + */ + msr cpsr_cxf, #0xdf + + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, .Stack + ldr r1, .Stack_size + sub r0, r0, r1 + ldr r1, .Stack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +/* Set stackpointer in internal RAM to call bootblock main() */ +call_bootblock: + ldr sp, .Stack /* Set up stack pointer */ + ldr r0,=0x00000000 + /* + * The current design of cpu_info places the + * struct at the top of the stack. The number of + * words pushed must be at least as large as that + * struct. + */ + push {r0-r2} + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + /* + * Use "bl" instead of "b" even though we do not intend to return. + * "bl" gets compiled to "blx" if we're transitioning from ARM to + * Thumb. However, "b" will not and GCC may attempt to create a + * wrapper which is currently broken. + */ + bl main +ENDPROC(_start) + +/* we do it this way because it's a 32-bit constant and + * in some cases too far away to be loaded as just an offset + * from IP + */ +.align 2 +.Stack: + .word CONFIG_STACK_TOP +.align 2 +/* create this size the same way we do in ramstage.ld: top-bottom */ +.Stack_size: + .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM diff --git a/src/soc/nvidia/tegra132/clk_rst.h b/src/soc/nvidia/tegra132/clk_rst.h new file mode 100644 index 0000000..9e2b33f --- /dev/null +++ b/src/soc/nvidia/tegra132/clk_rst.h @@ -0,0 +1,551 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_CLK_RST_H_ +#define _TEGRA132_CLK_RST_H_ + +/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ +struct __attribute__ ((__packed__)) clk_rst_ctlr { + u32 rst_src; /* _RST_SOURCE, 0x000 */ + u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ + u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ + u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ + u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ + u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ + u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ + u32 _rsv0; /* 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ + u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ + u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ + u32 _rsv1[3]; /* 0x034-03c */ + u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ + u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ + u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ + u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ + u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ + u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ + u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ + u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ + u32 _rsv2[8]; /* 0x060-07C */ + u32 pllc_base; /* _PLLC_BASE, 0x080 */ + u32 pllc_out; /* _PLLC_OUT, 0x084 */ + u32 pllc_misc2; /* _PLLC_MISC2, 0x088 */ + u32 pllc_misc; /* _PLLC_MISC, 0x08c */ + u32 pllm_base; /* _PLLM_BASE, 0x090 */ + u32 pllm_out; /* _PLLM_OUT, 0x094 */ + u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ + u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ + u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ + u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ + u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ + u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ + u32 plla_base; /* _PLLA_BASE, 0x0b0 */ + u32 plla_out; /* _PLLA_OUT, 0x0b4 */ + u32 _rsv3; /* 0x0b8 */ + u32 plla_misc; /* _PLLA_MISC, 0x0bc */ + u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ + u32 _rsv4[2]; /* 0x0c4-0c8 */ + u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ + u32 plld_base; /* _PLLD_BASE, 0x0d0 */ + u32 _rsv5[2]; /* 0x0d4-0d8 */ + u32 plld_misc; /* _PLLD_MISC, 0x0dc */ + u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ + u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ + u32 plle_base; /* _PLLE_BASE, 0x0e8 */ + u32 plle_misc; /* _PLLE_MISC, 0x0ec */ + u32 plls_base; /* _PLLS_BASE, 0x0f0 */ + u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ + u32 _rsv6[2]; /* 0x0f8-0fc */ + u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ + u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ + u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ + u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ + u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ + u32 _rsv7; /* 0x114 */ + u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ + u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ + u32 _rsv8; /* 0x120 */ + u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ + u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ + u32 _rsv9[2]; /* 0x12c-130 */ + u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ + u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ + u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ + u32 _rsv10[2]; /* 0x140-144 */ + u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ + u32 _rsv11; /* 0x14c */ + u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ + u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ + u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ + u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ + u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ + u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ + u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ + u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ + u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ + u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ + u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ + u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ + u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ + u32 _rsv12[2]; /* 0x184-188 */ + u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ + u32 _rsv13[2]; /* 0x190-194 */ + u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ + u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ + u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ + u32 _rsv14; /* 0x1a4 */ + u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ + u32 _rsv15[2]; /* 0x1ac-1b0 */ + u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ + u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ + u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ + u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ + u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ + u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ + u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ + u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ + u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ + u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ + u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ + u32 _rsv16[4]; /* 0x1e0-1ec */ + u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ + u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ + u32 _rsv17; /* 0x1f8 */ + u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ + u32 _rsv18[32]; /* 0x200-27c */ + u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + u32 rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + u32 _rsv19[23]; /* 0x298-2f0 */ + u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + u32 _rsv20[2]; /* 0x2f8-2fc */ + u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ + u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ + u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ + u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ + u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ + u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ + u32 _rsv21[2]; /* 0x318-31c */ + u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ + u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ + u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ + u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ + u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ + u32 clk_enb_u_clk; /* _CLK_ENB_U_CLR 0x334 */ + u32 _rsv22; /* 0x338 */ + u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ + u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ + u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ + u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ + u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ + u32 _rsv23[2]; /* 0x350-354 */ + u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ + u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ + u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ + u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ + u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ + u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ + u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ + u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ + u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ + u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ + u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ + u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ + u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ + u32 _rsv24[9]; /* 0x38c-3ac */ + u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ + u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ + u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ + u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ + u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ + u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ + u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ + u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ + u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ + u32 _rsv25; /* 0x3d4 */ + u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ + u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ + u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ + u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ + u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ + u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ + u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ + u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ + u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ + u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ + u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ + u32 _rsv26[4]; /* 0x404-410 */ + u32 clk_src_sor; /* _CLK_SOURCE_SOR_0, 0x414 */ + u32 _rsv261[2]; /* 0x404-410 */ + u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ + u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ + u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ + u32 _rsv27; /* 0x42c */ + u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ + u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ + u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ + u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ + u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ + u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ + u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ + u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ + u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ + u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ + u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ + u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ + u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ + u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ + u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ + u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ + u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ + u32 _rsv28; /* 0x474 */ + u32 intstatus; /* _INTSTATUS, 0x478 */ + u32 intmask; /* _INTMASK, 0x47c */ + u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ + u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ + u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ + u32 plle_aux; /* _PLLE_AUX, 0x48c */ + u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ + u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ + u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ + u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ + u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ + u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ + u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ + u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ + u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ + u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ + u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ + u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ + u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ + u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ + u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ + u32 _rsv29[7]; /* 0x4cc-4e4 */ + u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ + u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ + u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ + u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ + u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ + u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ + u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ + u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ + u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ + u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ + u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ + u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ + u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ + u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ + u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ + u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ + u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ + u32 _rsv30; /* 0x538 */ + u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ + u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ + u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ + u32 _rsv31; /* 0x554 */ + u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ + u32 spare_reg0; /* _SPARE_REG0, 0x55c */ + u32 _rsv32[4]; /* 0x560-0x56c */ + u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ + u32 _rsv32_1[7]; /* 0x574-58c */ + u32 plldp_base; /* _PLLDP_BASE, 0x590 */ + u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ + u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + u32 _rsrv32_2[25]; + u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ + u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ + u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ + u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ + u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ + u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ + u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ + u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ + u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ + u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ + u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ + u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ + u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ + u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ + u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ + u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ + u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ + u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ +}; +check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644); + +#define TEGRA_DEV_L 0 +#define TEGRA_DEV_H 1 +#define TEGRA_DEV_U 2 +#define TEGRA_DEV_V 0 +#define TEGRA_DEV_W 1 + +#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) + +/* Bits to enable/reset modules */ +#define CLK_ENB_CPU (1 << 0) +#define SWR_TRIG_SYS_RST (1 << 2) +#define SWR_CSITE_RST (1 << 9) +#define CLK_ENB_CSITE (1 << 9) + +/* CRC_SUPER_CCLK_DIVIDER_0 0x24 */ +#define SUPER_CDIV_ENB_ENABLE (1 << 31) + +/* CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 */ +#define EN_PPSB_STOPCLK (1 << 0) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4C) */ +#define CPU3_CLK_STP_SHIFT 11 +#define CPU2_CLK_STP_SHIFT 10 +#define CPU1_CLK_STP_SHIFT 9 +#define CPU0_CLK_STP_SHIFT 8 +#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) + +/* CRC_OSC_CTRL_0 0x50 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT) +#define OSC_PREDIV_SHIFT 26 +#define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 +#define OSC_XOBP (1 << 1) +#define OSC_XOE (1 << 0) + +enum { + OSC_FREQ_12 = 8, /* 12.0MHz */ + OSC_FREQ_13 = 0, /* 13.0MHz */ + OSC_FREQ_16P8 = 1, /* 16.8MHz */ + OSC_FREQ_19P2 = 4, /* 19.2MHz */ + OSC_FREQ_26 = 12, /* 26.0MHz */ + OSC_FREQ_38P4 = 5, /* 38.4MHz */ + OSC_FREQ_48 = 9, /* 48.0MHz */ +}; + +/* CLK_RST_CONTROLLER_PLL*_BASE_0 */ +#define PLL_BASE_BYPASS (1U << 31) +#define PLL_BASE_ENABLE (1U << 30) +#define PLL_BASE_REF_DIS (1U << 29) +#define PLL_BASE_OVRRIDE (1U << 28) +#define PLL_BASE_LOCK (1U << 27) + +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) + +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) + +#define PLL_BASE_DIVM_SHIFT 0 +#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) + +/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ +#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLM_BASE_DIVP_MASK (0x1U << PLL_BASE_DIVP_SHIFT) +#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) +#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) + +/* PLLM specific registers */ +#define PLLM_MISC1_SETUP_SHIFT 0 +#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 +#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 +#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 +#define PLLM_MISC2_KCP_SHIFT 1 +#define PLLM_MISC2_KVCO_SHIFT 0 +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) + +/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits + * on the side that we don't particularly care about. */ +#define PLL_BASE_DIV_MASK (0xffffff) + +/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ +#define PLL_OUT_RSTN (1 << 0) +#define PLL_OUT_CLKEN (1 << 1) +#define PLL_OUT_OVR (1 << 2) + +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) + +#define PLL_OUT1_SHIFT 0 +#define PLL_OUT2_SHIFT 16 +#define PLL_OUT3_SHIFT 0 +#define PLL_OUT4_SHIFT 16 + +/* CLK_RST_CONTROLLER_PLL*_MISC_0 */ +#define PLL_MISC_DCCON (1 << 20) + +#define PLL_MISC_CPCON_SHIFT 8 +#define PLL_MISC_CPCON_MASK (0xfU << PLL_MISC_CPCON_SHIFT) + +#define PLL_MISC_LFCON_SHIFT 4 +#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT) + +/* This bit is different all over the place. Oh joy... */ +#define PLLDPD2_MISC_LOCK_ENABLE (1 << 30) +#define PLLC_MISC_LOCK_ENABLE (1 << 24) +#define PLLUD_MISC_LOCK_ENABLE (1 << 22) +#define PLLD_MISC_CLK_ENABLE (1 << 30) +#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) + +#define PLLU_MISC_VCO_FREQ (1 << 20) + +/* PLLX_BASE_0 0xe0 */ +#define PLLX_BASE_PLLX_ENABLE (1 << 30) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) + +#define CLK_DIVISOR_MASK (0xffff) + +#define CLK_SOURCE_SHIFT 29 +#define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) + +#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) + +#define CLK_UART_DIV_OVERRIDE (1 << 24) + +/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ +#define SCLK_SYS_STATE_SHIFT 28U +#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) +enum { + SCLK_SYS_STATE_STDBY, + SCLK_SYS_STATE_IDLE, + SCLK_SYS_STATE_RUN, + SCLK_SYS_STATE_IRQ = 4U, + SCLK_SYS_STATE_FIQ = 8U, +}; +#define SCLK_COP_FIQ_MASK (1 << 27) +#define SCLK_CPU_FIQ_MASK (1 << 26) +#define SCLK_COP_IRQ_MASK (1 << 25) +#define SCLK_CPU_IRQ_MASK (1 << 24) + +#define SCLK_FIQ_SHIFT 12 +#define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_IRQ_SHIFT 8 +#define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_RUN_SHIFT 4 +#define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_IDLE_SHIFT 0 +#define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT) +enum { + SCLK_SOURCE_CLKM, + SCLK_SOURCE_PLLC_OUT1, + SCLK_SOURCE_PLLP_OUT4, + SCLK_SOURCE_PLLP_OUT3, + SCLK_SOURCE_PLLP_OUT2, + SCLK_SOURCE_PLLC_OUT0, + SCLK_SOURCE_CLKS, + SCLK_SOURCE_PLLM_OUT1, +}; + +/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */ +#define SCLK_DIV_ENB (1 << 31) +#define SCLK_DIVIDEND_SHIFT 8 +#define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT) +#define SCLK_DIVISOR_SHIFT 0 +#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) + +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ +#define HCLK_DISABLE (1 << 7) +#define HCLK_DIVISOR_SHIFT 4 +#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define PCLK_DISABLE (1 << 3) +#define PCLK_DIVISOR_SHIFT 0 +#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) + +// CCLK_BRST_POL +enum { + CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, + CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 +}; + +// SUPER_CCLK_DIVIDER +enum { + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +// CLK_CPU_CMPLX_CLR +enum { + CRC_CLK_CLR_CPU0_STP = 0x1 << 8, + CRC_CLK_CLR_CPU1_STP = 0x1 << 9, + CRC_CLK_CLR_CPU2_STP = 0x1 << 10, + CRC_CLK_CLR_CPU3_STP = 0x1 << 11 +}; + +// RST_CPUG_CMPLX_CLR +enum { + CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, + CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, + CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, + CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, + CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, + CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, + CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, + CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, + CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, + CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, + CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, + CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, + CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, + CRC_RST_CPUG_CLR_L2 = 0x1 << 24, + CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, +}; + +// RST_CPULP_CMPLX_CLR +enum { + CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, + CRC_RST_CPULP_CLR_L2 = 0x1 << 24, + CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, +}; + +#endif /* _TEGRA132_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c new file mode 100644 index 0000000..5237712 --- /dev/null +++ b/src/soc/nvidia/tegra132/clock.c @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <console/console.h> +#include <delay.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <stdlib.h> +#include "clk_rst.h" +#include "flow.h" +#include "maincpu.h" +#include "pmc.h" +#include "sysctr.h" + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; +static struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; +static struct sysctr_regs *sysctr = (void *)TEGRA_SYSCTR0_BASE; + +struct pll_dividers { + u32 n : 10; + u32 m : 8; + u32 p : 4; + u32 cpcon : 4; + u32 lfcon : 4; + u32 : 2; +}; + +/* Some PLLs have more restrictive divider bit lengths or are missing some + * fields. Make sure to use the right struct in the osc_table definition to get + * compile-time checking, but keep the bits aligned with struct pll_dividers so + * they can be used interchangeably at run time. Add new formats as required. */ +struct pllcx_dividers { + u32 n : 8; + u32 : 2; + u32 m : 8; + u32 p : 4; + u32 : 10; +}; +struct pllpad_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 3; + u32 : 1; + u32 cpcon : 4; + u32 : 6; +}; +struct pllu_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 1; + u32 : 3; + u32 cpcon : 4; + u32 lfcon : 4; + u32 : 2; +}; + +union __attribute__((transparent_union)) pll_fields { + u32 raw; + struct pll_dividers div; + struct pllcx_dividers cx; + struct pllpad_dividers pad; + struct pllu_dividers u; +}; + +/* This table defines the frequency dividers for every PLL to turn the external + * OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h. + * All PLLs have three dividers (n, m and p), with the governing formula for + * the output frequency being CF = (IN / m), VCO = CF * n and OUT = VCO / (2^p). + * All divisor configurations must meet the PLL's constraints for VCO and CF: + * PLLX: 12 MHz < CF < 50 MHz, 700 MHz < VCO < 3000 MHz + * PLLC: 12 MHz < CF < 50 MHz, 600 MHz < VCO < 1400 MHz + * PLLM: 12 MHz < CF < 50 MHz, 400 MHz < VCO < 1066 MHz + * PLLP: 1 MHz < CF < 6 MHz, 200 MHz < VCO < 700 MHz + * PLLD: 1 MHz < CF < 6 MHz, 500 MHz < VCO < 1000 MHz + * PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz + * PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz + * (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */ +struct { + int khz; + struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */ + struct pllcx_dividers pllc; /* target: 600 MHz */ + /* PLLM is set up dynamically by clock_sdram(). */ + /* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */ + struct pllu_dividers pllu; /* target; 960 MHz */ + struct pllcx_dividers plldp; /* target; 270 MHz */ + /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ +} static const osc_table[16] = { + [OSC_FREQ_12]{ + .khz = 12000, + .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 90, .m = 1, .p = 3}, + }, + [OSC_FREQ_13]{ + .khz = 13000, + .pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0}, + .pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */ + .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */ + }, + [OSC_FREQ_16P8]{ + .khz = 16800, + .pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0}, + .pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */ + .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2}, + .plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */ + }, + [OSC_FREQ_19P2]{ + .khz = 19200, + .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, + .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ + .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, + .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ + }, + [OSC_FREQ_26]{ + .khz = 26000, + .pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0}, + .pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */ + .pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 83, .m = 2, .p = 3}, /* 269.8 MHz */ + }, + /* These oscillators get predivided as PLL inputs... n/m/p divisors for + * 38.4 should always match 19.2, and 48 should always match 12. */ + [OSC_FREQ_38P4]{ + .khz = 38400, + .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, + .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ + .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, + .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ + }, + [OSC_FREQ_48]{ + .khz = 48000, + .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 90, .m = 1, .p = 3}, + }, +}; + +/* Get the oscillator frequency, from the corresponding hardware + * configuration field. This is actually a per-soc thing. Avoid the + * temptation to make it common. + */ +static u32 clock_get_osc_bits(void) +{ + return (readl(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; +} + +int clock_get_osc_khz(void) +{ + return osc_table[clock_get_osc_bits()].khz; +} + +int clock_get_pll_input_khz(void) +{ + u32 osc_ctrl = readl(&clk_rst->osc_ctrl); + u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; + return osc_table[osc_bits].khz >> pll_ref_div; +} + +void clock_init_arm_generic_timer(void) +{ + uint32_t freq = clock_get_osc_khz() * 1000; + // Set the cntfrq register. + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); + + // Record the system timer frequency. + write32(freq, &sysctr->cntfid0); + // Enable the system counter. + uint32_t cntcr = read32(&sysctr->cntcr); + cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; + write32(cntcr, &sysctr->cntcr); +} + +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) + +void sor_clock_stop(void) +{ + /* The Serial Output Resource clock has to be off + * before we start the plldp. Learned the hard way. + * FIXME: this has to be cleaned up a bit more. + * Waiting on some new info from Nvidia. + */ + clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); +} + +void sor_clock_start(void) +{ + /* uses PLLP, has a non-standard bit layout. */ + setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); +} + +static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) +{ + u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT | + pll.div.m << PLL_BASE_DIVM_SHIFT | + pll.div.p << PLL_BASE_DIVP_SHIFT; + u32 misc_con = pll.div.cpcon << PLL_MISC_CPCON_SHIFT | + pll.div.lfcon << PLL_MISC_LFCON_SHIFT; + + /* Write dividers but BYPASS the PLL while we're messing with it. */ + writel(dividers | PLL_BASE_BYPASS, base); + /* + * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't + * exist for this PLL) + */ + writel(lock | misc_con, misc); + + /* Enable PLL and take it back out of BYPASS */ + writel(dividers | PLL_BASE_ENABLE, base); + + /* Wait for lock ready */ + while (!(readl(base) & PLL_BASE_LOCK)); +} + +static void init_utmip_pll(void) +{ + int khz = clock_get_pll_input_khz(); + + /* Shut off PLL crystal clock while we mess with it */ + clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + udelay(1); + + write32(80 << 16 | /* (rst) phy_divn */ + 1 << 8 | /* (rst) phy_divm */ + 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + + write32(div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + 0 << 16 | /* PLLU pwrdn */ + 0 << 14 | /* pll_enable pwrdn */ + 0 << 12 | /* pll_active pwrdn */ + div_round_up(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */ + 0, &clk_rst->utmip_pll_cfg1); + + /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ + write32(0 << 24 | /* SAMP_D/XDEV pwrdn */ + div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + 0 << 4 | /* SAMP_C/USB3 pwrdn */ + 0 << 2 | /* SAMP_B/XHOST pwrdn */ + 0 << 0 | /* SAMP_A/USBD pwrdn */ + 0, &clk_rst->utmip_pll_cfg2); + + setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ +} + +/* Graphics just has to be different. There's a few more bits we + * need to set in here, but it makes sense just to restrict all the + * special bits to this one function. + */ +static void graphics_pll(void) +{ + int osc = clock_get_osc_bits(); + u32 *cfg = &clk_rst->plldp_ss_cfg; + /* the vendor code sets the dither bit (28) + * an undocumented bit (24) + * and clamp while we mess with it (22) + * Dither is pretty important to display port + * so we really do need to handle these bits. + * I'm not willing to not clamp it, even if + * it might "mostly work" with it not set, + * I don't want to find out in a few months + * that it is needed. + */ + u32 scfg = (1<<28) | (1<<24) | (1<<22); + writel(scfg, cfg); + init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, + osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); + /* leave dither and undoc bits set, release clamp */ + scfg = (1<<28) | (1<<24); + writel(scfg, cfg); + + /* disp1 will be set when panel information (pixel clock) is + * retrieved (clock_display). + */ +} + +/* Init PLLD clock source. */ +int +clock_display(u32 frequency) +{ + /** + * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz + * = (cf * n) >> p, where 1MHz < cf < 6MHz + * = ((ref / m) * n) >> p + * + * Iterate the possible values of p (3 bits, 2^7) to find out a minimum + * safe vco, then find best (m, n). since m has only 5 bits, we can + * iterate all possible values. Note Tegra 124 supports 11 bits for n, + * but our pll_fields has only 10 bits for n. + * + * Note values undershoot or overshoot target output frequency may not + * work if the values are not in "safe" range by panel specification. + */ + struct pllpad_dividers plld = { 0 }; + u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0; + u32 cf, vco; + u32 diff, best_diff; + const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, + mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, + min_cf = 1 * mhz, max_cf = 6 * mhz; + + for (vco = frequency; vco < min_vco && p < max_p; p++) + vco <<= 1; + + if (vco < min_vco || vco > max_vco) { + printk(BIOS_ERR, "%s: Cannot find out a supported VCO" + " for Frequency (%u).\n", __func__, frequency); + return -1; + } + + plld.p = p; + best_diff = vco; + + for (m = 1; m < max_m && best_diff; m++) { + cf = ref / m; + if (cf < min_cf) + break; + if (cf > max_cf) + continue; + + n = vco / cf; + if (n >= max_n) + continue; + + diff = vco - n * cf; + if (n + 1 < max_n && diff > cf / 2) { + n++; + diff = cf - diff; + } + + if (diff >= best_diff) + continue; + + best_diff = diff; + plld.m = m; + plld.n = n; + } + + if (plld.n < 50) + plld.cpcon = 2; + else if (plld.n < 300) + plld.cpcon = 3; + else if (plld.n < 600) + plld.cpcon = 8; + else + plld.cpcon = 12; + + if (best_diff) { + printk(BIOS_ERR, "%s: Failed to match output frequency %u, " + "best difference is %u.\n", __func__, frequency, + best_diff); + } + + printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", + __func__, (ref / plld.m * plld.n) >> plld.p, ref, plld.m, plld.n, + plld.p, plld.cpcon); + + init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, plld, + (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE)); + return 0; +} + +/* Initialize the UART and put it on CLK_M so we can use it during clock_init(). + * Will later move it to PLLP in clock_config(). The divisor must be very small + * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * CLK_SOURCE divider to get more precision. (This might still not be enough for + * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has + * been determined through trial and error (must lead to div 13 at 24MHz). */ +void clock_early_uart(void) +{ + write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | + CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta); + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + udelay(2); + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); +} + +/* Enable output clock (CLK1~3) for external peripherals. */ +void clock_external_output(int clk_id) +{ + switch (clk_id) { + case 1: + setbits_le32(&pmc->clk_out_cntrl, 1 << 2); + break; + case 2: + setbits_le32(&pmc->clk_out_cntrl, 1 << 10); + break; + case 3: + setbits_le32(&pmc->clk_out_cntrl, 1 << 18); + break; + default: + printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", + clk_id); + break; + } +} + +/* Start PLLM for SDRAM. */ +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq) +{ + u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) | + (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) | + (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) | + (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)), + misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | + (kcp << PLLM_MISC2_KCP_SHIFT)), + base; + + if (same_freq) + emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + else + emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + + /* + * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and + * PLLM_BASE.ENABLE must be in DISABLE state (both are the default + * values after coldboot reset). + */ + + writel(misc1, &clk_rst->pllm_misc1); + writel(misc2, &clk_rst->pllm_misc2); + + /* PLLM.BASE needs BYPASS=0, different from general init_pll */ + base = readl(&clk_rst->pllm_base); + base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | + PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); + base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | + (p << PLL_BASE_DIVP_SHIFT)); + writel(base, &clk_rst->pllm_base); + + setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); + /* stable_time is required, before we can start to check lock. */ + udelay(stable_time); + + while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { + udelay(1); + } + /* + * After PLLM reports being locked, we have to delay 10us before + * enabling PLLM_OUT. + */ + udelay(10); + + /* Put OUT1 out of reset state (start to output). */ + setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); + + /* Enable and start MEM(MC) and EMC. */ + clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); + writel(emc_source, &clk_rst->clk_src_emc); + udelay(IO_STABILIZATION_DELAY); +} + +void clock_cpu0_config_and_reset(void *entry) +{ + void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + + write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); + write32((uintptr_t)entry, &maincpu_entry_point); + write32((uintptr_t)&maincpu_setup, evp_cpu_reset); + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + // Set up cclk_brst and divider. + write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | + (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), + &clk_rst->cclk_brst_pol); + write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, + &clk_rst->super_cclk_div); + + // Enable the clocks for CPUs 0-3. + uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); + cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | + CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; + write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + + // Enable other CPU related clocks. + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); + + // Disable the reset on the non-CPU parts of the fast cluster. + write32(CRC_RST_CPUG_CLR_NONCPU, + &clk_rst->rst_cpug_cmplx_clr); + // Disable the various resets on the CPUs. + write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | + CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | + CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | + CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | + CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | + CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | + CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | + CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, + &clk_rst->rst_cpug_cmplx_clr); + + // Disable the reset on the non-CPU parts of the slow cluster. + write32(CRC_RST_CPULP_CLR_NONCPU, + &clk_rst->rst_cpulp_cmplx_clr); + // Disable the various resets on the LP CPU. + write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | + CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | + CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, + &clk_rst->rst_cpulp_cmplx_clr); +} + +void clock_halt_avp(void) +{ + for (;;) { + write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | + FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, + &flow->halt_cop_events); + } +} + +void clock_init(void) +{ + u32 osc = clock_get_osc_bits(); + + /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ + writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); + + /* Max out the AVP clock before everything else (need PLLC for that). */ + init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, + osc_table[osc].pllc, PLLC_MISC_LOCK_ENABLE); + + /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA + * features section in the TRM). */ + write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, + &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ + write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); + write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | + SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, + &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ + + /* Change the oscillator drive strength (from U-Boot -- why?) */ + clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, + OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + + /* + * Ambiguous quote from u-boot. TODO: what's this mean? + * "should update same value in PMC_OSC_EDPD_OVER XOFS + * field for warmboot " + */ + clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, + OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); + + /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ + clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); + + /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ + write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, + &clk_rst->pllp_outa); + write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, + &clk_rst->pllp_outb); + + /* init pllx */ + init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, + osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE); + + /* init pllu */ + init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, + osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE); + + init_utmip_pll(); + graphics_pll(); +} + +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +{ + if (l) writel(l, &clk_rst->clk_enb_l_set); + if (h) writel(h, &clk_rst->clk_enb_h_set); + if (u) writel(u, &clk_rst->clk_enb_u_set); + if (v) writel(v, &clk_rst->clk_enb_v_set); + if (w) writel(w, &clk_rst->clk_enb_w_set); + if (x) writel(x, &clk_rst->clk_enb_x_set); + + /* Give clocks time to stabilize. */ + udelay(IO_STABILIZATION_DELAY); + + if (l) writel(l, &clk_rst->rst_dev_l_clr); + if (h) writel(h, &clk_rst->rst_dev_h_clr); + if (u) writel(u, &clk_rst->rst_dev_u_clr); + if (v) writel(v, &clk_rst->rst_dev_v_clr); + if (w) writel(w, &clk_rst->rst_dev_w_clr); + if (x) writel(x, &clk_rst->rst_dev_x_clr); +} + +void clock_reset_l(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_l_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_l_clr); +} + +void clock_reset_h(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_h_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_h_clr); +} + +void clock_reset_u(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_u_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_u_clr); +} + +void clock_reset_v(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_v_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_v_clr); +} + +void clock_reset_w(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_w_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_w_clr); +} + +void clock_reset_x(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_x_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_x_clr); +} diff --git a/src/soc/nvidia/tegra132/flow.h b/src/soc/nvidia/tegra132/flow.h new file mode 100644 index 0000000..01dbc14 --- /dev/null +++ b/src/soc/nvidia/tegra132/flow.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_FLOW_H_ +#define _TEGRA132_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; +check_member(flow_ctlr, ram_repair, 0x40); + +enum { + FLOW_MODE_SHIFT = 29, + FLOW_MODE_MASK = 0x7 << FLOW_MODE_SHIFT, + + FLOW_MODE_NONE = 0 << FLOW_MODE_SHIFT, + FLOW_MODE_RUN_AND_INT = 1 << FLOW_MODE_SHIFT, + FLOW_MODE_WAITEVENT = 2 << FLOW_MODE_SHIFT, + FLOW_MODE_WAITEVENT_AND_INT = 3 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_IRQ = 4 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_IRQ_AND_INT = 5 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ = 6 << FLOW_MODE_SHIFT, +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +enum { + FLOW_EVENT_GIC_FIQ = 1 << 8, + FLOW_EVENT_GIC_IRQ = 1 << 9, + FLOW_EVENT_LIC_FIQ = 1 << 10, + FLOW_EVENT_LIC_IRQ = 1 << 11, + FLOW_EVENT_IBF = 1 << 12, + FLOW_EVENT_IBE = 1 << 13, + FLOW_EVENT_OBF = 1 << 14, + FLOW_EVENT_OBE = 1 << 15, + FLOW_EVENT_XRQ_A = 1 << 16, + FLOW_EVENT_XRQ_B = 1 << 17, + FLOW_EVENT_XRQ_C = 1 << 18, + FLOW_EVENT_XRQ_D = 1 << 19, + FLOW_EVENT_SMP30 = 1 << 20, + FLOW_EVENT_SMP31 = 1 << 21, + FLOW_EVENT_X_RDY = 1 << 22, + FLOW_EVENT_SEC = 1 << 23, + FLOW_EVENT_MSEC = 1 << 24, + FLOW_EVENT_USEC = 1 << 25, + FLOW_EVENT_X32K = 1 << 26, + FLOW_EVENT_SCLK = 1 << 27, + FLOW_EVENT_JTAG = 1 << 28 +}; + +#endif /* _TEGRA132_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index 5fc10c3..6f69fef 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -18,7 +18,12 @@ #ifndef __SOC_NVIDIA_TEGRA132_CLOCK_H__ #define __SOC_NVIDIA_TEGRA132_CLOCK_H__ +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/nvidia/tegra132/clk_rst.h> #include <stdint.h> +#include <stdlib.h> enum { CLK_L_CPU = 0x1 << 0, @@ -174,6 +179,7 @@ enum { #define CLOCK_PLL_STABLE_DELAY_US 300 #define IO_STABILIZATION_DELAY (2) + /* Calculate clock fractional divider value from ref and target frequencies. * This is for a U7.1 format. This is not well written up in the book and * there have been some questions about this macro, so here we go. @@ -195,7 +201,7 @@ enum { * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you * will assign this to a u8, it gets nicely truncated for you. */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2) +#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2) /* Calculate clock frequency value from reference and clock divider value * The discussion in the book is pretty lacking. @@ -216,11 +222,23 @@ enum { */ #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) +static inline void _clock_set_div(u32 *reg, const char *name, u32 div, + u32 div_mask, u32 src) +{ + // The I2C and UART divisors are 16 bit while all the others are 8 bit. + // The I2C clocks are handled by the specialized macro below, but the + // UART clocks aren't. Don't use this function on UART clocks. + if (div & ~div_mask) { + printk(BIOS_ERR, "%s clock divisor overflow!", name); + hlt(); + } + clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + src << CLK_SOURCE_SHIFT | div); +} + #define clock_configure_irregular_source(device, src, freq, src_id) \ - clrsetbits_le32(&clk_rst->clk_src_##device, \ - CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \ - src_id << CLK_SOURCE_SHIFT | \ - CLK_DIVIDER(TEGRA_##src##_KHZ, freq)) + _clock_set_div(&clk_rst->clk_src_##device, #device, \ + CLK_DIVIDER(TEGRA_##src##_KHZ, freq), 0xff, src_id) /* Warning: Some devices just use different bits for the same sources for no * apparent reason. *Always* double-check the TRM before trusting this macro. */ @@ -232,11 +250,12 @@ enum { * We can deal with those here and make it easier to select what the actual * bus frequency will be. The 0x19 value is the default divisor in the * clk_divisor register in the controller, and 8 is just a magic number in the - * documentation. Multiplying by 2 compensates for the different format of the - * divisor. + * documentation. */ #define clock_configure_i2c_scl_freq(device, src, freq) \ - clock_configure_source(device, src, (freq) * (0x19 + 1) * 8 * 2) + _clock_set_div(&clk_rst->clk_src_##device, #device, \ + div_round_up(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \ + 0xffff, src) enum clock_source { /* Careful: Not true for all sources, always check TRM! */ PLLP = 0, @@ -259,6 +278,8 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */ #define TEGRA_PLLU_KHZ (960000) int clock_get_osc_khz(void); +int clock_get_pll_input_khz(void); +int clock_display(u32 frequency); void clock_early_uart(void); void clock_external_output(int clk_id); void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, @@ -267,6 +288,12 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, void clock_cpu0_config_and_reset(void * entry); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); +void clock_reset_l(u32 l); +void clock_reset_h(u32 h); +void clock_reset_u(u32 u); +void clock_reset_v(u32 v); +void clock_reset_w(u32 w); +void clock_reset_x(u32 x); void clock_init(void); void clock_init_arm_generic_timer(void); void sor_clock_stop(void); diff --git a/src/soc/nvidia/tegra132/maincpu.S b/src/soc/nvidia/tegra132/maincpu.S new file mode 100644 index 0000000..898d821 --- /dev/null +++ b/src/soc/nvidia/tegra132/maincpu.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +ENTRY(maincpu_setup) + /* + * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. + */ + msr cpsr, #0xdf + + ldr sp, maincpu_stack_pointer + eor lr, lr + ldr r0, maincpu_entry_point + bx r0 +ENDPROC(maincpu_setup) + + .align 2 + + .global maincpu_stack_pointer +maincpu_stack_pointer: + .word 0 + + .global maincpu_entry_point +maincpu_entry_point: + .word 0 diff --git a/src/soc/nvidia/tegra132/maincpu.h b/src/soc/nvidia/tegra132/maincpu.h new file mode 100644 index 0000000..1f795df --- /dev/null +++ b/src/soc/nvidia/tegra132/maincpu.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_MAINCPU_H__ +#define __SOC_NVIDIA_TEGRA132_MAINCPU_H__ + +#include <stdint.h> + +extern u32 maincpu_stack_pointer; +extern u32 maincpu_entry_point; +void maincpu_setup(void); + +#endif /* __SOC_NVIDIA_TEGRA132_MAINCPU_H__ */ diff --git a/src/soc/nvidia/tegra132/pinmux.h b/src/soc/nvidia/tegra132/pinmux.h new file mode 100644 index 0000000..2bed253 --- /dev/null +++ b/src/soc/nvidia/tegra132/pinmux.h @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_PINMUX_H__ +#define __SOC_NVIDIA_TEGRA132_PINMUX_H__ + +#include <soc/nvidia/tegra/pinmux.h> +#include <stdint.h> + +#define PINMUX_CONSTANTS(index, name, gpio, func0, func1, func2, func3) \ + PINMUX_##name##_INDEX = index, \ + PINMUX_##name##_FUNC_##func0 = 0, \ + PINMUX_##name##_FUNC_##func1 = 1, \ + PINMUX_##name##_FUNC_##func2 = 2, \ + PINMUX_##name##_FUNC_##func3 = 3, \ + PINMUX_GPIO_##gpio = PINMUX_##name##_INDEX + +enum { + PINMUX_CONSTANTS(0, ULPI_DATA0, O1, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(1, ULPI_DATA1, O2, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(2, ULPI_DATA2, O3, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(3, ULPI_DATA3, O4, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(4, ULPI_DATA4, O5, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(5, ULPI_DATA5, O6, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(6, ULPI_DATA6, O7, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(7, ULPI_DATA7, O0, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(8, ULPI_CLK, Y0, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(9, ULPI_DIR, Y1, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(10, ULPI_NXT, Y2, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(11, ULPI_STP, Y3, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(12, DAP3_FS, P0, I2S2, SPI5, DCA, DCB), + PINMUX_CONSTANTS(13, DAP3_DIN, P1, I2S2, SPI5, DCA, DCB), + PINMUX_CONSTANTS(14, DAP3_DOUT, P2, I2S2, SPI5, DCA, RES3), + PINMUX_CONSTANTS(15, DAP3_SCLK, P3, I2S2, SPI5, RES2, DCB), + PINMUX_CONSTANTS(16, GPIO_PV0, V0, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(17, GPIO_PV1, V1, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(18, SDMMC1_CLK, Z0, SDMMC1, CLK12M, RES2, RES3), + PINMUX_CONSTANTS(19, SDMMC1_CMD, Z1, SDMMC1, SPDIF, SPI4, UA3), + PINMUX_CONSTANTS(20, SDMMC1_DAT3, Y4, SDMMC1, SPDIF, SPI4, UA3), + PINMUX_CONSTANTS(21, SDMMC1_DAT2, Y5, SDMMC1, PWM0, SPI4, UA3), + PINMUX_CONSTANTS(22, SDMMC1_DAT1, Y6, SDMMC1, PWM1, SPI4, UA3), + PINMUX_CONSTANTS(23, SDMMC1_DAT0, Y7, SDMMC1, RES1, SPI4, UA3), + PINMUX_CONSTANTS(26, CLK2_OUT, W5, EXTPERIPH2, RES1, RES2, RES3), + PINMUX_CONSTANTS(27, CLK2_REQ, CC5, DAP, RES1, RES2, RES3), + PINMUX_CONSTANTS(68, HDMI_INT, N7, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(69, DDC_SCL, V4, I2C4, RES1, RES2, RES3), + PINMUX_CONSTANTS(70, DDC_SDA, V5, I2C4, RES1, RES2, RES3), + PINMUX_CONSTANTS(89, UART2_RXD, C3, IR3, SPDIF, UA3, SPI4), + PINMUX_CONSTANTS(90, UART2_TXD, C2, IR3, SPDIF, UA3, SPI4), + PINMUX_CONSTANTS(91, UART2_RTS_N, J6, UA3, UB3, NOR, SPI4), + PINMUX_CONSTANTS(92, UART2_CTS_N, J5, UA3, UB3, NOR, SPI4), + PINMUX_CONSTANTS(93, UART3_TXD, W6, UC3, RES1, NOR, SPI4), + PINMUX_CONSTANTS(94, UART3_RXD, W7, UC3, RES1, NOR, SPI4), + PINMUX_CONSTANTS(95, UART3_CTS_N, A1, UC3, SDMMC1, DTV, NOR), + PINMUX_CONSTANTS(96, UART3_RTS_N, C0, UC3, PWM0, DTV, NOR), + PINMUX_CONSTANTS(97, GPIO_PU0, U0, OWR, UA3, NOR, RES3), + PINMUX_CONSTANTS(98, GPIO_PU1, U1, RES0, UA3, NOR, RES3), + PINMUX_CONSTANTS(99, GPIO_PU2, U2, RES0, UA3, NOR, RES3), + PINMUX_CONSTANTS(100, GPIO_PU3, U3, PWM0, UA3, NOR, DCB), + PINMUX_CONSTANTS(101, GPIO_PU4, U4, PWM1, UA3, NOR, DCB), + PINMUX_CONSTANTS(102, GPIO_PU5, U5, PWM2, UA3, NOR, DCB), + PINMUX_CONSTANTS(103, GPIO_PU6, U6, PWM3, UA3, RES2, NOR), + PINMUX_CONSTANTS(104, GEN1_I2C_SDA, C5, I2C1, RES1, RES2, RES3), + PINMUX_CONSTANTS(105, GEN1_I2C_SCL, C4, I2C1, RES1, RES2, RES3), + PINMUX_CONSTANTS(106, DAP4_FS, P4, I2S3, NOR, DTV, RES3), + PINMUX_CONSTANTS(107, DAP4_DIN, P5, I2S3, NOR, RES2, RES3), + PINMUX_CONSTANTS(108, DAP4_DOUT, P6, I2S3, NOR, DTV, RES3), + PINMUX_CONSTANTS(109, DAP4_SCLK, P7, I2S3, NOR, RES2, RES3), + PINMUX_CONSTANTS(110, CLK3_OUT, EE0, EXTPERIPH3, RES1, RES2, RES3), + PINMUX_CONSTANTS(111, CLK3_REQ, EE1, DEV3, RES1, RES2, RES3), + PINMUX_CONSTANTS(112, GPIO_PC7, C7, RES0, RES1, NOR_WP_N, NOR_INT1), + PINMUX_CONSTANTS(113, GPIO_PI5, I5, SDMMC2, RES1, NOR, RES3), + PINMUX_CONSTANTS(114, GPIO_PI7, I7, RES0, TRACE, NOR, DTV), + PINMUX_CONSTANTS(115, GPIO_PK0, K0, RES0, SDMMC3, NOR, SOC_THERM), + PINMUX_CONSTANTS(116, GPIO_PK1, K1, SDMMC2, TRACE, NOR, RES3), + PINMUX_CONSTANTS(117, GPIO_PJ0, J0, RES0, RES1, NOR, USB), + PINMUX_CONSTANTS(118, GPIO_PJ2, J2, RES0, RES1, NOR, SOC_THERM), + PINMUX_CONSTANTS(119, GPIO_PK3, K3, SDMMC2, TRACE, NOR, CCLA), + PINMUX_CONSTANTS(120, GPIO_PK4, K4, SDMMC2, RES1, NOR_AD22, NOR_INT1), + PINMUX_CONSTANTS(121, GPIO_PK2, K2, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(122, GPIO_PI3, I3, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(123, GPIO_PI6, I6, RES0, RES1, NOR, SDMMC2), + PINMUX_CONSTANTS(124, GPIO_PG0, G0, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(125, GPIO_PG1, G1, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(126, GPIO_PG2, G2, RES0, TRACE, NOR, RES3), + PINMUX_CONSTANTS(127, GPIO_PG3, G3, RES0, TRACE, NOR, RES3), + PINMUX_CONSTANTS(128, GPIO_PG4, G4, RES0, TMDS, NOR, SPI4), + PINMUX_CONSTANTS(129, GPIO_PG5, G5, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(130, GPIO_PG6, G6, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(131, GPIO_PG7, G7, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(132, GPIO_PH0, H0, PWM0, TRACE, NOR, DTV), + PINMUX_CONSTANTS(133, GPIO_PH1, H1, PWM1, TMDS, NOR, DCA), + PINMUX_CONSTANTS(134, GPIO_PH2, H2, PWM2, TDMS, NOR, CLDVFS), + PINMUX_CONSTANTS(135, GPIO_PH3, H3, PWM3, SPI4, NOR, CLDVFS), + PINMUX_CONSTANTS(136, GPIO_PH4, H4, SDMMC2, RES1, NOR, RES3), + PINMUX_CONSTANTS(137, GPIO_PH5, H5, SDMMC2, RES1, NOR, RES3), + PINMUX_CONSTANTS(138, GPIO_PH6, H6, SDMMC2, TRACE, NOR, DTV), + PINMUX_CONSTANTS(139, GPIO_PH7, H7, SDMMC2, TRACE, NOR, DTV), + PINMUX_CONSTANTS(140, GPIO_PJ7, J7, UD3, RES1, NOR_AD16, NOR_INT2), + PINMUX_CONSTANTS(141, GPIO_PB0, B0, UD3, RES1, NOR, RES3), + PINMUX_CONSTANTS(142, GPIO_PB1, B1, UD3, RES1, NOR, RES3), + PINMUX_CONSTANTS(143, GPIO_PK7, K7, UD3, RES1, NOR, RES3), + PINMUX_CONSTANTS(144, GPIO_PI0, I0, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(145, GPIO_PI1, I1, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(146, GPIO_PI2, I2, SDMMC2, TRACE, NOR, RES3), + PINMUX_CONSTANTS(147, GPIO_PI4, I4, SPI4, TRACE, NOR, DCA), + PINMUX_CONSTANTS(148, GEN2_I2C_SCL, T5, I2C2, RES1, NOR, RES3), + PINMUX_CONSTANTS(149, GEN2_I2C_SDA, T6, I2C2, RES1, NOR, RES3), + PINMUX_CONSTANTS(150, SDMMC4_CLK, CC4, SDMMC4, RES1, NOR, RES3), + PINMUX_CONSTANTS(151, SDMMC4_CMD, T7, SDMMC4, RES1, NOR, RES3), + PINMUX_CONSTANTS(152, SDMMC4_DAT0, AA0, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(153, SDMMC4_DAT1, AA1, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(154, SDMMC4_DAT2, AA2, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(155, SDMMC4_DAT3, AA3, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(156, SDMMC4_DAT4, AA4, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(157, SDMMC4_DAT5, AA5, SDMMC4, SPI3, RES2, RES3), + PINMUX_CONSTANTS(158, SDMMC4_DAT6, AA6, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(159, SDMMC4_DAT7, AA7, SDMMC4, RES1, NOR, RES3), + PINMUX_CONSTANTS(161, CAM_MCLK, CC0, VIMCLK_PRI, VIMCLK_ALT1, + VIMCLK_ALT3, SDMMC2), + PINMUX_CONSTANTS(162, GPIO_PCC1, CC1, I2S4, RES1, RES2, SDMMC2), + PINMUX_CONSTANTS(163, GPIO_PBB0, BB0, VGP6, VIMCLK2_PRI, SDMMC2, + VIMCLK2_ALT3), + PINMUX_CONSTANTS(164, CAM_I2C_SCL, BB1, VGP1, I2C3, RES2, SDMMC2), + PINMUX_CONSTANTS(165, CAM_I2C_SDA, BB2, VGP2, I2C3, RES2, SDMMC2), + PINMUX_CONSTANTS(166, GPIO_PBB3, BB3, VGP3, DCA, DCB, SDMMC2), + PINMUX_CONSTANTS(167, GPIO_PBB4, BB4, VGP4, DCA, DCB, SDMMC2), + PINMUX_CONSTANTS(168, GPIO_PBB5, BB5, VGP5, DCA, RES2, SDMMC2), + PINMUX_CONSTANTS(169, GPIO_PBB6, BB6, I2S4, RES1, DCB, SDMMC2), + PINMUX_CONSTANTS(170, GPIO_PBB7, BB7, I2S4, RES1, RES2, SDMMC2), + PINMUX_CONSTANTS(171, GPIO_PCC2, CC2, I2S4, RES1, SDMMC3, SDMMC2), + PINMUX_CONSTANTS(172, JTAG_RTCK, NONE172, RTCK, RES1, RES2, RES3), + PINMUX_CONSTANTS(173, PWR_I2C_SCL, Z6, I2CPMU, RES1, RES2, RES3), + PINMUX_CONSTANTS(174, PWR_I2C_SDA, Z7, I2CPMU, RES1, RES2, RES3), + PINMUX_CONSTANTS(175, KB_ROW0, R0, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(176, KB_ROW1, R1, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(177, KB_ROW2, R2, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(178, KB_ROW3, R3, RES0, DCA, SYS_CLK, DCB), + PINMUX_CONSTANTS(179, KB_ROW4, R4, RES0, DCA, RES2, DCB), + PINMUX_CONSTANTS(180, KB_ROW5, R5, RES0, DCA, RES2, DCB), + PINMUX_CONSTANTS(181, KB_ROW6, R6, RES0, DCA_LSC0, DCA_LSPII, DCB), + PINMUX_CONSTANTS(182, KB_ROW7, R7, RES0, RES1, CLDVFS, UA3), + PINMUX_CONSTANTS(183, KB_ROW8, S0, RES0, RES1, CLDVFS, UA3), + PINMUX_CONSTANTS(184, KB_ROW9, S1, RES0, RES1, RES2, UA3), + PINMUX_CONSTANTS(185, KB_ROW10, S2, RES0, RES1, RES2, UA3), + PINMUX_CONSTANTS(186, KB_ROW11, S3, RES0, RES1, RES2, IR3), + PINMUX_CONSTANTS(187, KB_ROW12, S4, RES0, RES1, RES2, IR3), + PINMUX_CONSTANTS(188, KB_ROW13, S5, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(189, KB_ROW14, S6, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(190, KB_ROW15, S7, RES0, SOC_THERM, RES2, RES3), + PINMUX_CONSTANTS(191, KB_COL0, Q0, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(192, KB_COL1, Q1, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(193, KB_COL2, Q2, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(194, KB_COL3, Q3, RES0, DCA, PWM2, UA3), + PINMUX_CONSTANTS(195, KB_COL4, Q4, RES0, OWR, SDMMC3, UA3), + PINMUX_CONSTANTS(196, KB_COL5, Q5, RES0, RES1, SDMMC3, RES3), + PINMUX_CONSTANTS(197, KB_COL6, Q6, RES0, RES1, SPI2, UD3), + PINMUX_CONSTANTS(198, KB_COL7, Q7, RES0, RES1, SPI2, UD3), + PINMUX_CONSTANTS(199, CLK_32K_OUT, A0, BLINK, SOC_THERM, RES2, RES3), + PINMUX_CONSTANTS(201, CORE_PWR_REQ, NONE201, PWRON, RES1, RES2, RES3), + PINMUX_CONSTANTS(202, CPU_PWR_REQ, NONE202, CPU, RES1, RES2, RES3), + PINMUX_CONSTANTS(203, PWR_INT_N, NONE203, PMICINTR, RES1, RES2, RES3), + PINMUX_CONSTANTS(204, CLK_32K_IN, NONE204, CLK_32K_IN, RES1, RES2, + RES3), + PINMUX_CONSTANTS(205, OWR, NONE205, OWR, RES1, RES2, RES3), + PINMUX_CONSTANTS(206, DAP1_FS, N0, I2S0, DAP1, NOR, RES3), + PINMUX_CONSTANTS(207, DAP1_DIN, N1, I2S0, DAP1, NOR, RES3), + PINMUX_CONSTANTS(208, DAP1_DOUT, N2, I2S0, DAP1, NOR, SATA), + PINMUX_CONSTANTS(209, DAP1_SCLK, N3, I2S0, DAP1, NOR, RES3), + PINMUX_CONSTANTS(210, DAP_MCLK1_REQ, EE2, DAP, DAP1, SATA, RES3), + PINMUX_CONSTANTS(211, DAP_MCLK1, W4, EXTPERIPH1, DAP2, RES2, RES3), + PINMUX_CONSTANTS(212, SPDIF_IN, K6, SPDIF, RES1, RES2, I2C3), + PINMUX_CONSTANTS(213, SPDIF_OUT, K5, SPDIF, RES1, RES2, I2C3), + PINMUX_CONSTANTS(214, DAP2_FS, A2, I2S1, DAP2, NOR, RES3), + PINMUX_CONSTANTS(215, DAP2_DIN, A4, I2S1, DAP2, NOR, RES3), + PINMUX_CONSTANTS(216, DAP2_DOUT, A5, I2S1, DAP2, NOR, RES3), + PINMUX_CONSTANTS(217, DAP2_SCLK, A3, I2S1, SAP2, NOR, RES3), + PINMUX_CONSTANTS(218, DVFS_PWM, X0, SPI6, CLDVFS, NOR, RES3), + PINMUX_CONSTANTS(219, GPIO_X1_AUD, X1, SPI6, RES1, NOR, RES3), + PINMUX_CONSTANTS(220, GPIO_X3_AUD, X3, SPI6, SPI1, NOR, RES3), + PINMUX_CONSTANTS(221, DVFS_CLK, X2, SPI6, CLDVFS_CLK, NOR, RES3), + PINMUX_CONSTANTS(222, GPIO_X4_AUD, X4, NOR, SPI1, SPI2, DAP2), + PINMUX_CONSTANTS(223, GPIO_X5_AUD, X5, NOR, SPI1, SPI2, RES3), + PINMUX_CONSTANTS(224, GPIO_X6_AUD, X6, SPI6, SPI1, SPI2, NOR), + PINMUX_CONSTANTS(225, GPIO_X7_AUD, X7, RES0, SPI1, SPI2, RES3), + PINMUX_CONSTANTS(228, SDMMC3_CLK, A6, SDMMC3, RES1, RES2, SPI3), + PINMUX_CONSTANTS(229, SDMMC3_CMD, A7, SDMMC3, PWM3, UA3, SPI3), + PINMUX_CONSTANTS(230, SDMMC3_DAT0, B7, SDMMC3, RES1, RES2, SPI3), + PINMUX_CONSTANTS(231, SDMMC3_DAT1, B6, SDMMC3, PWM2, UA3, SPI3), + PINMUX_CONSTANTS(232, SDMMC3_DAT2, B5, SDMMC3, PWM1, DCA, SPI3), + PINMUX_CONSTANTS(233, SDMMC3_DAT3, B4, SDMMC3, PWM0, DCB, SPI3), + PINMUX_CONSTANTS(239, PEX_L0_RST_N, DD1, PE0, RES1, RES2, RES3), + PINMUX_CONSTANTS(240, PEX_L0_CLKREQ_N, DD2, PE0, RES1, RES2, RES3), + PINMUX_CONSTANTS(241, PEX_WAKE_N, DD3, PE, RES1, RES2, RES3), + PINMUX_CONSTANTS(243, PEX_L1_RST_N, DD5, PE1, RES1, RES2, RES3), + PINMUX_CONSTANTS(244, PEX_L1_CLKREQ_N, DD6, PE1, RES1, RES2, RES3), + PINMUX_CONSTANTS(248, HDMI_CEC, EE3, CEC, RES1, RES2, RES3), + PINMUX_CONSTANTS(249, SDMMC1_WP_N, V3, SDMMC1, CLK12M, SPI4, UA3), + PINMUX_CONSTANTS(250, SDMMC3_CD_N, V2, SDMMC3, OWR, RES2, RES3), + PINMUX_CONSTANTS(251, GPIO_W2_AUD, W2, SPI6, RES1, SPI2, I2C1), + PINMUX_CONSTANTS(252, GPIO_W3_AUD, W3, SPI6, SPI1, SPI2, I2C1), + PINMUX_CONSTANTS(253, USB_VBUS_EN0, N4, USB, RES1, RES2, RES3), + PINMUX_CONSTANTS(254, USB_VBUS_EN1, N5, USB, RES1, RES2, RES3), + PINMUX_CONSTANTS(255, SDMMC3_CLK_LB_IN, EE5, SDMMC3, RES1, RES2, RES3), + PINMUX_CONSTANTS(256, SDMMC3_CLK_LB_OUT, EE4, SDMMC3, RES1, RES2, RES3), + PINMUX_CONSTANTS(258, RESET_OUT_N, NONE258, RES0, RES1, RES2, RESET), + PINMUX_CONSTANTS(259, KB_ROW16, T0, RES0, RES1, RES2, UC3), + PINMUX_CONSTANTS(260, KB_ROW17, T1, RES0, RES1, RES2, UC3), + PINMUX_CONSTANTS(261, USB_VBUS_EN2, FF1, USB, RES1, RES2, RES3), + PINMUX_CONSTANTS(262, GPIO_PFF2, FF2, SATA, RES1, RES2, RES3), + PINMUX_CONSTANTS(268, DP_HPD, FF0, DP, RES1, RES2, RES3), + + // Where do these go? + /* + PINMUX_JTAG_TRST_N_JTAG_TRST_N = 0, + + PINMUX_JTAG_TDO_JTAG_TDO = 0, + + PINMUX_JTAG_TMS_JTAG_TMS = 0, + + PINMUX_JTAG_TCK_JTAG_TCK = 0, + // What do functions 1 and 2 do? + + PINMUX_JTAG_TDI_JTAG_TDI = 0, + PINMUX_JTAG_TDI_PWR_BREAK = 1, + + PINMUX_TEST_MODE_EN_TEST_MODE_EN = 0, + PINMUX_TEST_MODE_EN_VIMCLK_PRI = 1, + PINMUX_TEST_MODE_EN_VIMCLK_ALT1 = 2, + PINMUX_TEST_MODE_EN_VIMCLK_ALT3 = 3, + + PINMUX_DP_AUX_CH0_P_I2C_CLK = 0, + PINMUX_DP_AUX_CH0_P_SDMMC3_DAT3 = 1, + PINMUX_DP_AUX_CH0_P_PM3_PWM0 = 2, + PINMUX_DP_AUX_CH0_P_DCB_LPM0 = 3, + + PINMUX_DP_AUX_CH0_N_I2C6_DAT = 0, + PINMUX_DP_AUX_CH0_N_SDMMC3_DAT2 = 1, + PINMUX_DP_AUX_CH0_N_PM3_PWM1 = 2, + PINMUX_DP_AUX_CH0_N_DCA_LPM0 = 3, + */ +}; + +#endif /* __SOC_NVIDIA_TEGRA132_PINMUX_H__ */ diff --git a/src/soc/nvidia/tegra132/pmc.h b/src/soc/nvidia/tegra132/pmc.h new file mode 100644 index 0000000..e9fbcd6 --- /dev/null +++ b/src/soc/nvidia/tegra132/pmc.h @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_PMC_H_ +#define _TEGRA132_PMC_H_ + +#include <stdint.h> + +enum { + POWER_PARTID_CRAIL = 0, + POWER_PARTID_TD = 1, + POWER_PARTID_VE = 2, + POWER_PARTID_VDE = 4, + POWER_PARTID_L2C = 5, + POWER_PARTID_MPE = 6, + POWER_PARTID_HEG = 7, + POWER_PARTID_CE1 = 9, + POWER_PARTID_CE2 = 10, + POWER_PARTID_CE3 = 11, + POWER_PARTID_CELP = 12, + POWER_PARTID_CE0 = 14, + POWER_PARTID_C0NC = 15, + POWER_PARTID_C1NC = 16, + POWER_PARTID_DIS = 18, + POWER_PARTID_DISB = 19, + POWER_PARTID_XUSBA = 20, + POWER_PARTID_XUSBB = 21, + POWER_PARTID_XUSBC = 22 +}; + +struct tegra_pmc_regs { + u32 cntrl; + u32 sec_disable; + u32 pmc_swrst; + u32 wake_mask; + u32 wake_lvl; + u32 wake_status; + u32 sw_wake_status; + u32 dpd_pads_oride; + u32 dpd_sample; + u32 dpd_enable; + u32 pwrgate_timer_off; + u32 clamp_status; + u32 pwrgate_toggle; + u32 remove_clamping_cmd; + u32 pwrgate_status; + u32 pwrgood_timer; + u32 blink_timer; + u32 no_iopower; + u32 pwr_det; + u32 pwr_det_latch; + u32 scratch0; + u32 scratch1; + u32 scratch2; + u32 scratch3; + u32 scratch4; + u32 scratch5; + u32 scratch6; + u32 scratch7; + u32 scratch8; + u32 scratch9; + u32 scratch10; + u32 scratch11; + u32 scratch12; + u32 scratch13; + u32 scratch14; + u32 scratch15; + u32 scratch16; + u32 scratch17; + u32 scratch18; + u32 scratch19; + u32 odmdata; + u32 scratch21; + u32 scratch22; + u32 scratch23; + u32 secure_scratch0; + u32 secure_scratch1; + u32 secure_scratch2; + u32 secure_scratch3; + u32 secure_scratch4; + u32 secure_scratch5; + u32 cpupwrgood_timer; + u32 cpupwroff_timer; + u32 pg_mask; + u32 pg_mask_1; + u32 auto_wake_lvl; + u32 auto_wake_lvl_mask; + u32 wake_delay; + u32 pwr_det_val; + u32 ddr_pwr; + u32 usb_debounce_del; + u32 usb_a0; + u32 crypto_op; + u32 pllp_wb0_override; + u32 scratch24; + u32 scratch25; + u32 scratch26; + u32 scratch27; + u32 scratch28; + u32 scratch29; + u32 scratch30; + u32 scratch31; + u32 scratch32; + u32 scratch33; + u32 scratch34; + u32 scratch35; + u32 scratch36; + u32 scratch37; + u32 scratch38; + u32 scratch39; + u32 scratch40; + u32 scratch41; + u32 scratch42; + u32 bondout_mirror[3]; + u32 sys_33v_en; + u32 bondout_mirror_access; + u32 gate; + u32 wake2_mask; + u32 wake2_lvl; + u32 wake2_status; + u32 sw_wake2_status; + u32 auto_wake2_lvl_mask; + u32 pg_mask_2; + u32 pg_mask_ce1; + u32 pg_mask_ce2; + u32 pg_mask_ce3; + u32 pwrgate_timer_ce[7]; + u32 pcx_edpd_cntrl; + u32 osc_edpd_over; + u32 clk_out_cntrl; + u32 sata_pwrgt; + u32 sensor_ctrl; + u32 rst_status; + u32 io_dpd_req; + u32 io_dpd_status; + u32 io_dpd2_req; + u32 io_dpd2_status; + u32 sel_dpd_tim; + u32 vddp_sel; + u32 ddr_cfg; + u32 e_no_vttgen; + u8 _rsv0[4]; + u32 pllm_wb0_override_freq; + u32 test_pwrgate; + u32 pwrgate_timer_mult; + u32 dis_sel_dpd; + u32 utmip_uhsic_triggers; + u32 utmip_uhsic_saved_state; + u32 utmip_pad_cfg; + u32 utmip_term_pad_cfg; + u32 utmip_uhsic_sleep_cfg; + u32 utmip_uhsic_sleepwalk_cfg; + u32 utmip_sleepwalk_p[3]; + u32 uhsic_sleepwalk_p0; + u32 utmip_uhsic_status; + u32 utmip_uhsic_fake; + u32 bondout_mirror3[5 - 3]; + u32 secure_scratch6; + u32 secure_scratch7; + u32 scratch43; + u32 scratch44; + u32 scratch45; + u32 scratch46; + u32 scratch47; + u32 scratch48; + u32 scratch49; + u32 scratch50; + u32 scratch51; + u32 scratch52; + u32 scratch53; + u32 scratch54; + u32 scratch55; + u32 scratch0_eco; + u32 por_dpd_ctrl; + u32 scratch2_eco; + u32 utmip_uhsic_line_wakeup; + u32 utmip_bias_master_cntrl; + u32 utmip_master_config; + u32 td_pwrgate_inter_part_timer; + u32 utmip_uhsic2_triggers; + u32 utmip_uhsic2_saved_state; + u32 utmip_uhsic2_sleep_cfg; + u32 utmip_uhsic2_sleepwalk_cfg; + u32 uhsic2_sleepwalk_p1; + u32 utmip_uhsic2_status; + u32 utmip_uhsic2_fake; + u32 utmip_uhsic2_line_wakeup; + u32 utmip_master2_config; + u32 utmip_uhsic_rpd_cfg; + u32 pg_mask_ce0; + u32 pg_mask3[5 - 3]; + u32 pllm_wb0_override2; + u32 tsc_mult; + u32 cpu_vsense_override; + u32 glb_amap_cfg; + u32 sticky_bits; + u32 sec_disable2; + u32 weak_bias; + u32 reg_short; + u32 pg_mask_andor; + u8 _rsv1[0x2c]; + u32 secure_scratch8; + u32 secure_scratch9; + u32 secure_scratch10; + u32 secure_scratch11; + u32 secure_scratch12; + u32 secure_scratch13; + u32 secure_scratch14; + u32 secure_scratch15; + u32 secure_scratch16; + u32 secure_scratch17; + u32 secure_scratch18; + u32 secure_scratch19; + u32 secure_scratch20; + u32 secure_scratch21; + u32 secure_scratch22; + u32 secure_scratch23; + u32 secure_scratch24; + u32 secure_scratch25; + u32 secure_scratch26; + u32 secure_scratch27; + u32 secure_scratch28; + u32 secure_scratch29; + u32 secure_scratch30; + u32 secure_scratch31; + u32 secure_scratch32; + u32 secure_scratch33; + u32 secure_scratch34; + u32 secure_scratch35; + u8 _rsv2[0xd0]; + u32 cntrl2; + u8 _rsv3[0x18]; + u32 io_dpd3_req; + u32 io_dqd3_status; + u32 strapping_opt_a; + u8 _rsv4[0x198]; + u32 scratch56; + u32 scratch57; + u32 scratch58; + u32 scratch59; + u32 scratch60; + u32 scratch61; + u32 scratch62; + u32 scratch63; + u32 scratch64; + u32 scratch65; + u32 scratch66; + u32 scratch67; + u32 scratch68; + u32 scratch69; + u32 scratch70; + u32 scratch71; + u32 scratch72; + u32 scratch73; + u32 scratch74; + u32 scratch75; + u32 scratch76; + u32 scratch77; + u32 scratch78; + u32 scratch79; + u32 scratch80; + u32 scratch81; + u32 scratch82; + u32 scratch83; + u32 scratch84; + u32 scratch85; + u32 scratch86; + u32 scratch87; + u32 scratch88; + u32 scratch89; + u32 scratch90; + u32 scratch91; + u32 scratch92; + u32 scratch93; + u32 scratch94; + u32 scratch95; + u32 scratch96; + u32 scratch97; + u32 scratch98; + u32 scratch99; + u32 scratch100; + u32 scratch101; + u32 scratch102; + u32 scratch103; + u32 scratch104; + u32 scratch105; + u32 scratch106; + u32 scratch107; + u32 scratch108; + u32 scratch109; + u32 scratch110; + u32 scratch111; + u32 scratch112; + u32 scratch113; + u32 scratch114; + u32 scratch115; + u32 scratch116; + u32 scratch117; + u32 scratch118; + u32 scratch119; +}; + +check_member(tegra_pmc_regs, scratch119, 0x6fc); + +enum { + PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, + PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, + PMC_PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +enum { + PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, + PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, + PMC_CNTRL_RTC_RST = 0x1 << 2, + PMC_CNTRL_KBC_RST = 0x1 << 3, + PMC_CNTRL_MAIN_RST = 0x1 << 4, + PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, + PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, + PMC_CNTRL_BLINK_EN = 0x1 << 7, + PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, + PMC_CNTRL_PWRREQ_OE = 0x1 << 9, + PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, + PMC_CNTRL_SYSCLK_OE = 0x1 << 11, + PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, + PMC_CNTRL_AOINIT = 0x1 << 13, + PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, + PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, + PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, + PMC_CNTRL_INTR_POLARITY = 0x1 << 17, + PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, + PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, + PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, + PMC_CNTRL_CPUPWRGOOD_SEL_MASK = + 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT +}; + +enum { + PMC_DDR_PWR_EMMC_MASK = 1 << 1, + PMC_DDR_PWR_VAL_MASK = 1 << 0, +}; + +enum { + PMC_DDR_CFG_PKG_MASK = 1 << 0, + PMC_DDR_CFG_IF_MASK = 1 << 1, + PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, +}; + +enum { + PMC_NO_IOPOWER_MEM_MASK = 1 << 7, + PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, +}; + +enum { + PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, +}; + +enum { + PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 +}; + +enum { + PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, + PMC_OSC_EDPD_OVER_XOFS_MASK = + 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT +}; + +enum { + PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, + PMC_STRAPPING_OPT_A_RAM_CODE_MASK = + 0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT, +}; + +#endif /* _TEGRA132_PMC_H_ */ diff --git a/src/soc/nvidia/tegra132/power.h b/src/soc/nvidia/tegra132/power.h new file mode 100644 index 0000000..9283b55 --- /dev/null +++ b/src/soc/nvidia/tegra132/power.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_POWER_H__ +#define __SOC_NVIDIA_TEGRA132_POWER_H__ + +// This function does not enable the external power to the rail, it enables +// the rail itself internal to the SOC. +void power_enable_cpu_rail(void); + +void power_ungate_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA132_POWER_H__ */ diff --git a/src/soc/nvidia/tegra132/sysctr.h b/src/soc/nvidia/tegra132/sysctr.h new file mode 100644 index 0000000..ea9746d --- /dev/null +++ b/src/soc/nvidia/tegra132/sysctr.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SYSCTR_H__ +#define __SOC_NVIDIA_TEGRA132_SYSCTR_H__ + +#include <stdint.h> + +enum { + SYSCTR_CNTCR_EN = 1 << 0, + SYSCTR_CNTCR_HDBG = 1 << 1, + SYSCTR_CNTCR_FCREQ = 1 << 8 +}; + +struct sysctr_regs { + uint32_t cntcr; + uint32_t cntsr; + uint32_t cntcv0; + uint32_t cntcv1; + uint8_t _rsv0[0x10]; + uint32_t cntfid0; + uint32_t cntfid1; + uint8_t _rsv1[0xfa8]; + uint32_t counterid4; + uint32_t counterid5; + uint32_t counterid6; + uint32_t counterid7; + uint32_t counterid0; + uint32_t counterid1; + uint32_t counterid2; + uint32_t counterid3; + uint32_t counterid8; + uint32_t counterid9; + uint32_t counterid10; + uint32_t counterid11; +}; +check_member(sysctr_regs, counterid11, 0xffc); + +#endif /* __SOC_NVIDIA_TEGRA132_SYSCTR_H__ */ diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c new file mode 100644 index 0000000..41a9c73 --- /dev/null +++ b/src/soc/nvidia/tegra132/uart.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <stdint.h> +#include <drivers/uart/uart8250reg.h> + +struct tegra132_uart { + union { + uint32_t thr; // Transmit holding register. + uint32_t rbr; // Receive buffer register. + uint32_t dll; // Divisor latch lsb. + }; + union { + uint32_t ier; // Interrupt enable register. + uint32_t dlm; // Divisor latch msb. + }; + union { + uint32_t iir; // Interrupt identification register. + uint32_t fcr; // FIFO control register. + }; + uint32_t lcr; // Line control register. + uint32_t mcr; // Modem control register. + uint32_t lsr; // Line status register. + uint32_t msr; // Modem status register. +} __attribute__ ((packed)); + +static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr); +static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr); + +static void tegra132_uart_init(struct tegra132_uart *uart_ptr) +{ + // Use a hardcoded divisor for now. + const unsigned divisor = 221; + const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 + + tegra132_uart_tx_flush(uart_ptr); + + // Disable interrupts. + write8(0, &uart_ptr->ier); + // Force DTR and RTS to high. + write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + // Set line configuration, access divisor latches. + write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + // Set the divisor. + write8(divisor & 0xff, &uart_ptr->dll); + write8((divisor >> 8) & 0xff, &uart_ptr->dlm); + // Hide the divisor latches. + write8(line_config, &uart_ptr->lcr); + // Enable FIFOs, and clear receive and transmit. + write8(UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | + UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr); +} + +static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) +{ + if (!tegra132_uart_tst_byte(uart_ptr)) + return 0; + return read8(&uart_ptr->rbr); +} + +static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data) +{ + while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); + write8(data, &uart_ptr->thr); +} + +static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr) +{ + while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT)); +} + +static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr) +{ + return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; +} + +uintptr_t uart_platform_base(int idx) +{ + //Default to UART A + unsigned int base = 0x70006000; + //UARTs A - E are mapped as index 0 - 4 + if ((idx < 5) && (idx >= 0)) { + if (idx != 1) { //not UART B + base += idx * 0x100; + } else { + base += 0x40; + } + } + return base; +} + +void uart_init(int idx) +{ + struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); + tegra132_uart_init(uart_ptr); +} + +unsigned char uart_rx_byte(int idx) +{ + struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); + return tegra132_uart_rx_byte(uart_ptr); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); + tegra132_uart_tx_byte(uart_ptr, data); +} + +void uart_tx_flush(int idx) +{ + struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); + tegra132_uart_tx_flush(uart_ptr); +} + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

1 0

New patch to review for coreboot: 01a6fe1 console: Clean up ARM CONFIG_CONSOLE_SERIAL
by Marc Jones 23 Feb '15

23 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8516 -gerrit commit 01a6fe1828bdd08e128cf6292672edff6197ab04 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Sun Feb 22 23:07:48 2015 -0700 console: Clean up ARM CONFIG_CONSOLE_SERIAL CONFIG_CONSOLE_SERIAL_UART has been updated to CONFIG_CONSOLE_SERIAL. There were a couple of instances of it that were missed in previous merges from the chromium tree. Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/arm64/early_console.c | 2 +- src/soc/nvidia/tegra124/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/early_console.c b/src/arch/arm64/early_console.c index aa287a3..8901f5d 100644 --- a/src/arch/arm64/early_console.c +++ b/src/arch/arm64/early_console.c @@ -32,7 +32,7 @@ void console_tx_byte(unsigned char byte) CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); } #endif -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 4b0ec96..7dee55b 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -26,7 +26,7 @@ verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c verstage-y += timer.c -verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +verstage-$(CONFIG_CONSOLE_SERIAL) += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/pinmux.c

1 0

Patch set updated for coreboot: 6d638a3 fsp_baytrail: Add new microcode for Bay Trail M
by Alexandru Gagniuc 23 Feb '15

23 Feb '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8399 -gerrit commit 6d638a33c641690d240410bf6a47787b801c739c Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 10:16:12 2015 +0100 fsp_baytrail: Add new microcode for Bay Trail M Add a new microcode for Bay Trail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has been added (I or M/D) which allows to use only the really needed microcode for a given CPU type. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 4 ++++ src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 15 ++++++++++----- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 6 +++++- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 639071a..e873450 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -51,6 +51,10 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT +config SOC_INTEL_FSP_BAYTRAIL_MD + bool + default n + config BOOTBLOCK_CPU_INIT string default "soc/intel/fsp_baytrail/bootblock/bootblock.c" diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 709ff92..cda9e26 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,12 +19,17 @@ unsigned microcode[] = { -/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ -#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 -#include "M0130679901.h" // M0130679: Baytrail I D0 +#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ + #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1 + #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3 + #include "M0130679901.h" // M0130679: Bay Trail I D0 +#else + /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */ + #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping +#endif - /* Dummy terminator */ + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec55314..2af2201 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,6 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + #define MICROCODE_REGION_LENGTH 0x30000 +#else + #define MICROCODE_REGION_LENGTH 0x10000 +#endif

1 0

Patch set updated for coreboot: 92e625a AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins
by Alexandru Gagniuc 23 Feb '15

23 Feb '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8495 -gerrit commit 92e625adb013ad74beaacfa9a430f146cedbbd15 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 11 17:22:23 2014 +0200 AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins Some GPIO pins are shared with PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, simply setting 0:14.4 disabled in the devicetree does not work here yet. Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb800/chip.h | 1 + src/southbridge/amd/cimx/sb800/late.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h index 2c2ce1e..f0ce075 100644 --- a/src/southbridge/amd/cimx/sb800/chip.h +++ b/src/southbridge/amd/cimx/sb800/chip.h @@ -35,6 +35,7 @@ struct southbridge_amd_cimx_sb800_config { u32 boot_switch_sata_ide : 1; + u32 disconnect_pcib : 1; u8 gpp_configuration; /* diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e017936..2125027 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -401,7 +401,7 @@ static void sb800_enable(device_t dev) * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins * to function as GPIO {GPIO 35:0}. */ - if (dev->enabled) + if (!sb_chip->disconnect_pcib && dev->enabled) RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); else RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);

1 0

Patch set updated for coreboot: 3e5c780 fsp_baytrail: Add I2C driver
by Werner Zeh 23 Feb '15

23 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8401 -gerrit commit 3e5c780377f9b0020378850dbfe040ff563e782a Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 13:02:34 2015 +0100 fsp_baytrail: Add I2C driver Add a driver wich can handle the internal I2C controllers of Baytrail SoC. This driver is not suitable for the SMBus controller. Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/baytrail/i2c.h | 136 +++++++++++++++ src/soc/intel/fsp_baytrail/i2c.c | 267 ++++++++++++++++++++++++++++++ 3 files changed, 404 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 3896e85..2dfb9cb 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -54,6 +54,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c +ramstage-y += i2c.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/baytrail/i2c.h b/src/soc/intel/fsp_baytrail/baytrail/i2c.h new file mode 100644 index 0000000..a89f091 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/i2c.h @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ +#define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> + +/* SMBus controller settings in PCI configuration space */ +#define I2C_PCI_VENDOR_ID 0x8086 +#define I2C0_PCI_DEV_ID 0x0f41 +#define I2C1_PCI_DEV_ID 0x0f42 +#define I2C2_PCI_DEV_ID 0x0f43 +#define I2C3_PCI_DEV_ID 0x0f44 +#define I2C4_PCI_DEV_ID 0x0f45 +#define I2C5_PCI_DEV_ID 0x0f46 +#define I2C6_PCI_DEV_ID 0x0f47 + +#define I2C0_MEM_BASE 0xd0921000 +#define I2C1_MEM_BASE 0xd0923000 +#define I2C2_MEM_BASE 0xd0925000 +#define I2C3_MEM_BASE 0xd0927000 +#define I2C4_MEM_BASE 0xd0929000 +#define I2C5_MEM_BASE 0xd092b000 +#define I2C6_MEM_BASE 0xd092d000 + +#define I2C_STANDARD_MODE 0x1 +#define I2C_FAST_MODE 0x2 + +/* Define relevant registers in PCI space */ +#define I2C_PCI_COMMAND 0x4 +#define I2C_PCI_STATUS 0x6 + +/* Define memory mapped registers */ +#define I2C_CTRL 0x0 +#define I2C_SLAVE_DISABLE 0x40 +#define I2C_RESTART_EN 0x20 +#define I2C_ADR_MODE 0x10 +#define I2C_SPEED_MASK 0x6 +#define I2C_STD_MODE 0x1 +#define I2C_FAST_MODE 0x2 +#define I2C_MASTER_ENABLE 0x1 + +#define I2C_TARGET_ADR 0x4 +#define I2C_TARGET_ADR_MASK 0x3ff + +#define I2C_DATA_CMD 0x10 +#define I2C_RESTART 0x400 +#define I2C_STOP 0x200 +#define I2C_RW_CMD 0x100 + +#define I2C_SS_SCL_HCNT 0x14 /* Counter for high period for 100 kHz SCL */ +#define I2C_SS_SCL_LCNT 0x18 /* Counter for low period for 100 kHz SCL */ +#define I2C_FS_SCL_HCNT 0x1c /* Counter for high period for 400 kHz SCL */ +#define I2C_FS_SCL_LCNT 0x20 /* Counter for low period for 400 kHz SCL */ + +#define I2C_INTR_STAT 0x2c /* Interrupt status register, read only */ +#define I2C_INTR_MASK 0x30 /* Interrupt mask register */ +#define I2C_RAW_INTR_STAT 0x34 /* Raw interrupt status, read only */ +#define I2C_START_DETECT 0x400 +#define I2C_STOP_DETECT 0x200 +#define I2C_ACTIVITY 0x100 +#define I2C_TX_ABORT 0x40 +#define I2C_RD_REQ 0x20 /* Read request in slave mode */ +#define I2C_TX_EMPTY 0x10 +#define I2C_TX_OVERFLOW 0x8 +#define I2C_RX_FULL 0x4 +#define I2C_RX_OVERFLOW 0x2 +#define I2C_RX_UNDERFLOW 0x1 + +#define I2C_RX_TL 0x38 /* Rx FIFO threshold level 0..255 */ +#define I2C_TX_TL 0x3c /* Tx FIFO threshold level 0..255 */ +#define I2C_CLR_INTR 0x40 /* Clear all events with a read */ +#define I2C_CLR_TX_ABRT 0x54 /* Clear TX-Abort event with a read */ + +/* There are a bunch of interrupt clearing registers now which are not used! */ +/* So proceed somewhat later with definition */ +#define I2C_ENABLE 0x6c /* 0: disable I2C controller, 1: enable */ +#define I2C_STATUS 0x70 +#define I2C_MST_ACTIVITY 0x20 /* Master FSM activity */ +#define I2C_RFF 0x10 /* Receive FIFO completely full */ +#define I2C_RFNE 0x8 /* Receive FIFO not empty */ +#define I2C_TFE 0x4 /* Transmit FIFO completely empty */ +#define I2C_TFNF 0x2 /* Transmit FIFO not full */ +#define I2C_ACTIVE 0x1 /* 1: I2C currently in operation */ + +#define I2C_TXFLR 0x74 /* Current transmit FIFO level */ +#define I2C_RXFLR 0x78 /* Current receive FIFO level */ +#define I2C_SDA_HOLD 0x7c /* Data hold time after SCL goes low */ +#define I2C_ABORT_SOURCE 0x80 +#define I2C_ARB_LOST 0x1000 /* Arbitration lost */ +#define I2C_MASTER_DIS 0x800 /* Master was disabled by user */ +#define I2C_10B_RD_NORSTRT 0x400 /* 10 bit address read and RESTART disabled */ +#define I2C_SBYTE_NORSTRT 0x200 /* START with RESTART disabled */ +#define I2C_START_ACKDET 0x80 /* START byte was acknowledged */ +#define I2C_TX_DATA_NOACK 0x8 /* TX data not acknowledged */ +#define I2C_10B_ADR2_NOACK 0x4 /* Second address byte in 10 bit mode NACK */ +#define I2C_10B_ADR1_NOACK 0x2 /* First address byte in 10 bit NACK */ +#define I2C_7B_ADDR_NACK 0x1 /* 7 bit address byte not acknowledged */ + +#define I2C_ENABLE_STATUS 0x9c + +/* Define some status and error values */ +#define I2C_ERR_INVALID_ADR 0x1000000 +#define I2C_ERR_TIMEOUT 0x2000000 +#define I2C_ERR_ABORT 0x4000000 +#define I2C_NO_ERROR 0x0000000 + + +#define I2C_TIMEOUT_US 2000 /* Use 2000 us as time */ + +/* Prototype section*/ +int i2c_init(unsigned bus); +int i2c_read(unsigned bus, unsigned chip, unsigned addr, uint8_t *buf, unsigned len); +int i2c_write(unsigned bus, unsigned chip, unsigned addr, const uint8_t *buf, unsigned len); + +#endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c new file mode 100644 index 0000000..700bba1 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include <baytrail/baytrail.h> +#include <baytrail/pci_devs.h> +#include <baytrail/iosf.h> +#include <delay.h> +#include <baytrail/i2c.h> + +/* Wait for the transmit FIFO till there is at least one slot empty. + * FIFO stall due to transmit abort will be checked and resolved + */ +static int wait_tx_fifo(char *base_adr) { + int i; + + if (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff) { + /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ + i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); + return I2C_ERR_ABORT | + (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + } + + /* Wait here for a free slot in TX-FIFO */ + i = I2C_TIMEOUT_US; + while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF)) + && (i)) { + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/* Wait for the receive FIFO till there is at least one valid entry to read. + * FIFO stall due to transmit abort will be checked and resolved + */ +static int wait_rx_fifo(char *base_adr) { + int i; + + if (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff) { + /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ + i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); + return I2C_ERR_ABORT | + (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + } + + /* Wait here for a received entry in RX-FIFO */ + i = I2C_TIMEOUT_US; + while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE)) + && (i)) { + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/* When there will be a fast switch between send and receive, one have + * to wait until the first operation is completely finished + * before starting the second operation + */ +static int wait_for_idle(char *base_adr) +{ + int i; + volatile int status; + + /* For IDLE, increase timeout by ten times */ + i = I2C_TIMEOUT_US * 10; + status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE))) && (i)) { + status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/** \brief Enables I2C-controller, sets up BAR and timing parameters + * @param bus Number of the I2C-controller to use (0...6) + * @return 0 on success, otherwise error code + */ +int i2c_init(unsigned bus) +{ + device_t dev; + int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE, + I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, + I2C6_MEM_BASE}; + char *base_ptr = (char*)base_adr[bus]; + /* Ensure the desired device is valid */ + if (bus > 6) { + printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n"); + return 1; + } + + /* Set the I2C-device the user wants to use */ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + + /* Ensure we have the right PCI device */ + if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || + (pci_read_config16(dev, 0x2) != (I2C0_PCI_DEV_ID + bus))) { + printk(BIOS_ERR, "I2C: Controller %d not found!\n", bus); + return 2; + } + + /* Set memory base */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, (int)base_ptr); + + /* Enable memory space */ + pci_write_config32(dev, PCI_COMMAND, + (pci_read_config32(dev, PCI_COMMAND) | 0x2)); + + /* Set up some settings of I2C controller */ + *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN | + (I2C_STANDARD_MODE << 1) | + I2C_MASTER_ENABLE); + /* Adjust frequency for standard mode to 100 kHz */ + /* The counter value can be computed by N=100MHz/2/I2C_CLK */ + /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */ + *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; + *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + /* For 400 kHz, the counter value is 0x7d */ + *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; + *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + + /* Enable the I2C controller for operation */ + *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + + printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); + return I2C_NO_ERROR; +} + +/** \brief Read bytes over I2C-Bus from a slave. This function tries only one + * time to transmit data. In case of an error (abort) error code is + * returned. Retransmission has to be done from caller! + * @param bus Number of the I2C-controller to use (0...6) + * @param chip 7 Bit of the slave address on I2C bus + * @param addr Address inside slave where to read from + * @param *buf Pointer to the buffer where to store read data + * @param len Number of bytes to read + * @return I2C_NO_ERROR when read was successful, otherwise error code + */ +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + uint8_t *buf, unsigned len) +{ + int i = 0; + char *base_ptr = NULL; + device_t dev; + unsigned int val; + int stat; + + /* Get base address of desired I2C-controller */ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (base_ptr == NULL) { + printk(BIOS_INFO, "I2C: Invalid Base address\n"); + return I2C_ERR_INVALID_ADR; + } + + /* Ensure I2C controller is not active before setting slave address */ + stat = wait_for_idle(base_ptr); + if (stat != I2C_NO_ERROR) + return stat; + /* Now we can program the desired slave address and start transfer */ + *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + /* Send address inside slave to read from */ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + + /* For the next byte we need a repeated start condition */ + val = I2C_RW_CMD | I2C_RESTART; + /* Now we can read desired amount of data over I2C */ + for (i = 0; i < len; i++) { + /* A read is initiated by writing dummy data to the DATA-register */ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + stat = wait_rx_fifo(base_ptr); + if (stat) + return stat; + buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + val = I2C_RW_CMD; + if (i == (len - 2)) { + /* For the last byte we need a stop condition to be generated */ + val |= I2C_STOP; + } + } + return I2C_NO_ERROR; +} + +/** \brief Write bytes over I2C-Bus from a slave. This function tries only one + * time to transmit data. In case of an error (abort) error code is + * returned. Retransmission has to be done from caller! + * @param bus Number of the I2C-controller to use (0...6) + * @param chip 7 Bit of the slave address on I2C bus + * @param addr Address inside slave where to write to + * @param *buf Pointer to the buffer where data to write is stored + * @param len Number of bytes to write + * @return I2C_NO_ERROR when read was successful, otherwise error code + */ +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + const uint8_t *buf, unsigned len) +{ + int i; + char *base_ptr; + device_t dev; + unsigned int val; + int stat; + + /* Get base address of desired I2C-controller */ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (base_ptr == NULL) { + return I2C_ERR_INVALID_ADR; + } + + /* Ensure I2C controller is not active yet */ + stat = wait_for_idle(base_ptr); + if (stat) { + return stat; + } + /* Program slave address to use for this transfer */ + *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + + /* Send address inside slave to write data to */ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + + for (i = 0; i < len; i++) { + val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits */ + if (i == (len - 1)) { + /* For the last byte we need a stop condition */ + val |= I2C_STOP; + } + stat = wait_tx_fifo(base_ptr); + if (stat) { + return stat; + } + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + } + return I2C_NO_ERROR; +}

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Patch set updated for coreboot: ec3b02d drivers/pc80/mc146818rtc: Enable RTC reset on power loss
by Werner Zeh 23 Feb '15

23 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8373 -gerrit commit ec3b02d6b0bf49b47aab73f8469f1492d77e3792 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Feb 9 08:17:40 2015 +0100 drivers/pc80/mc146818rtc: Enable RTC reset on power loss If function cmos_init() was called with parameter invalid set, this indicates, that the caller has found a power loss event in the RTC registers. In this case, we need to load the default date and time because it can be corrupted. Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/pc80/mc146818rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index fe669ca..4f034a2 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -86,7 +86,7 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) #ifndef __SMM__ void cmos_init(bool invalid) { - bool cmos_invalid = false; + bool cmos_invalid = invalid; bool checksum_invalid = false; bool clear_cmos; size_t i;

1 0

Patch set updated for coreboot: 91b7537 drivers/intel/i210: Add new driver for Intel i210 MACPHY
by Werner Zeh 23 Feb '15

23 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8404 -gerrit commit 91b753723a9e9831e9e3d599ca62c7895241c233 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Feb 13 12:18:58 2015 +0100 drivers/intel/i210: Add new driver for Intel i210 MACPHY Add a new driver for Intel i210 MACPHY with the goal to update the MAC address in i210 if it is found during PCI scan. Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/i210/Kconfig | 3 + src/drivers/intel/i210/Makefile.inc | 1 + src/drivers/intel/i210/i210.c | 243 ++++++++++++++++++++++++++++++++++++ src/drivers/intel/i210/i210.h | 45 +++++++ 6 files changed, 294 insertions(+) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 9954f31..511cf5c 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -18,3 +18,4 @@ ## source src/drivers/intel/gma/Kconfig +source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index 7bc6dd5..dba81b5 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += gma subdirs-y += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP) += fsp +subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/i210/Kconfig b/src/drivers/intel/i210/Kconfig new file mode 100644 index 0000000..0191169 --- /dev/null +++ b/src/drivers/intel/i210/Kconfig @@ -0,0 +1,3 @@ +config DRIVER_INTEL_I210 + bool + default n diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc new file mode 100644 index 0000000..a1f15de --- /dev/null +++ b/src/drivers/intel/i210/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += i210.c \ No newline at end of file diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c new file mode 100644 index 0000000..cdb76e4 --- /dev/null +++ b/src/drivers/intel/i210/i210.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i210.h" +#include <device/device.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <string.h> +#include <types.h> +#include <delay.h> + +/* We need one function we can call to get a MAC address to use */ +/* This function can be coded somewhere else but must exist. */ +extern enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); + +/* This is a private function to wait for a bit mask in a given register */ +/* To avoid endless loops, a time-out is implemented here. */ +static int wait_done(u32* reg, u32 mask) +{ + u32 timeout = I210_POLL_TIMEOUT_US; + + while (!(*reg & mask)) { + udelay(1); + if (!--timeout) + return I210_NOT_READY; + } + return I210_SUCCESS; +} + +/** \brief This function can read the configuration space of the MACPHY + * For this purpose, the EEPROM interface is used. No direct access + * to the flash memory will be done. + * @param *dev Pointer to the PCI device of this MACPHY + * @param address Address inside the flash where reading will start + * @param count Number of words (16 bit values) to read + * @param *buffer Pointer to the buffer where to store read data + * @return void I210_NO_ERROR or an error code + */ +static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +{ + u32 bar; + u32 *eeprd; + u32 i; + + /* Get the BAR to memory mapped space*/ + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if ((!bar) || ((address + count) > 0x40)) + return I210_INVALID_PARAM; + eeprd = (u32*)(bar + I210_REG_EEREAD); + /* Prior to start ensure flash interface is ready by checking DONE-bit */ + if (wait_done(eeprd, I210_DONE)) + return I210_NOT_READY; + + /*OK, interface is ready, we can use it now */ + for (i = 0; i < count; i++) { + /* To start a read cycle write desired address in bits 12..2 */ + *eeprd = ((address + i) << 2) & 0x1FFC; + /* Wait until read is done */ + if (wait_done(eeprd, I210_DONE)) + return I210_READ_ERROR; + /* Here, we can read back desired word in bits 31..16 */ + buffer[i] = (*eeprd & 0xffff0000) >> 16; + } + return I210_SUCCESS; +} + +/** \brief This function computes the checksum for the configuration space. + * The address range for the checksum is 0x00..0x3e. + * @param *dev Pointer to the PCI device of this MACPHY + * @param *checksum Pointer to the buffer where to store the checksum + * @return void I210_NO_ERROR or an error code + */ +static u32 compute_checksum(struct device *dev, u16 *checksum) +{ + u16 eep_data[0x40]; + u32 i; + + /* First read back data to compute the checksum for */ + if (read_flash(dev, 0, 0x3f, eep_data)) + return I210_READ_ERROR; + /* The checksum is computed in that way that after summarize all the */ + /* data from word address 0 to 0x3f the result is 0xBABA. */ + *checksum = 0; + for (i = 0; i < 0x3f; i++) + *checksum += eep_data[i]; + *checksum = I210_TARGET_CHECKSUM - *checksum; + return I210_SUCCESS; +} + +/** \brief This function can write the configuration space of the MACPHY + * For this purpose, the EEPROM interface is used. No direct access + * to the flash memory will be done. This function will update + * the checksum after a value was changed. + * @param *dev Pointer to the PCI device of this MACPHY + * @param address Address inside the flash where writing will start + * @param count Number of words (16 bit values) to write + * @param *buffer Pointer to the buffer where data to write is stored in + * @return void I210_NO_ERROR or an error code + */ +static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +{ + u32 bar; + u32 *eepwr; + u32 *eectrl; + u16 checksum; + u32 i; + + /* Get the BAR to memory mapped space */ + bar = pci_read_config32(dev, 0x10); + if ((!bar) || ((address + count) > 0x40)) + return I210_INVALID_PARAM; + eepwr = (u32*)(bar + I210_REG_EEWRITE); + eectrl = (u32*)(bar + I210_REG_EECTRL); + /* Prior to start ensure flash interface is ready by checking DONE-bit */ + if (wait_done(eepwr, I210_DONE)) + return I210_NOT_READY; + + /* OK, interface is ready, we can use it now */ + for (i = 0; i < count; i++) { + /* To start a write cycle write desired address in bits 12..2 */ + /* and data to write in bits 31..16 into EEWRITE-register */ + *eepwr = ((((address + i) << 2) & 0x1FFC) | (buffer[i] << 16)); + /* Wait until write is done */ + if (wait_done(eepwr, I210_DONE)) + return I210_WRITE_ERROR; + } + /* Since we have modified data, we need to update the checksum */ + if (compute_checksum(dev, &checksum)) + return I210_CHECKSUM_ERROR; + *eepwr = (0x3f << 2) | checksum << 16; + if (wait_done(eepwr, I210_DONE)) + return I210_WRITE_ERROR; + /* Up to now, desired data was written into shadowed RAM. We now need */ + /* to perform a flash cycle to bring the shadowed RAM into flash memory. */ + /* To start a flash cycle we need to set FLUPD-bit and wait for FLDONE. */ + *eectrl = *eectrl | I210_FLUPD; + if (wait_done(eectrl, I210_FLUDONE)) + return I210_FLASH_UPDATE_ERROR; + return I210_SUCCESS; +} + +/** \brief This function can read the MAC address out of the MACPHY + * @param *dev Pointer to the PCI device of this MACPHY + * @param *MACAdr Pointer to the buffer where to store read MAC address + * @return void I210_NO_ERROR or an error code + */ +static u32 read_mac_adr(struct device *dev, u8 *mac_adr) +{ + u16 adr[3]; + if (!dev || !mac_adr) + return I210_INVALID_PARAM; + if (read_flash(dev, 0, 3, adr)) + return I210_READ_ERROR; + /* Copy the address into destination. This is done because of */ + /* possible not matching alignment for destination to u16 boundary. */ + memcpy(mac_adr, (u8*)adr, 6); + return I210_SUCCESS; +} + +/** \brief This function can write the MAC address to the MACPHY + * @param *dev Pointer to the PCI device of this MACPHY + * @param *MACAdr Pointer to the buffer where the desired MAC address is + * @return void I210_NO_ERROR or an error code + */ +static u32 write_mac_adr(struct device *dev, u8 *mac_adr) +{ + u16 adr[3]; + if (!dev || !mac_adr) + return I210_INVALID_PARAM; + /* Copy desired address into a local buffer to avoid alignment issues */ + memcpy((u8*)adr, mac_adr, 6); + return write_flash(dev, 0, 3, adr); +} + +/** \brief This function is the driver entry point for the init phase + * of the PCI bus allocator. It will program a MAC address + * into the MACPHY. + * @param *dev Pointer to the used PCI device + * @return void Nothing is given back + */ +static void init(struct device *dev) +{ + u8 cur_adr[6]; + u8 adr_to_set[6]; + enum cb_err status; + + /*Check first whether there is a valid MAC address available */ + status = mainboard_get_mac_address(dev->bus->subordinate, + dev->path.pci.devfn, adr_to_set); + if (status != CB_SUCCESS) { + printk(BIOS_ERR, "I210: No valid MAC address found\n"); + return; + } + /* Before we will write a new address, check the existing one */ + if (read_mac_adr(dev, cur_adr)) { + printk(BIOS_ERR, "I210: Not able to read MAC address.\n"); + return; + } + if (memcmp(cur_adr, adr_to_set, 6)) { + if (write_mac_adr(dev, adr_to_set)) + printk(BIOS_ERR, "I210: Error setting MAC address\n"); + else + printk(BIOS_INFO, "I210: MAC address changed.\n"); + } else { + printk(BIOS_INFO, "I210: MAC address is up to date.\n"); + } + return; +} + +static struct device_operations i210_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static const unsigned short i210_device_ids[] = { 0x1538, 0x1533, 0 }; + +static const struct pci_driver i210_driver __pci_driver = { + .ops = &i210_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = i210_device_ids, +}; diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h new file mode 100644 index 0000000..b4f18ec --- /dev/null +++ b/src/drivers/intel/i210/i210.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _INTEL_I210_H_ +#define _INTEL_I210_H_ + +#define I210_PCI_MEM_BAR_OFFSET 0x10 +#define I210_REG_EECTRL 0x12010 /* Offset for EEPROM control reg */ +#define I210_FLUPD 0x800000 /* Start flash update bit */ +#define I210_FLUDONE 0x4000000 /* Flash update done indicator */ +#define I210_REG_EEREAD 0x12014 /* Offset for EEPROM read reg */ +#define I210_REG_EEWRITE 0x12018 /* Offset for EEPROM write reg */ +#define I210_CMDV 0x01 /* command valid bit */ +#define I210_DONE 0x02 /* command done bit */ +#define I210_TARGET_CHECKSUM 0xBABA /* resulting checksum */ + + +/*define some other useful values here */ +#define I210_POLL_TIMEOUT_US 300000 /* 300 ms */ +/*Define some error states here*/ +#define I210_SUCCESS 0x00000000 +#define I210_INVALID_PARAM 0x00000001 +#define I210_NOT_READY 0x00000002 +#define I210_READ_ERROR 0x00000004 +#define I210_WRITE_ERROR 0x00000008 +#define I210_CHECKSUM_ERROR 0x00000010 +#define I210_FLASH_UPDATE_ERROR 0x00000020 + +#endif /* _INTEL_I210_H_ */

1 0

Patch set updated for coreboot: e4f776b mainboard/siemens/mc_tcu3: Add new mainboard.
by Werner Zeh 23 Feb '15

23 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8430 -gerrit commit e4f776bcfa42285d7a6e095db9f68041048d81f9 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Feb 12 12:40:15 2015 +0100 mainboard/siemens/mc_tcu3: Add new mainboard. This mainboard is based on Intel's Bayleybay board which uses Bay Trail CPU with Intel FSP. It has one USB3.0 interface, 4 USB2.0 interfaces, up to two Ethernet ports and a LVDS connection for LCD panels. The board is equipped with 512 MB of DDR3 in a memory down configuration. This board boots into Ubuntu/Lubuntu 14.10 using SeaBIOS, but other OSes should work as well (but are not tested). It has a version.hex file which is needed for our OS and has no hardware functionality. Change-Id: I94401bbd1d61ec69703de38ae1bc97969c5d979e Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/Kconfig | 4 + src/mainboard/siemens/mc_tcu3/Kconfig | 75 +++++++ src/mainboard/siemens/mc_tcu3/Makefile.inc | 51 +++++ src/mainboard/siemens/mc_tcu3/acpi/ec.asl | 0 src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl | 25 +++ src/mainboard/siemens/mc_tcu3/acpi/superio.asl | 0 src/mainboard/siemens/mc_tcu3/acpi_tables.c | 254 +++++++++++++++++++++++ src/mainboard/siemens/mc_tcu3/board_info.txt | 4 + src/mainboard/siemens/mc_tcu3/cmos.layout | 132 ++++++++++++ src/mainboard/siemens/mc_tcu3/devicetree.cb | 82 ++++++++ src/mainboard/siemens/mc_tcu3/dsdt.asl | 57 +++++ src/mainboard/siemens/mc_tcu3/fadt.c | 35 ++++ src/mainboard/siemens/mc_tcu3/gpio.c | 224 ++++++++++++++++++++ src/mainboard/siemens/mc_tcu3/hwinfo.hex | Bin 0 -> 997 bytes src/mainboard/siemens/mc_tcu3/hwinfo10.hex | Bin 0 -> 485 bytes src/mainboard/siemens/mc_tcu3/hwinfo12.hex | Bin 0 -> 485 bytes src/mainboard/siemens/mc_tcu3/hwinfo15.hex | Bin 0 -> 485 bytes src/mainboard/siemens/mc_tcu3/hwinfo19.hex | Bin 0 -> 485 bytes src/mainboard/siemens/mc_tcu3/irqroute.c | 22 ++ src/mainboard/siemens/mc_tcu3/irqroute.h | 77 +++++++ src/mainboard/siemens/mc_tcu3/lcd_panel.c | 94 +++++++++ src/mainboard/siemens/mc_tcu3/lcd_panel.h | 39 ++++ src/mainboard/siemens/mc_tcu3/mainboard.c | 50 +++++ src/mainboard/siemens/mc_tcu3/modhwinfo.c | 150 +++++++++++++ src/mainboard/siemens/mc_tcu3/modhwinfo.h | 170 +++++++++++++++ src/mainboard/siemens/mc_tcu3/ptn3460.c | 181 ++++++++++++++++ src/mainboard/siemens/mc_tcu3/ptn3460.h | 78 +++++++ src/mainboard/siemens/mc_tcu3/romstage.c | 208 +++++++++++++++++++ src/mainboard/siemens/mc_tcu3/thermal.h | 33 +++ src/mainboard/siemens/mc_tcu3/version.hex | 3 + 30 files changed, 2048 insertions(+) diff --git a/src/mainboard/siemens/Kconfig b/src/mainboard/siemens/Kconfig index f03f822..e25cfa5 100644 --- a/src/mainboard/siemens/Kconfig +++ b/src/mainboard/siemens/Kconfig @@ -6,9 +6,13 @@ choice config BOARD_SIEMENS_SITEMP_G1P1 bool "MB SITEMP-G1 (U1P0/U1P1)" +config BOARD_SIEMENS_MC_TCU3 + bool "MB TCU3" + endchoice source "src/mainboard/siemens/sitemp_g1p1/Kconfig" +source "src/mainboard/siemens/mc_tcu3/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig new file mode 100644 index 0000000..2a1de0f --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -0,0 +1,75 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_SIEMENS_MC_TCU3 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select OVERRIDE_MRC_CACHE_LOC + select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT + select ENABLE_BUILTIN_COM1 + select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT + select ENABLE_FSP_FAST_BOOT + select TSC_MONOTONIC_TIMER + select DRIVER_INTEL_I210 + select SOC_INTEL_FSP_BAYTRAIL_MD + +config MAINBOARD_DIR + string + default "siemens/mc_tcu3" + +config INCLUDE_ME + bool + default n + +config MAINBOARD_PART_NUMBER + string + default "MC_TCU3 (FSP)" + + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x1000000 + +config MRC_CACHE_LOC_OVERRIDE + hex + default 0xfff80000 + depends on ENABLE_FSP_FAST_BOOT + +config CBFS_SIZE + hex + default 0x00e00000 + +config FSP_PACKAGE_DEFAULT + bool "Configure defaults for the Intel FSP package" + default n + +config VGA_BIOS + bool + default y if FSP_PACKAGE_DEFAULT + +endif # BOARD_SIEMENS_MC_TCU3 diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc new file mode 100644 index 0000000..91d4bd2 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += modhwinfo.c + +ramstage-y += gpio.c +ramstage-y += irqroute.c +ramstage-y += modhwinfo.c +ramstage-y += lcd_panel.c +ramstage-y += ptn3460.c + +cbfs-files-y += hwinfo.hex +hwinfo.hex-file := hwinfo.hex +hwinfo.hex-type := 0x50 +hwinfo.hex-align := 0x1000 + +cbfs-files-y += version.hex +version.hex-file := version.hex +version.hex-type := 0x50 + +cbfs-files-y += hwinfo10.hex +hwinfo10.hex-file := hwinfo10.hex +hwinfo10.hex-type := 0x50 + +cbfs-files-y += hwinfo12.hex +hwinfo12.hex-file := hwinfo12.hex +hwinfo12.hex-type := 0x50 + +cbfs-files-y += hwinfo15.hex +hwinfo15.hex-file := hwinfo15.hex +hwinfo15.hex-type := 0x50 + +cbfs-files-y += hwinfo19.hex +hwinfo19.hex-file := hwinfo19.hex +hwinfo19.hex-type := 0x50 diff --git a/src/mainboard/siemens/mc_tcu3/acpi/ec.asl b/src/mainboard/siemens/mc_tcu3/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl b/src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl new file mode 100644 index 0000000..c1884c5 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/siemens/mc_tcu3/acpi/superio.asl b/src/mainboard/siemens/mc_tcu3/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/siemens/mc_tcu3/acpi_tables.c b/src/mainboard/siemens/mc_tcu3/acpi_tables.c new file mode 100644 index 0000000..5f81e26 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/acpi_tables.c @@ -0,0 +1,254 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> +#include <baytrail/iomap.h> + + +extern const unsigned char AmlCode[]; + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 0; + + /* Enable DPTF */ + gnvs->dpte = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, + facs->length); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + ALIGN_CURRENT; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, + dsdt->length); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, + fadt->header.length); + + /* + * We explicitly add these tables later on: + */ + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, + hpet->header.length); + + /* If we want to use HPET Timers Linux wants an MADT */ + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, + madt->header.length); + + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, + mcfg->header.length); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ +#if CONFIG_HAVE_SMI_HANDLER + smm_setup_structures(gnvs, NULL, NULL); +#endif + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + ssdt = (acpi_header_t *)current; + memset(ssdt, 0, sizeof(acpi_header_t)); + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, + ssdt->length); + ALIGN_CURRENT; + } else { + ssdt = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); + } + + ssdt2 = (acpi_header_t *)current; + memset(ssdt2, 0, sizeof(acpi_header_t)); + acpi_create_serialio_ssdt(ssdt2); + if (ssdt2->length) { + current += ssdt2->length; + acpi_add_table(rsdp, ssdt2); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, + ssdt2->length); + ALIGN_CURRENT; + } else { + ssdt2 = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); + } + + printk(BIOS_DEBUG, "current = %lx\n", current); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/siemens/mc_tcu3/board_info.txt b/src/mainboard/siemens/mc_tcu3/board_info.txt new file mode 100644 index 0000000..264dc3e --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/board_info.txt @@ -0,0 +1,4 @@ +Board name: TCU3 +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/siemens/mc_tcu3/cmos.layout b/src/mainboard/siemens/mc_tcu3/cmos.layout new file mode 100644 index 0000000..115dcb5 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/cmos.layout @@ -0,0 +1,132 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/siemens/mc_tcu3/devicetree.cb b/src/mainboard/siemens/mc_tcu3/devicetree.cb new file mode 100644 index 0000000..c00c804 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/devicetree.cb @@ -0,0 +1,82 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/intel/fsp_baytrail + + #### ACPI Register Settings #### + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + + #### FSP register settings #### + register "PcdSataMode" = "SATA_MODE_AHCI" + register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" + register "PcdGttSize" = "GTT_SIZE_DEFAULT" + register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router + device pci 02.0 on end # 8086 0F31 - GFX + device pci 03.0 off end # 8086 0F38 - MIPI - camera interface + + device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time + device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins) + device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins) + device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) + device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 off end # 8086 0F28 - LP Engine Audio + device pci 16.0 off end # 8086 0F37 - OTG controller + device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time + device pci 18.0 on end # 8086 0F40 - SIO - DMA + device pci 18.1 on end # 8086 0F41 - I2C Port 1 + device pci 18.2 on end # 8086 0F42 - I2C Port 2 + device pci 18.3 on end # 8086 0F43 - I2C Port 3 + device pci 18.4 on end # 8086 0F44 - I2C Port 4 + device pci 18.5 on end # 8086 0F45 - I2C Port 5 + device pci 18.6 on end # 8086 0F46 - I2C Port 6 + device pci 18.7 on end # 8086 0F47 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on # 8086 0F48 - PCIe Root Port 1 (x4 slot) + device pci 0.0 on end # 8086 1538 - Intel i210 MACPHY + end + device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot) + device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot) + device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot) + device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time + device pci 1e.0 on end # 8086 0F06 - SIO - DMA + device pci 1e.1 on end # 8086 0F08 - PWM 1 + device pci 1e.2 on end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 0F0A - HSUART 1 + device pci 1e.4 on end # 8086 0F0C - HSUART 2 + device pci 1e.5 on end # 8086 0F0E - SPI + device pci 1f.0 on end # 8086 0F1C - LPC bridge + device pci 1f.3 on end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/siemens/mc_tcu3/dsdt.asl b/src/mainboard/siemens/mc_tcu3/dsdt.asl new file mode 100644 index 0000000..cb2a4da --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/siemens/mc_tcu3/fadt.c b/src/mainboard/siemens/mc_tcu3/fadt.c new file mode 100644 index 0000000..29d0c1d --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/fadt.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <baytrail/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt,facs,dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c new file mode 100644 index 0000000..4306a23 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> +#include "irqroute.h" + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO 0 */ + GPIO_FUNC2, /* GPIO 1 */ + GPIO_FUNC2, /* GPIO 2 */ + GPIO_FUNC2, /* GPIO 3 */ + GPIO_FUNC2, /* GPIO 4 */ + GPIO_FUNC2, /* GPIO 5 */ + GPIO_FUNC2, /* GPIO 6 */ + GPIO_FUNC2, /* GPIO 7 */ + GPIO_FUNC2, /* GPIO 8 */ + GPIO_FUNC2, /* GPIO 9 */ + GPIO_FUNC2, /* GPIO 10 */ + GPIO_FUNC2, /* GPIO 11 */ + GPIO_FUNC2, /* GPIO 12 */ + GPIO_FUNC2, /* GPIO 13 */ + GPIO_FUNC2, /* GPIO 14 */ + GPIO_FUNC2, /* GPIO 15 */ + GPIO_FUNC2, /* GPIO 16 */ + GPIO_FUNC2, /* GPIO 17 */ + GPIO_FUNC2, /* GPIO 18 */ + GPIO_FUNC2, /* GPIO 19 */ + GPIO_FUNC2, /* GPIO 20 */ + GPIO_FUNC2, /* GPIO 21 */ + GPIO_FUNC2, /* GPIO 22 */ + GPIO_FUNC2, /* GPIO 23 */ + GPIO_FUNC2, /* GPIO 24 */ + GPIO_FUNC2, /* GPIO 25 */ + GPIO_FUNC2, /* GPIO 26 */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] SATA_GP[0] .*/ + GPIO_FUNC2, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] .*/ + GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# */ + GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */ + GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */ + GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */ + GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */ + GPIO_NC, /* GPIO_S0_SC[007] RESERVED SD3_WP */ + GPIO_FUNC2, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# */ + GPIO_FUNC2, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC */ + GPIO_FUNC2, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */ + GPIO_FUNC2, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */ + GPIO_FUNC2, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] */ + GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] */ + GPIO_DEFAULT, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED */ + GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED */ + GPIO_NC, /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */ + GPIO_NC, /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */ + GPIO_NC, /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */ + GPIO_NC, /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */ + GPIO_NC, /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */ + GPIO_NC, /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */ + GPIO_NC, /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */ + GPIO_NC, /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */ + GPIO_NC, /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */ + GPIO_NC, /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */ + GPIO_NC, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */ + GPIO_FUNC1, /* GPIO_S0_SC[027] SD2_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[028] SD2_D[0] */ + GPIO_FUNC1, /* GPIO_S0_SC[029] SD2_D[1] */ + GPIO_FUNC1, /* GPIO_S0_SC[030] SD2_D[2] */ + GPIO_FUNC1, /* GPIO_S0_SC[031] SD2_D[3]_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[032] SD2_CMD */ + GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK */ + GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] */ + GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] */ + GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] */ + GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] */ + GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# */ + GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD */ + GPIO_NC, /* GPIO_S0_SC[040] SD3_1P8EN */ + GPIO_NC, /* GPIO_S0_SC[041] SD3_PWREN# */ + GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] */ + GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] */ + GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] */ + GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] */ + GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# */ + GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] */ + GPIO_FUNC1, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] */ + GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */ + GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ */ + GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# */ + GPIO_FUNC1, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED */ + GPIO_OUT_HIGH, /* GPIO_S0_SC[055] RESERVED */ + GPIO_FUNC0, /* GPIO_S0_SC[056] RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD */ + GPIO_OUT_LOW, /* GPIO_S0_SC[058] RESERVED */ + GPIO_OUT_LOW, /* GPIO_S0_SC[059] RESERVED */ + GPIO_OUT_LOW, /* GPIO_S0_SC[060] RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] SIO_SPI_CS# */ + GPIO_FUNC1, /* GPIO_S0_SC[067] SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# */ + GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# */ + GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[075] SIO_UART2_TXD */ + GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# */ + GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# */ + GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[080] SIO_I2C1_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED */ + GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[084] SIO_I2C3_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[085] SIO_I2C3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[086] SIO_I2C4_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[087] SIO_I2C4_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[088] SIO_I2C5_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[089] SIO_I2C5_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */ + GPIO_FUNC1, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */ + GPIO_FUNC1, /* RESERVED GPIO_S0_SC[092] */ + GPIO_FUNC1, /* RESERVED GPIO_S0_SC[093] */ + GPIO_FUNC1, /* GPIO_S0_SC[094] SIO_PWM[0] */ + GPIO_FUNC1, /* GPIO_S0_SC[095] SIO_PWM[1] */ + GPIO_FUNC1, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] */ + GPIO_FUNC1, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] */ + GPIO_FUNC1, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] */ + GPIO_FUNC1, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] */ + GPIO_FUNC1, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] */ + GPIO_DEFAULT, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_INPUT_PD_10K, /* GPIO_S5[00] RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */ + GPIO_INPUT_PD_10K, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */ + GPIO_INPUT_PD_10K, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */ + GPIO_INPUT_PD_10K, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ + GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ + GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */ + GPIO_INPUT_PU_10K, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */ + GPIO_DEFAULT, /* PMC_SUSCLK[0] GPIO_S5[12] - - */ + GPIO_DEFAULT, /* RESERVED GPIO_S5[13] - - */ + GPIO_DEFAULT, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - */ + GPIO_DEFAULT, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - */ + GPIO_DEFAULT, /* PMC_PWRBTN# GPIO_S5[16] - - */ + GPIO_DEFAULT, /* RESERVED GPIO_S5[17] - - */ + GPIO_DEFAULT, /* PMC_SUS_STAT# GPIO_S5[18] - - */ + GPIO_DEFAULT, /* USB_OC[0]# GPIO_S5[19] - - */ + GPIO_DEFAULT, /* USB_OC[1]# GPIO_S5[20] - - */ + GPIO_DEFAULT, /* PCU_SPI_CS[1]# GPIO_S5[21] - */ + GPIO_DEFAULT, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[27] RESERVED RESERVED ESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ + GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED */ + GPIO_INPUT_PD_10K, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED */ + GPIO_INPUT_PD_20K, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED */ + GPIO_INPUT_PD_20K, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED */ + GPIO_INPUT_PD_20K, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED */ + GPIO_INPUT_PD_20K, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex new file mode 100644 index 0000000..ce7fc07 Binary files /dev/null and b/src/mainboard/siemens/mc_tcu3/hwinfo.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo10.hex b/src/mainboard/siemens/mc_tcu3/hwinfo10.hex new file mode 100644 index 0000000..390c6b4 Binary files /dev/null and b/src/mainboard/siemens/mc_tcu3/hwinfo10.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo12.hex b/src/mainboard/siemens/mc_tcu3/hwinfo12.hex new file mode 100644 index 0000000..471af4f Binary files /dev/null and b/src/mainboard/siemens/mc_tcu3/hwinfo12.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo15.hex b/src/mainboard/siemens/mc_tcu3/hwinfo15.hex new file mode 100644 index 0000000..4cbbe5b Binary files /dev/null and b/src/mainboard/siemens/mc_tcu3/hwinfo15.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo19.hex b/src/mainboard/siemens/mc_tcu3/hwinfo19.hex new file mode 100644 index 0000000..f8510fc Binary files /dev/null and b/src/mainboard/siemens/mc_tcu3/hwinfo19.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.c b/src/mainboard/siemens/mc_tcu3/irqroute.c new file mode 100644 index 0000000..552be8f --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/irqroute.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h new file mode 100644 index 0000000..08552c5 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/irqroute.h @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 4), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.c b/src/mainboard/siemens/mc_tcu3/lcd_panel.c new file mode 100644 index 0000000..1dc429e --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include "modhwinfo.h" +#include "baytrail/gpio.h" +#include "lcd_panel.h" +#include "ptn3460.h" + +/** \brief Reads GPIOs used for LCD panel encoding and returns the 4 bit value + * @param no parameters + * @return LCD panel type encoded in 4 bits + */ +u8 get_lcd_panel_type(void) +{ + u8 lcd_type_gpio; + + lcd_type_gpio = ((read_ssus_gpio(LCD_TYPE_GPIO_BIT3) << 3) | + (read_ssus_gpio(LCD_TYPE_GPIO_BIT2) << 2) | + (read_ssus_gpio(LCD_TYPE_GPIO_BIT1) << 1) | + (read_ssus_gpio(LCD_TYPE_GPIO_BIT0))); + /* There is an inverter in this signals so we need to invert them as well */ + return ((~lcd_type_gpio) & 0x0f); +} + +/** \brief Setup LCD panel + * @param no parameters + * @return 0 on success otherwise error value + */ +int setup_lcd_panel(void) +{ + u8 lcd_type; + int status; + struct edidinfo *eib = NULL; + struct shortinfo *sib = NULL; + char blockname[33]; + + lcd_type = get_lcd_panel_type(); + printk(BIOS_INFO, "LCD: Found panel type %d\n", lcd_type); + switch (lcd_type) { + case LCD_PANEL_TYPE_10_INCH: + strcpy(blockname, "hwinfo10.hex"); + break; + case LCD_PANEL_TYPE_12_INCH: + strcpy(blockname, "hwinfo12.hex"); + break; + case LCD_PANEL_TYPE_15_INCH: + strcpy(blockname, "hwinfo15.hex"); + break; + case LCD_PANEL_TYPE_19_INCH: + strcpy(blockname, "hwinfo19.hex"); + break; + case LCD_PANEL_TYPE_EDID: + strcpy(blockname, "hwinfo.hex"); + break; + default: + printk(BIOS_ERR, "LCD: No supported panel found.\n"); + status = 1; + break; + } + + /* Now that we have the panel type, get the matching block and setup */ + /* the DP2LVDS converter accordingly */ + eib = get_edidinfo(blockname); + sib = get_shortinfo(blockname); + + if ((!eib) || (!sib)) { + printk(BIOS_ERR, "LCD: Info block named \"%s\" not found!\n", blockname); + status = 1; + } else { + printk(BIOS_INFO, "LCD: Found SIB at 0x%x, EIB at 0x%x\n", + (int)sib, (int)eib); + status = ptn3460_init(lcd_type, eib, sib); + printk(BIOS_INFO, "LCD: Setup PTN with status 0x%x\n", status); + } + return status; +} diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.h b/src/mainboard/siemens/mc_tcu3/lcd_panel.h new file mode 100644 index 0000000..b423dc0 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _LCD_PANEL_H_ +#define _LCD_PANEL_H_ + +/* This GPIOs are used for LCD panel type encoding */ +#define LCD_TYPE_GPIO_BIT0 40 +#define LCD_TYPE_GPIO_BIT1 41 +#define LCD_TYPE_GPIO_BIT2 42 +#define LCD_TYPE_GPIO_BIT3 43 + +#define LCD_PANEL_TYPE_10_INCH 4 +#define LCD_PANEL_TYPE_12_INCH 7 +#define LCD_PANEL_TYPE_15_INCH 6 +#define LCD_PANEL_TYPE_19_INCH 1 +#define LCD_PANEL_TYPE_EDID 15 + +u8 get_lcd_panel_type(void); +int setup_lcd_panel(void); + + +#endif /* _LCD_PANEL_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c new file mode 100644 index 0000000..fb350e5 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> + +#include "lcd_panel.h" + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ + setup_lcd_panel(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.c b/src/mainboard/siemens/mc_tcu3/modhwinfo.c new file mode 100644 index 0000000..95bb76c --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/modhwinfo.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "modhwinfo.h" +#include "lcd_panel.h" +#include <cbfs.h> +#include <string.h> + +/** \brief This function will find the first linked info block. + * @param *filename Filename in cbfs + * @param *file_offset Pointer to the offset of the cbfs file contents + * @return u8* Pointer to the found block + */ +u8* get_first_linked_block(char *filename, u8 **file_offset) +{ + u8* block_ptr = NULL; + + block_ptr = (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, filename, + 0x50, NULL)); + if (!block_ptr) + return NULL; + if (!strncmp((char*)block_ptr, "H1W2M3I4", LEN_MAGIC_NUM)) { + if ((*((u16*)(block_ptr + HWI_LEN_OFFSET)) == LEN_MAIN_HWINFO) && + (*((s32*)(block_ptr + NEXT_OFFSET_HWINFO)) != 0x00)) { + *file_offset = block_ptr; + return *((s32*)(block_ptr + NEXT_OFFSET_HWINFO)) + block_ptr; + } else + return NULL; + } else if (!strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM)) { + *file_offset = block_ptr; + return block_ptr; + } else + return NULL; +} + +/** \brief This function will find the main info block + * @param *filename Filename in cbfs + * @return *hwinfo Pointer to the data of the main info block + */ +struct hwinfo* get_hwinfo(char *filename) +{ + struct hwinfo* main_hwinfo; + + main_hwinfo = (struct hwinfo*)(cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + filename, 0x50, NULL)); + if ((main_hwinfo) && + (!strncmp(main_hwinfo->magicNumber, "H1W2M3I4", LEN_MAGIC_NUM)) && + (main_hwinfo->length == LEN_MAIN_HWINFO)) + return main_hwinfo; + else + return NULL; +} + +/** \brief This function will find the short info block + * @param *filename Filename in cbfs + * @return *shortinfo Pointer to the data of the short info block + */ +struct shortinfo* get_shortinfo(char *filename) +{ + u8 *block_ptr = NULL; + u8 *file_offset = NULL; + + block_ptr = get_first_linked_block(filename, &file_offset); + if ((block_ptr == NULL) || + (strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM))) + return NULL; + + if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_SHORT_INFO) + return (struct shortinfo *)block_ptr; + + block_ptr = (file_offset + *((s32*)(block_ptr + NEXT_OFFSET_EDID))); + if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_SHORT_INFO) + return (struct shortinfo *)block_ptr; + else + return NULL; +} + +/** \brief This function will find the edid info block + * @param *filename Filename in cbfs + * @return *edidinfo Pointer to the data of the edid info block + */ +struct edidinfo* get_edidinfo(char *filename) +{ + u8 *block_ptr = NULL; + u8 *file_offset = NULL; + + block_ptr = get_first_linked_block(filename, &file_offset); + if ((block_ptr == NULL) || + (strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM))) + return NULL; + + if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_EDID_INFO) + return (struct edidinfo *)block_ptr; + + block_ptr = (file_offset + *((s32*)(block_ptr + NEXT_OFFSET_SIB))); + if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_EDID_INFO) + return (struct edidinfo *)block_ptr; + else + return NULL; +} + +/** \brief This function will search for a MAC address which can be assigned + * to a MACPHY. + * @param pci_bdf Bus, device and function of the given PCI-device + * @param mac buffer where to store the MAC address + * @return cb_err CB_ERR or CB_SUCCESS + */ +enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) +{ + struct hwinfo* main_hwinfo; + u32 i; + + main_hwinfo = get_hwinfo((char*)"hwinfo.hex"); + if (!main_hwinfo) + return CB_ERR; + /* Ensure the first MAC-Address is not completely 0x00 or 0xff */ + for (i = 0; i < 6; i++) { + if (main_hwinfo->macAddress1[i] != 0xFF) + break; + } + if (i == 6){ + return CB_ERR; + } + for (i = 0; i < 6; i++) { + if (main_hwinfo->macAddress1[i] != 0x00) + break; + } + if (i == 6){ + return CB_ERR; + } else { + memcpy(mac, main_hwinfo->macAddress1, 6); + return CB_SUCCESS; + } +} diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.h b/src/mainboard/siemens/mc_tcu3/modhwinfo.h new file mode 100644 index 0000000..6eb8f05 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/modhwinfo.h @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _MODHWINFO_H_ +#define _MODHWINFO_H_ + +#include <types.h> + +#define LEN_MAGIC_NUM 8 +#define LEN_MLFB 20 +#define LEN_SERIAL_NUM 16 +#define LEN_HW_REVISION 2 +#define LEN_MAC_ADDRESS 6 +#define LEN_SPD 128 +#define NUMBER_OF_MAC_ADDR 4 +#define LEN_EDID 128 +#define LEN_MAIN_HWINFO 509 +#define LEN_SHORT_INFO 289 +#define LEN_EDID_INFO 181 +#define NEXT_OFFSET_HWINFO 476 +#define NEXT_OFFSET_SIB 260 +#define NEXT_OFFSET_EDID 176 +#define HWI_LEN_OFFSET 12 + +/* Define some masks and values */ +#define SIB_HWINIT_IDX 0x0e +#define SIB_COLOR_6BIT 0x00 +#define SIB_COLOR_8BIT 0x01 +#define SIB_COLOR_10BIT 0x02 +#define SIB_DISP_CON_IDX 0x16 +#define SIB_LVDS_SINGLE_LANE 0x00 +#define SIB_LVDS_DUAL_LANE 0x05 + +struct PhysDevStruc { + u8 bustype; + u8 devfn; + u16 bus; +} __attribute__ ((packed)); + + +struct hwinfo { +// Offset 0x0 + char magicNumber[LEN_MAGIC_NUM]; +// Offset 0x08 + u8 versionID[4]; +// Offset 0x0c + u16 length; +// Offset 0x0e + char BGR_Name[128]; +//Offset 0x8e + char MLFB[LEN_MLFB]; +// Offset 0xa2 + u8 uniqueNumber[16]; +// Offset 0xb2 + u8 fill_1[12]; +// Offset 0xbe + u8 hwRevision[LEN_HW_REVISION]; +//Offset 0xc0 + u8 macAddress1[LEN_MAC_ADDRESS]; + u8 numOfAuxMacAddr1; + u8 fill_2; +//Offset 0xc8 + u8 macAddress2[LEN_MAC_ADDRESS]; + u8 numOfAuxMacAddr2; + u8 fill_3; +//Offset 0xd0 + u8 macAddress3[LEN_MAC_ADDRESS]; + u8 numOfAuxMacAddr3; + u8 fill_4; +//Offset 0xd8 + u8 macAddress4[LEN_MAC_ADDRESS]; + u8 numOfAuxMacAddr4; + u8 fill_5; +// Offset 0xe0 + u8 SPD[LEN_SPD]; +// Offset 0x160 + u8 fill_6[88]; +// Offset 0x1b8 + u32 featureFlags; +// Offset 0x1bc + u8 fill_7[4]; +// Offset 0x1c0 + u32 biosFlags; +// Offset 0x1c4 + u8 fill_8[8]; +//Offset 0x1cc + struct PhysDevStruc etherDev[NUMBER_OF_MAC_ADDR]; +// Offset 0x1dc + s32 nextInfoOffset; +// Offset 0x1e0 + u8 fill_9[4]; +// Offset 0x1e4 + u32 portRTC; +// Offset 0x1e8 + u8 typeRTC; +// Offset 0x1e9 + u8 fill_10[20]; +} __attribute__ ((packed)); + +struct shortinfo { +// Offset 0x0 + char magicNumber[LEN_MAGIC_NUM]; +// Offset 0x08 + u8 versionID[4]; +// Offset 0x0c + u16 length; +// Offset 0x0e + char BGR_Name[128]; +//Offset 0x8e + char MLFB[LEN_MLFB]; +// Offset 0xa2 + u8 uniqueNumber[26]; +// Offset 0xbc + u8 fill_1[12]; +//Offset 0xc8 + u8 hwRevision[2]; +// Offset 0xca + u8 fill_2[18]; +// Offset 0xdc + u8 panelFeatures[32]; +// Offset 0xfc + u8 fill_3[8]; +// Offset 0x104 + s32 nextInfoOffset; +// Offset 0x108 + u8 fill_4[25]; +} __attribute__ ((packed)); + +struct edidinfo { +// Offset 0x0 + char magicNumber[LEN_MAGIC_NUM]; +// Offset 0x08 + u8 versionID[4]; +// Offset 0x0c + u16 length; +// Offset 0x0e + u8 fill_1[2]; +// Offset 0x10 + u8 edid[LEN_EDID]; +// Offset 0x90 + u8 fill_2[32]; +// Offset 0xb0 + s32 nextInfoOffset; +// Offset 0xb4 + u8 fill_3; +} __attribute__ ((packed)); + +u8* get_first_linked_block(char *filename, u8 **starting_adr); +struct hwinfo* get_hwinfo(char *filename); +struct shortinfo* get_shortinfo(char *filename); +struct edidinfo* get_edidinfo(char *filename); +enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); + +#endif /* _MODHWINFO_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c new file mode 100644 index 0000000..bb204e5 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include "baytrail/i2c.h" +#include "ptn3460.h" + +/** \brief This functions sets up the DP2LVDS-converter to be used with the + * appropriate lcd panel + * @param lcd_type Type of LCD we should set up the converter for + * @param *sib Pointer to short info block structure + * @param *eib Pointer to EDID info block structure + * @return 0 on success or error code + */ +int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib) +{ + struct ptn_3460_config cfg; + int status; + + + status = i2c_init(PTN_I2C_CONTROLER); + if (status) + return (PTN_BUS_ERROR | status); + + /* If we are here, we have all the desired information for setting up */ + /* DP2LVDS converter. In addition, the information matches the connected */ + /* LCD-panel and therefore, we do not have to distinguish between */ + /* different panels here for the timing. Inside the converter, table 6 */ + /* will be used for the timings. */ + status = ptn3460_write_edid(6, eib->edid); + if (status) + return status; + /* Select this table to be emulated */ + ptn_select_edid(6); + /* Read PTN configuration data */ + status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, + (u8*)&cfg, PTN_CONFIG_LEN); + if (status) + return (PTN_BUS_ERROR | status); + + /* Set up configuration data according to the information blocks we get */ + cfg.dp_interface_ctrl = 0; + cfg.lvds_interface_ctrl1 = 0x00; + if (sib->panelFeatures[SIB_DISP_CON_IDX] == SIB_LVDS_DUAL_LANE) + cfg.lvds_interface_ctrl1 |= 0x0b; /* Turn on dual LVDS lane and clock */ + if ((sib->panelFeatures[SIB_HWINIT_IDX] & 0x03) == SIB_COLOR_6BIT) + cfg.lvds_interface_ctrl1 |= 0x20; /* Use 18 bits per pixel */ + + cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ + cfg.lvds_interface_ctrl3 = 0x00; /* no LVDS signal swap */ + cfg.t2_delay = 1; /* Delay T2 (VDD to LVDS active) by 16 ms */ + cfg.t3_timing = 5; /* 250 ms from LVDS to backlight active */ + cfg.t12_timing = 20; /* 1 second re-power delay */ + cfg.t4_timing = 3; /* 150 ms backlight off to LVDS inactive */ + cfg.t5_delay = 1; /* Delay T5 (LVDS to VDD inactive) by 16 ms */ + cfg.backlight_ctrl = 0; /* Enable backlight control */ + + /* Write back configuration data to PTN3460 */ + status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, + (u8*)&cfg, PTN_CONFIG_LEN); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} + +/** \brief This functions reads one desired EDID data structure from PTN3460 + * @param edid_num Number of EDID that must be read (0..6) + * @param *data Pointer to a buffer where to store read data + * @return 0 on success or error code + */ +int ptn3460_read_edid(u8 edid_num, u8 *data) +{ + int status; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + /* First enable access to the desired EDID table */ + status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, + &edid_num, 1); + if (status) + return (PTN_BUS_ERROR | status); + + /* Now we can simply read back EDID-data */ + status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF, + data, PTN_EDID_LEN); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} + +/** \brief This functions writes one EDID data structure to PTN3460 + * @param edid_num Number of EDID that must be written (0..6) + * @param *data Pointer to a buffer where data to write is stored in + * @return 0 on success or error code + */ +int ptn3460_write_edid(u8 edid_num, u8 *data) +{ + int status; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + /* First enable access to the desired EDID table */ + status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, + &edid_num, 1); + if (status) + return (PTN_BUS_ERROR | status); + + /* Now we can simply write EDID-data to ptn3460 */ + status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF, + data, PTN_EDID_LEN); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} + +/** \brief This functions selects one of 7 EDID-tables inside PTN3460 + * which should be emulated on display port and turn emulation ON + * @param edid_num Number of EDID to emulate (0..6) + * @return 0 on success or error code + */ +int ptn_select_edid (u8 edid_num) +{ + int status; + u8 val; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + /* Enable emulation of the desired EDID table */ + val = (edid_num << 1) | 1; + status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, + &val, 1); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} + +/** \brief This functions performs a flash operation which will write + * current configuration table (all the EDID-tables and the + * configuration space with a total amount of 1 KByte) + * to the internal flash of PTN3460 + * @param none + * @return 0 on success or error code + */ +int ptn3460_flash_config(void) +{ + int status; + struct ptn_3460_flash flash; + + flash.cmd = 0x01; /* perform erase and flash cycle */ + flash.magic = 0x7845; /* Magic number to protect flash operation */ + flash.trigger = 0x56; /* This value starts flash operation */ + status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF, + (u8*)&flash, PTN_FLASH_CFG_LEN); + if (status) { + return (PTN_BUS_ERROR | status); + } else { + /* To ensure the flash operation is finished, we have to wait 300 ms */ + mdelay(300); + return PTN_NO_ERROR; + } +} diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h new file mode 100644 index 0000000..b975a69 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PTN3460_H_ +#define PTN3460_H_ + +#include <delay.h> +#include "modhwinfo.h" +#include "lcd_panel.h" + +#define PTN_SLAVE_ADR 0x20 +#define PTN_I2C_CONTROLER 0 + +#define PTN_EDID_OFF 0x00 +#define PTN_EDID_LEN 0x80 +#define PTN_CONFIG_OFF 0x80 +#define PTN_CONFIG_LEN 0x19 +#define PTN_FLASH_CFG_OFF 0xE8 +#define PTN_FLASH_CFG_LEN 0x04 +#define PTN_MAX_EDID_NUM 6 + +/* Define some error codes that can be used */ +#define PTN_NO_ERROR 0x00000000 +#define PTN_BUS_ERROR 0x10000000 +#define PTN_INVALID_EDID 0x20000000 + +struct ptn_3460_config{ + u8 dp_interface_ctrl; /* DiplayPort interface control */ + u8 lvds_interface_ctrl1; /* LVDS interface control register 1 */ + u8 lvds_interface_ctrl2; /* LVDS interface control register 2 */ + u8 lvds_interface_ctrl3; /* LVDS interface control register 3 */ + u8 edid_rom_emulation; /* select which EDID-block is emulated */ + u8 edid_rom_access_ctrl; /* select which EDID block to map to 0..0x7F */ + u8 pwm_min[3]; /* smallest PWM frequency for back light */ + u8 pwm_max[3]; /* biggest PWM frequency for back light */ + u8 fast_link_ctrl; /* Fast link training control register */ + u8 pin_cfg_ctrl1; /* Pin configuration control register 1 */ + u8 pin_cfg_ctrl2; /* Pin configuration control register 2 */ + u8 pwm_default; /* Default PWM bit count in DPCD register */ + u16 pwm_value; /* Current PWM bit count in DPCD register */ + u8 pwm_default_freq; /* Default PWM frequency in DPCD register */ + u8 t3_timing; /* Panel T3 timing value */ + u8 t12_timing; /* Panel T12 timing value */ + u8 backlight_ctrl; /* Back light control register */ + u8 t2_delay; /* Panel T2 delay */ + u8 t4_timing; /* Panel T4 timing value */ + u8 t5_delay; /* Panel T5 delay */ +}__attribute__((packed)); + +struct ptn_3460_flash{ + u8 cmd; /* Flash command (erase or erase and flash) */ + u16 magic; /* Magic number needed by the flash algorithm */ + u8 trigger; /* Trigger for starting flash operation */ +}__attribute__((packed)); + + +int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib); +int ptn3460_read_edid(u8 edid_num, u8 *data); +int ptn3460_write_edid(u8 edid_num, u8 *data); +int ptn_select_edid(u8 edid_num); +int ptn3460_flash_config(void); +#endif /* PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c new file mode 100644 index 0000000..5274529 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/cpu.h> +#include <lib.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <romstage_handoff.h> +#include <timestamp.h> +#include <baytrail/gpio.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/romstage.h> +#include <baytrail/acpi.h> +#include <baytrail/baytrail.h> +#include <drivers/intel/fsp/fsp_util.h> +#include "modhwinfo.h" + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry() +{ + +} + +/** + * Get function disables - most of these will be done automatically + * @param fd_mask + * @param fd2_mask + */ +void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +{ + +} + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ +void late_mainboard_romstage_entry() +{ + +} + +const uint32_t mAzaliaVerbTableData13[] = { +/* + *ALC262 Verb Table - 10EC0262 + */ + /* Pin Complex (NID 0x11 ) */ + 0x01171CF0, + 0x01171D11, + 0x01171E11, + 0x01171F41, + /* Pin Complex (NID 0x12 ) */ + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + /* Pin Complex (NID 0x14 ) */ + 0x01471C10, + 0x01471D40, + 0x01471E01, + 0x01471F01, + /* Pin Complex (NID 0x15 ) */ + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + /* Pin Complex (NID 0x16 ) */ + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + /* Pin Complex (NID 0x18 ) */ + 0x01871C20, + 0x01871D98, + 0x01871EA1, + 0x01871F01, + /* Pin Complex (NID 0x19 ) */ + 0x01971C21, + 0x01971D98, + 0x01971EA1, + 0x01971F02, + /* Pin Complex (NID 0x1A ) */ + 0x01A71C2F, + 0x01A71D30, + 0x01A71E81, + 0x01A71F01, + /* Pin Complex (NID 0x1B ) */ + 0x01B71C1F, + 0x01B71D40, + 0x01B71E21, + 0x01B71F02, + /* Pin Complex (NID 0x1C ) */ + 0x01C71CF0, + 0x01C71D11, + 0x01C71E11, + 0x01C71F41, + /* Pin Complex (NID 0x1D ) */ + 0x01D71C01, + 0x01D71DC6, + 0x01D71E14, + 0x01D71F40, + /* Pin Complex (NID 0x1E ) */ + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + /* Pin Complex (NID 0x1F ) */ + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41 }; + +const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { +/* + * VerbTable: (RealTek ALC262) + * Revision ID = 0xFF, support all steps + * Codec Verb Table For AZALIA + * Codec Address: CAd value (0/1/2) + * Codec Vendor: 0x10EC0262 + */ + { + 0x10EC0262, /* Vendor ID/Device IDA */ + 0x0000, /* SubSystem ID */ + 0xFF, /* Revision IDA */ + 0x01, /* Front panel support (1=yes, 2=no) */ + 0x000B, /* Number of Rear Jacks = 11 */ + 0x0002 /* Number of Front Jacks = 2 */ + }, + (uint32_t *)mAzaliaVerbTableData13 } }; + +const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { + .Pme = 1, + .DS = 1, + .DA = 0, + .HdmiCodec = 1, + .AzaliaVCi = 1, + .Rsvdbits = 0, + .AzaliaVerbTableNum = 1, + .AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable, + .ResetWaitTimer = 300 }; + +/** /brief customize fsp parameters here if needed + */ +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + struct hwinfo *hwi_main; + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + /* Initialize the Azalia Verb Tables to mainboard specific version */ + UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; + + /* Disable 2nd DIMM on Bakersport*/ +#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP) + UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ +#endif + /* Get SPD data from hardware information block and setup memory down */ + /* parameters for FSP accordingly */ + hwi_main = get_hwinfo((char*)"hwinfo.hex"); + if (hwi_main) { + UpdData->PcdMemoryParameters.EnableMemoryDown = 1; + UpdData->PcdMemoryParameters.DRAMType = hwi_main->SPD[2]; + UpdData->PcdMemoryParameters.DIMM0Enable = hwi_main->SPD[3] & 0x01; + UpdData->PcdMemoryParameters.DIMM1Enable = (hwi_main->SPD[3] >> 1) & 0x01; + UpdData->PcdMemoryParameters.DIMMDensity = hwi_main->SPD[4]; + UpdData->PcdMemoryParameters.DIMMDWidth = hwi_main->SPD[5]; + UpdData->PcdMemoryParameters.DIMMSides = hwi_main->SPD[7]; + UpdData->PcdMemoryParameters.DIMMBusWidth = hwi_main->SPD[8]; + UpdData->PcdMemoryParameters.DRAMSpeed = hwi_main->SPD[12]; + UpdData->PcdMemoryParameters.DIMMtCL = hwi_main->SPD[14]; + UpdData->PcdMemoryParameters.DIMMtWR = hwi_main->SPD[17]; + UpdData->PcdMemoryParameters.DIMMtRPtRCD = hwi_main->SPD[18]; + UpdData->PcdMemoryParameters.DIMMtRRD = hwi_main->SPD[19]; + UpdData->PcdMemoryParameters.DIMMtWTR = hwi_main->SPD[26]; + UpdData->PcdMemoryParameters.DIMMtRTP = hwi_main->SPD[27]; + UpdData->PcdMemoryParameters.DIMMtFAW = hwi_main->SPD[28]; + /*If one need output from MRC to be used in Intel RMT, simply */ + /*enable the following line */ + //UpdData->PcdMrcDebugMsg = 1; + } else + printk(BIOS_ERR, "HWInfo not found, leave default timings for DDR3.\n"); +} diff --git a/src/mainboard/siemens/mc_tcu3/thermal.h b/src/mainboard/siemens/mc_tcu3/thermal.h new file mode 100644 index 0000000..78dfcbe --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/thermal.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/siemens/mc_tcu3/version.hex b/src/mainboard/siemens/mc_tcu3/version.hex new file mode 100644 index 0000000..10b9c23 --- /dev/null +++ b/src/mainboard/siemens/mc_tcu3/version.hex @@ -0,0 +1,3 @@ +$USRV01.00.00.00 +$PLTTCU30.3 +$EXVV01.00.00.00

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coreboot-gerrit February 2015