coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

1 participants
509 discussions

Patch merged into coreboot/master: 21a5309 soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`
by gerrit＠coreboot.org 25 Feb '15

25 Feb '15

the following patch was just integrated into master: commit 21a530981df1af8d648a4b2d46af0febbd56a8c5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Feb 17 11:04:30 2015 +0100 soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER` Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`). Therefore remove the explicit selection of that Kconfig option. Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8471 for details. -gerrit

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Patch merged into coreboot/master: e5853d5 nvramcui: drop unused variable
by gerrit＠coreboot.org 25 Feb '15

25 Feb '15

the following patch was just integrated into master: commit e5853d5235478897632dee3467f81b3b2467cf73 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Sun Feb 1 14:33:55 2015 +0100 nvramcui: drop unused variable nvramcui.c: In function ‘main’: nvramcui.c:68:8: warning: unused variable ‘cur’ [-Wunused-variable] ITEM *cur; ^ Change-Id: I5c692fc2e6da460cd7c6f7978378c92587d829d2 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> Reviewed-on: http://review.coreboot.org/8525 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8525 for details. -gerrit

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Patch merged into coreboot/master: f3a235e intel/broadwell: free local heap object
by gerrit＠coreboot.org 25 Feb '15

25 Feb '15

the following patch was just integrated into master: commit f3a235e9770035d429e66da511edef24a2e88b6b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Feb 22 16:51:23 2015 +0100 intel/broadwell: free local heap object No real harm done (thanks to our free() implementation), but let's do it right. Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8511 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8511 for details. -gerrit

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Patch merged into coreboot/master: bdd185a amd/sb600: Fix NULL test after use issue
by gerrit＠coreboot.org 25 Feb '15

25 Feb '15

the following patch was just integrated into master: commit bdd185a355c15a6f18c11cf173cdeb4f599059a6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Feb 22 17:54:18 2015 +0100 amd/sb600: Fix NULL test after use issue Change-Id: Icecbcc1dee837ecfe0dd52bade3b83fdcdd15bad Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8513 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8513 for details. -gerrit

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Patch set updated for coreboot: 8a7b811 x86: Fix pointer arithmetic regressions from MMIO changes
by Kevin Paul Herbert 25 Feb '15

25 Feb '15

Kevin Paul Herbert (kph(a)meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8530 -gerrit commit 8a7b81119db78dbfd4979c92d26f04de3aa87282 Author: Kevin Paul Herbert <kph(a)meraki.net> Date: Wed Feb 25 00:36:51 2015 -0800 x86: Fix pointer arithmetic regressions from MMIO changes During the development of bde6d30, there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the ibexpeak SATA driver. Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe. Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert <kph(a)meraki.net> --- src/soc/intel/fsp_baytrail/southcluster.c | 4 ++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 878535f..ec2f94f 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -91,8 +91,8 @@ static void sc_enable_ioapic(struct device *dev) * Set SCI IRQ to IRQ9 */ write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */ - write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ *ioapic_index = 0; *ioapic_data = (1 << 25); diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 5463d2b..9deeb45 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 21df6c0..05ca871 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -11,7 +11,7 @@ #include "amd8111.h" -#define CMD3 (0x54/(sizeof(u32))) +#define CMD3 0x54 typedef enum { VAL3 = (1 << 31), /* VAL bit for byte 3 */ diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8f29670..80673a6 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev) u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); /* * Enable ACPI I/O and power management.

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New patch to review for coreboot: e72fbd1 x86: Fix pointer arithmetic regressions from MMIO changes
by Kevin Paul Herbert 25 Feb '15

25 Feb '15

Kevin Paul Herbert (kph(a)meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8530 -gerrit commit e72fbd1984763032a51952da3b842a97b33380da Author: Kevin Paul Herbert <kph(a)meraki.net> Date: Wed Feb 25 00:36:51 2015 -0800 x86: Fix pointer arithmetic regressions from MMIO changes During the development of bde6d30, there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the ibexpeak SATA driver. Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe. Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert <kph(a)meraki.net> --- src/soc/intel/fsp_baytrail/southcluster.c | 4 ++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 878535f..ec2f94f 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -91,8 +91,8 @@ static void sc_enable_ioapic(struct device *dev) * Set SCI IRQ to IRQ9 */ write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */ - write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ *ioapic_index = 0; *ioapic_data = (1 << 25); diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 5463d2b..0d032b3 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL), reg32); } diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 21df6c0..05ca871 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -11,7 +11,7 @@ #include "amd8111.h" -#define CMD3 (0x54/(sizeof(u32))) +#define CMD3 0x54 typedef enum { VAL3 = (1 << 31), /* VAL bit for byte 3 */ diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8f29670..32fb220 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev) u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f); + u8 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f); /* * Enable ACPI I/O and power management.

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Patch set updated for coreboot: 62465b5 coreboot arm: Define function for setting cntfrq register
by Marc Jones 25 Feb '15

25 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8468 -gerrit commit 62465b509b1e8d7e58e2a55468c821b2f46c2a9b Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 15:21:03 2014 -0700 coreboot arm: Define function for setting cntfrq register Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a --- src/arch/arm/Makefile.inc | 3 + src/arch/arm/clock.c | 36 ++ src/arch/arm/include/arch/clock.h | 25 ++ src/arch/arm64/armv8/lib/Makefile.inc | 2 +- src/arch/arm64/armv8/lib/clock.c | 32 ++ src/arch/arm64/include/arch/clock.h | 25 ++ src/soc/nvidia/tegra124/clock.c | 3 +- src/soc/nvidia/tegra132/clock.c | 674 ++++++++++++++++++++++++++++++++++ 8 files changed, 798 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 96c8b49..0fcbf6c 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -60,6 +60,7 @@ bootblock-y += memset.S bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c +bootblock-y += clock.c $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -91,6 +92,7 @@ romstage-y += eabi_compat.c romstage-y += memset.S romstage-y += memcpy.S romstage-y += memmove.S +romstage-y += clock.c VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o @@ -115,6 +117,7 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S +ramstage-y += clock.c ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions diff --git a/src/arch/arm/clock.c b/src/arch/arm/clock.c new file mode 100644 index 0000000..5f68e6f --- /dev/null +++ b/src/arch/arm/clock.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include <stdint.h> +#include <arch/clock.h> + +void set_cntfrq(uint32_t freq) +{ + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); +} diff --git a/src/arch/arm/include/arch/clock.h b/src/arch/arm/include/arch/clock.h new file mode 100644 index 0000000..a11fbd4 --- /dev/null +++ b/src/arch/arm/include/arch/clock.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_CLOCK_H_ +#define __ARM_CLOCK_H_ + +void set_cntfrq(uint32_t); + +#endif //__ARM_CLOCK_H_ diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index bda203b..3e393bb 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -20,7 +20,7 @@ ## ################################################################################ -lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c +lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c clock.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) bootblock-y += $(lib_access) diff --git a/src/arch/arm64/armv8/lib/clock.c b/src/arch/arm64/armv8/lib/clock.c new file mode 100644 index 0000000..00c9208 --- /dev/null +++ b/src/arch/arm64/armv8/lib/clock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * clock.c: Functions for accessing clock and timer related registers + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + */ + +#include <stdint.h> + +#include <arch/clock.h> + +void set_cntfrq(uint32_t freq) +{ + __asm__ __volatile__("msr cntfrq_el0, %0" :: "r"(freq)); +} diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h new file mode 100644 index 0000000..a11fbd4 --- /dev/null +++ b/src/arch/arm64/include/arch/clock.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_CLOCK_H_ +#define __ARM_CLOCK_H_ + +void set_cntfrq(uint32_t); + +#endif //__ARM_CLOCK_H_ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index e3c0e71..fa33283 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -20,6 +20,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <stdlib.h> +#include <arch/clock.h> #include "clk_rst.h" #include "flow.h" #include "maincpu.h" @@ -181,7 +182,7 @@ void clock_init_arm_generic_timer(void) { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. - __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); + set_cntfrq(freq); // Record the system timer frequency. write32(freq, &sysctr->cntfid0); diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c new file mode 100644 index 0000000..83a73f2 --- /dev/null +++ b/src/soc/nvidia/tegra132/clock.c @@ -0,0 +1,674 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <console/console.h> +#include <delay.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <stdlib.h> +#include <arch/clock.h> +#include "clk_rst.h" +#include "flow.h" +#include "maincpu.h" +#include "pmc.h" +#include "sysctr.h" + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; +static struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; +static struct sysctr_regs *sysctr = (void *)TEGRA_SYSCTR0_BASE; + +struct pll_dividers { + u32 n : 10; + u32 m : 8; + u32 p : 4; + u32 cpcon : 4; + u32 lfcon : 4; + u32 : 2; +}; + +/* Some PLLs have more restrictive divider bit lengths or are missing some + * fields. Make sure to use the right struct in the osc_table definition to get + * compile-time checking, but keep the bits aligned with struct pll_dividers so + * they can be used interchangeably at run time. Add new formats as required. */ +struct pllcx_dividers { + u32 n : 8; + u32 : 2; + u32 m : 8; + u32 p : 4; + u32 : 10; +}; +struct pllpad_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 3; + u32 : 1; + u32 cpcon : 4; + u32 : 6; +}; +struct pllu_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 1; + u32 : 3; + u32 cpcon : 4; + u32 lfcon : 4; + u32 : 2; +}; + +union __attribute__((transparent_union)) pll_fields { + u32 raw; + struct pll_dividers div; + struct pllcx_dividers cx; + struct pllpad_dividers pad; + struct pllu_dividers u; +}; + +/* This table defines the frequency dividers for every PLL to turn the external + * OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h. + * All PLLs have three dividers (n, m and p), with the governing formula for + * the output frequency being CF = (IN / m), VCO = CF * n and OUT = VCO / (2^p). + * All divisor configurations must meet the PLL's constraints for VCO and CF: + * PLLX: 12 MHz < CF < 50 MHz, 700 MHz < VCO < 3000 MHz + * PLLC: 12 MHz < CF < 50 MHz, 600 MHz < VCO < 1400 MHz + * PLLM: 12 MHz < CF < 50 MHz, 400 MHz < VCO < 1066 MHz + * PLLP: 1 MHz < CF < 6 MHz, 200 MHz < VCO < 700 MHz + * PLLD: 1 MHz < CF < 6 MHz, 500 MHz < VCO < 1000 MHz + * PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz + * PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz + * (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */ +struct { + int khz; + struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */ + struct pllcx_dividers pllc; /* target: 600 MHz */ + /* PLLM is set up dynamically by clock_sdram(). */ + /* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */ + struct pllu_dividers pllu; /* target; 960 MHz */ + struct pllcx_dividers plldp; /* target; 270 MHz */ + /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ +} static const osc_table[16] = { + [OSC_FREQ_12]{ + .khz = 12000, + .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 90, .m = 1, .p = 3}, + }, + [OSC_FREQ_13]{ + .khz = 13000, + .pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0}, + .pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */ + .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */ + }, + [OSC_FREQ_16P8]{ + .khz = 16800, + .pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0}, + .pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */ + .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2}, + .plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */ + }, + [OSC_FREQ_19P2]{ + .khz = 19200, + .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, + .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ + .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, + .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ + }, + [OSC_FREQ_26]{ + .khz = 26000, + .pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0}, + .pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */ + .pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 83, .m = 2, .p = 3}, /* 269.8 MHz */ + }, + /* These oscillators get predivided as PLL inputs... n/m/p divisors for + * 38.4 should always match 19.2, and 48 should always match 12. */ + [OSC_FREQ_38P4]{ + .khz = 38400, + .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, + .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ + .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, + .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ + }, + [OSC_FREQ_48]{ + .khz = 48000, + .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, + .plldp = {.n = 90, .m = 1, .p = 3}, + }, +}; + +/* Get the oscillator frequency, from the corresponding hardware + * configuration field. This is actually a per-soc thing. Avoid the + * temptation to make it common. + */ +static u32 clock_get_osc_bits(void) +{ + return (readl(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; +} + +int clock_get_osc_khz(void) +{ + return osc_table[clock_get_osc_bits()].khz; +} + +int clock_get_pll_input_khz(void) +{ + u32 osc_ctrl = readl(&clk_rst->osc_ctrl); + u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; + return osc_table[osc_bits].khz >> pll_ref_div; +} + +void clock_init_arm_generic_timer(void) +{ + uint32_t freq = clock_get_osc_khz() * 1000; + /* Set the cntfrq register. */ + set_cntfrq(freq); + + /* Record the system timer frequency. */ + write32(freq, &sysctr->cntfid0); + /* Enable the system counter. */ + uint32_t cntcr = read32(&sysctr->cntcr); + cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; + write32(cntcr, &sysctr->cntcr); +} + +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) + +void sor_clock_stop(void) +{ + /* The Serial Output Resource clock has to be off + * before we start the plldp. Learned the hard way. + * FIXME: this has to be cleaned up a bit more. + * Waiting on some new info from Nvidia. + */ + clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); +} + +void sor_clock_start(void) +{ + /* uses PLLP, has a non-standard bit layout. */ + setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); +} + +static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) +{ + u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT | + pll.div.m << PLL_BASE_DIVM_SHIFT | + pll.div.p << PLL_BASE_DIVP_SHIFT; + u32 misc_con = pll.div.cpcon << PLL_MISC_CPCON_SHIFT | + pll.div.lfcon << PLL_MISC_LFCON_SHIFT; + + /* Write dividers but BYPASS the PLL while we're messing with it. */ + writel(dividers | PLL_BASE_BYPASS, base); + /* + * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't + * exist for this PLL) + */ + writel(lock | misc_con, misc); + + /* Enable PLL and take it back out of BYPASS */ + writel(dividers | PLL_BASE_ENABLE, base); + + /* Wait for lock ready */ + while (!(readl(base) & PLL_BASE_LOCK)); +} + +static void init_utmip_pll(void) +{ + int khz = clock_get_pll_input_khz(); + + /* Shut off PLL crystal clock while we mess with it */ + clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + udelay(1); + + write32(80 << 16 | /* (rst) phy_divn */ + 1 << 8 | /* (rst) phy_divm */ + 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + + write32(div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + 0 << 16 | /* PLLU pwrdn */ + 0 << 14 | /* pll_enable pwrdn */ + 0 << 12 | /* pll_active pwrdn */ + div_round_up(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */ + 0, &clk_rst->utmip_pll_cfg1); + + /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ + write32(0 << 24 | /* SAMP_D/XDEV pwrdn */ + div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + 0 << 4 | /* SAMP_C/USB3 pwrdn */ + 0 << 2 | /* SAMP_B/XHOST pwrdn */ + 0 << 0 | /* SAMP_A/USBD pwrdn */ + 0, &clk_rst->utmip_pll_cfg2); + + setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ +} + +/* Graphics just has to be different. There's a few more bits we + * need to set in here, but it makes sense just to restrict all the + * special bits to this one function. + */ +static void graphics_pll(void) +{ + int osc = clock_get_osc_bits(); + u32 *cfg = &clk_rst->plldp_ss_cfg; + /* the vendor code sets the dither bit (28) + * an undocumented bit (24) + * and clamp while we mess with it (22) + * Dither is pretty important to display port + * so we really do need to handle these bits. + * I'm not willing to not clamp it, even if + * it might "mostly work" with it not set, + * I don't want to find out in a few months + * that it is needed. + */ + u32 scfg = (1 << 28) | (1 << 24) | (1 << 22); + writel(scfg, cfg); + init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, + osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); + /* leave dither and undoc bits set, release clamp */ + scfg = (1<<28) | (1<<24); + writel(scfg, cfg); + + /* disp1 will be set when panel information (pixel clock) is + * retrieved (clock_display). + */ +} + +/* Init PLLD clock source. */ +int +clock_display(u32 frequency) +{ + /** + * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz + * = (cf * n) >> p, where 1MHz < cf < 6MHz + * = ((ref / m) * n) >> p + * + * Iterate the possible values of p (3 bits, 2^7) to find out a minimum + * safe vco, then find best (m, n). since m has only 5 bits, we can + * iterate all possible values. Note Tegra 124 supports 11 bits for n, + * but our pll_fields has only 10 bits for n. + * + * Note, values that undershoot or overshoot the target output frequency + * may not work if the values are not in "safe" range by panel + * specification. + */ + struct pllpad_dividers plld = { 0 }; + u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0; + u32 cf, vco; + u32 diff, best_diff; + const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, + mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, + min_cf = 1 * mhz, max_cf = 6 * mhz; + + for (vco = frequency; vco < min_vco && p < max_p; p++) + vco <<= 1; + + if (vco < min_vco || vco > max_vco) { + printk(BIOS_ERR, "%s: Cannot find out a supported VCO" + " for Frequency (%u).\n", __func__, frequency); + return -1; + } + + plld.p = p; + best_diff = vco; + + for (m = 1; m < max_m && best_diff; m++) { + cf = ref / m; + if (cf < min_cf) + break; + if (cf > max_cf) + continue; + + n = vco / cf; + if (n >= max_n) + continue; + + diff = vco - n * cf; + if (n + 1 < max_n && diff > cf / 2) { + n++; + diff = cf - diff; + } + + if (diff >= best_diff) + continue; + + best_diff = diff; + plld.m = m; + plld.n = n; + } + + if (plld.n < 50) + plld.cpcon = 2; + else if (plld.n < 300) + plld.cpcon = 3; + else if (plld.n < 600) + plld.cpcon = 8; + else + plld.cpcon = 12; + + if (best_diff) + printk(BIOS_ERR, "%s: Failed to match output frequency %u, " + "best difference is %u.\n", __func__, frequency, + best_diff); + + printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", + __func__, (ref / plld.m * plld.n) >> plld.p, ref, plld.m, plld.n, + plld.p, plld.cpcon); + + init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, plld, + (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE)); + return 0; +} + +/* Initialize the UART and put it on CLK_M so we can use it during clock_init(). + * Will later move it to PLLP in clock_config(). The divisor must be very small + * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * CLK_SOURCE divider to get more precision. (This might still not be enough for + * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has + * been determined through trial and error (must lead to div 13 at 24MHz). */ +void clock_early_uart(void) +{ + write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | + CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta); + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + udelay(2); + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); +} + +/* Enable output clock (CLK1~3) for external peripherals. */ +void clock_external_output(int clk_id) +{ + switch (clk_id) { + case 1: + setbits_le32(&pmc->clk_out_cntrl, 1 << 2); + break; + case 2: + setbits_le32(&pmc->clk_out_cntrl, 1 << 10); + break; + case 3: + setbits_le32(&pmc->clk_out_cntrl, 1 << 18); + break; + default: + printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", + clk_id); + break; + } +} + +/* Start PLLM for SDRAM. */ +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq) +{ + u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) | + (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) | + (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) | + (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)); + u32 misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | + (kcp << PLLM_MISC2_KCP_SHIFT)); + u32 base; + + if (same_freq) + emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + else + emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + + /* + * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and + * PLLM_BASE.ENABLE must be in DISABLE state (both are the default + * values after coldboot reset). + */ + + writel(misc1, &clk_rst->pllm_misc1); + writel(misc2, &clk_rst->pllm_misc2); + + /* PLLM.BASE needs BYPASS=0, different from general init_pll */ + base = readl(&clk_rst->pllm_base); + base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | + PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); + base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | + (p << PLL_BASE_DIVP_SHIFT)); + writel(base, &clk_rst->pllm_base); + + setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); + /* stable_time is required, before we can start to check lock. */ + udelay(stable_time); + + while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) + udelay(1); + + /* + * After PLLM reports being locked, we have to delay 10us before + * enabling PLLM_OUT. + */ + udelay(10); + + /* Put OUT1 out of reset state (start to output). */ + setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); + + /* Enable and start MEM(MC) and EMC. */ + clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); + writel(emc_source, &clk_rst->clk_src_emc); + udelay(IO_STABILIZATION_DELAY); +} + +void clock_cpu0_config_and_reset(void *entry) +{ + void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + + write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); + write32((uintptr_t)entry, &maincpu_entry_point); + write32((uintptr_t)&maincpu_setup, evp_cpu_reset); + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + /* Set up cclk_brst and divider. */ + write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | + (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), + &clk_rst->cclk_brst_pol); + write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, + &clk_rst->super_cclk_div); + + /* Enable the clocks for CPUs 0-3. */ + uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); + cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | + CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; + write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + + /* Enable other CPU related clocks. */ + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); + + /* Disable the reset on the non-CPU parts of the fast cluster. */ + write32(CRC_RST_CPUG_CLR_NONCPU, + &clk_rst->rst_cpug_cmplx_clr); + /* Disable the various resets on the CPUs. */ + write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | + CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | + CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | + CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | + CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | + CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | + CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | + CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, + &clk_rst->rst_cpug_cmplx_clr); + + /* Disable the reset on the non-CPU parts of the slow cluster. */ + write32(CRC_RST_CPULP_CLR_NONCPU, + &clk_rst->rst_cpulp_cmplx_clr); + /* Disable the various resets on the LP CPU. */ + write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | + CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | + CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, + &clk_rst->rst_cpulp_cmplx_clr); +} + +void clock_halt_avp(void) +{ + for (;;) + write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | + FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, + &flow->halt_cop_events); +} + +void clock_init(void) +{ + u32 osc = clock_get_osc_bits(); + + /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ + writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); + + /* Max out the AVP clock before everything else (need PLLC for that). */ + init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, + osc_table[osc].pllc, PLLC_MISC_LOCK_ENABLE); + + /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA + * features section in the TRM). */ + write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, + &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ + write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); + write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | + SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, + &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ + + /* Change the oscillator drive strength (from U-Boot -- why?) */ + clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, + OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + + /* + * Ambiguous quote from u-boot. TODO: what's this mean? + * "should update same value in PMC_OSC_EDPD_OVER XOFS + * field for warmboot " + */ + clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, + OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); + + /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ + clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); + + /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ + write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, + &clk_rst->pllp_outa); + write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, + &clk_rst->pllp_outb); + + /* init pllx */ + init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, + osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE); + + /* init pllu */ + init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, + osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE); + + init_utmip_pll(); + graphics_pll(); +} + +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +{ + if (l) + writel(l, &clk_rst->clk_enb_l_set); + if (h) + writel(h, &clk_rst->clk_enb_h_set); + if (u) + writel(u, &clk_rst->clk_enb_u_set); + if (v) + writel(v, &clk_rst->clk_enb_v_set); + if (w) + writel(w, &clk_rst->clk_enb_w_set); + if (x) + writel(x, &clk_rst->clk_enb_x_set); + + /* Give clocks time to stabilize. */ + udelay(IO_STABILIZATION_DELAY); + + if (l) + writel(l, &clk_rst->rst_dev_l_clr); + if (h) + writel(h, &clk_rst->rst_dev_h_clr); + if (u) + writel(u, &clk_rst->rst_dev_u_clr); + if (v) + writel(v, &clk_rst->rst_dev_v_clr); + if (w) + writel(w, &clk_rst->rst_dev_w_clr); + if (x) + writel(x, &clk_rst->rst_dev_x_clr); +} + +void clock_reset_l(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_l_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_l_clr); +} + +void clock_reset_h(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_h_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_h_clr); +} + +void clock_reset_u(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_u_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_u_clr); +} + +void clock_reset_v(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_v_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_v_clr); +} + +void clock_reset_w(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_w_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_w_clr); +} + +void clock_reset_x(u32 bit) +{ + writel(bit, &clk_rst->rst_dev_x_set); + udelay(1); + writel(bit, &clk_rst->rst_dev_x_clr); +}

1 0

Patch set updated for coreboot: 13c6016 coreboot arm64: Correct cache function names
by Marc Jones 25 Feb '15

25 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8469 -gerrit commit 13c601603b1d12adca67732f5daf5a633bac704c Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 24 17:35:30 2014 -0700 coreboot arm64: Correct cache function names Correct function names to make them consistent with generic calling name BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205582 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16668529527224fca3086ee88955d29e3a268516) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317 --- src/arch/arm64/armv8/cache.c | 6 +++--- src/arch/arm64/include/armv8/arch/cache.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 918a883..97822ff 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -101,17 +101,17 @@ static void dcache_op_va(void const *addr, size_t len, enum dcache_op op) isb(); } -void dcache_clean_by_va(void const *addr, size_t len) +void dcache_clean_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCVAC); } -void dcache_clean_invalidate_by_va(void const *addr, size_t len) +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCIVAC); } -void dcache_invalidate_by_va(void const *addr, size_t len) +void dcache_invalidate_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCIVAC); } diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 977edba..2d42011 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -59,13 +59,13 @@ /* dcache clean by virtual address to PoC */ -void dcache_clean_by_va(void const *addr, size_t len); +void dcache_clean_by_mva(void const *addr, size_t len); /* dcache clean and invalidate by virtual address to PoC */ -void dcache_clean_invalidate_by_va(void const *addr, size_t len); +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); /* dcache invalidate by virtual address to PoC */ -void dcache_invalidate_by_va(void const *addr, size_t len); +void dcache_invalidate_by_mva(void const *addr, size_t len); /* dcache invalidate all */ void flush_dcache_all(void);

1 0

Patch set updated for coreboot: 7a0dc4b rush: Correct version field to match t132
by Marc Jones 25 Feb '15

25 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8467 -gerrit commit 7a0dc4bd334c40127c1871bcbf30e28f2ec3036e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 24 14:22:36 2014 -0500 rush: Correct version field to match t132 The version field for t132 cpus is 0x00130001. Update it to the correct version. BUG=chrome-os-partner:29882 BRANCH=None TEST=Built and was able to see serial with subsequent changes. Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205435 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a --- src/mainboard/google/rush/bct/emmc.cfg | 2 +- src/mainboard/google/rush/bct/spi.cfg | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/rush/bct/emmc.cfg b/src/mainboard/google/rush/bct/emmc.cfg index be8f79f..430ffd6 100644 --- a/src/mainboard/google/rush/bct/emmc.cfg +++ b/src/mainboard/google/rush/bct/emmc.cfg @@ -1,7 +1,7 @@ # Copyright (c) 2013 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 -Version = 0x00350001; +Version = 0x00130001; BlockSize = 0x00004000; PageSize = 0x00000200; PartitionSize = 0x01000000; diff --git a/src/mainboard/google/rush/bct/spi.cfg b/src/mainboard/google/rush/bct/spi.cfg index 7d05363..a5ded0b 100644 --- a/src/mainboard/google/rush/bct/spi.cfg +++ b/src/mainboard/google/rush/bct/spi.cfg @@ -1,13 +1,11 @@ # Copyright (c) 2013 The Chromium OS Authors. All rights reserved. # Distributed under the terms of the GNU General Public License v2 -Version = 0x00350001; +Version = 0x00130001; BlockSize = 32768; PageSize = 2048; PartitionSize = 4194304; -Bctcopy = 1; - DevType[0] = NvBootDevType_Spi; DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;

1 0

Patch set updated for coreboot: a5b12af coreboot arm64: Add library for system access
by Marc Jones 25 Feb '15

25 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8465 -gerrit commit a5b12af797a583685190ee7e3e534f771eb59af1 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 11 14:48:37 2014 -0700 coreboot arm64: Add library for system access Add support for library functions required to access different system registers: 1) PSTATE and special purpose registers 2) System control registers 3) Cache-related registers 4) TLB maintenance registers 5) Misc barrier related functions BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203490 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Get the library and the GPL license in a single commit. Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d --- src/arch/arm64/armv8/Makefile.inc | 2 + src/arch/arm64/armv8/cache.c | 17 +- src/arch/arm64/armv8/lib/Makefile.inc | 35 + src/arch/arm64/armv8/lib/cache.c | 82 +++ src/arch/arm64/armv8/lib/misc.c | 58 ++ src/arch/arm64/armv8/lib/pstate.c | 423 ++++++++++++ src/arch/arm64/armv8/lib/sysctrl.c | 871 ++++++++++++++++++++++++ src/arch/arm64/armv8/lib/tlb.c | 75 ++ src/arch/arm64/include/armv8/arch/arch_io.h | 2 +- src/arch/arm64/include/armv8/arch/cache.h | 174 ----- src/arch/arm64/include/armv8/arch/lib_helpers.h | 296 ++++++++ 11 files changed, 1852 insertions(+), 183 deletions(-) diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index c5f7a80..ca4562b 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -19,6 +19,8 @@ ## ################################################################################ +subdirs-y += lib/ + armv8_flags = -march=armv8-a -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_ARM_ARCH__=8 armv8_asm_flags = $(armv8_flags) diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index a0eff46..918a883 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -34,13 +34,14 @@ #include <stdint.h> #include <arch/cache.h> +#include <arch/lib_helpers.h> void tlb_invalidate_all(void) { /* TLBIALL includes dTLB and iTLB on systems that have them. */ - tlbiall(current_el()); - dsb(); - isb(); + tlbiall_current(); + dsb(); + isb(); } unsigned int dcache_line_bytes(void) @@ -51,7 +52,7 @@ unsigned int dcache_line_bytes(void) if (line_bytes) return line_bytes; - ccsidr = read_ccsidr(); + ccsidr = raw_read_ccsidr_el1(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */ line_bytes = 1 << ((ccsidr & 0x7) + 4); /* words per line */ line_bytes *= sizeof(uint32_t); /* bytes per word */ @@ -125,18 +126,18 @@ void dcache_mmu_disable(void) uint32_t sctlr; flush_dcache_all(); - sctlr = read_sctlr(current_el()); + sctlr = raw_read_sctlr_current(); sctlr &= ~(SCTLR_C | SCTLR_M); - write_sctlr(sctlr, current_el()); + raw_write_sctlr_current(sctlr); } void dcache_mmu_enable(void) { uint32_t sctlr; - sctlr = read_sctlr(current_el()); + sctlr = raw_read_sctlr_current(); sctlr |= SCTLR_C | SCTLR_M; - write_sctlr(sctlr, current_el()); + raw_write_sctlr_current(sctlr); } void cache_sync_instructions(void) diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc new file mode 100644 index 0000000..bda203b --- /dev/null +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -0,0 +1,35 @@ +################################################################################ +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## +################################################################################ + +lib_access = pstate.c sysctrl.c cache.c tlb.c misc.c + +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) +bootblock-y += $(lib_access) +endif + +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) +romstage-y += $(lib_access) +endif + +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) +ramstage-y += $(lib_access) +endif diff --git a/src/arch/arm64/armv8/lib/cache.c b/src/arch/arm64/armv8/lib/cache.c new file mode 100644 index 0000000..d4c3996 --- /dev/null +++ b/src/arch/arm64/armv8/lib/cache.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * cache.c: Cache Maintenance Instructions + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + */ + +#include <stdint.h> + +#include <arch/lib_helpers.h> + +void dccisw(uint64_t cisw) +{ + __asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) :"memory"); +} + +void dccivac(uint64_t civac) +{ + __asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) :"memory"); +} + +void dccsw(uint64_t csw) +{ + __asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) :"memory"); +} + +void dccvac(uint64_t cvac) +{ + __asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) :"memory"); +} + +void dccvau(uint64_t cvau) +{ + __asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) :"memory"); +} + +void dcisw(uint64_t isw) +{ + __asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) :"memory"); +} + +void dcivac(uint64_t ivac) +{ + __asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) :"memory"); +} + +void dczva(uint64_t zva) +{ + __asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) :"memory"); +} + +void iciallu(void) +{ + __asm__ __volatile__("ic iallu\n\t" : : :"memory"); +} + +void icialluis(void) +{ + __asm__ __volatile__("ic ialluis\n\t" : : :"memory"); +} + +void icivau(uint64_t ivau) +{ + __asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) :"memory"); +} diff --git a/src/arch/arm64/armv8/lib/misc.c b/src/arch/arm64/armv8/lib/misc.c new file mode 100644 index 0000000..da02a33 --- /dev/null +++ b/src/arch/arm64/armv8/lib/misc.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + * misc.c: Memory barrier functions + */ + +#include <stdint.h> + +#include <arch/lib_helpers.h> + + +/* + * Sync primitives + */ + +/* data memory barrier */ +void dmb(void) +{ + asm volatile ("dmb sy" : : : "memory"); +} + +/* data sync barrier */ +void dsb(void) +{ + asm volatile ("dsb sy" : : : "memory"); +} + +/* instruction sync barrier */ +void isb(void) +{ + asm volatile ("isb sy" : : : "memory"); +} diff --git a/src/arch/arm64/armv8/lib/pstate.c b/src/arch/arm64/armv8/lib/pstate.c new file mode 100644 index 0000000..a194b91 --- /dev/null +++ b/src/arch/arm64/armv8/lib/pstate.c @@ -0,0 +1,423 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + * pstate.c: This file defines all the library functions for accessing + * PSTATE and special purpose registers + */ + +#include <stdint.h> + +#include <arch/lib_helpers.h> + +/* CurrentEL */ +uint32_t raw_read_current_el(void) +{ + uint32_t current_el; + + __asm__ __volatile__("mrs %0, CurrentEL\n\t" : "=r" (current_el) : : "memory"); + + return current_el; +} + +uint32_t get_current_el(void) +{ + uint32_t current_el = raw_read_current_el(); + return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK); +} + +/* DAIF */ +uint32_t raw_read_daif(void) +{ + uint32_t daif; + + __asm__ __volatile__("mrs %0, DAIF\n\t" : "=r" (daif) : : "memory"); + + return daif; +} + +void raw_write_daif(uint32_t daif) +{ + __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory"); +} + +void enable_debug_exceptions(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" : : "i" (DAIF_DBG_BIT) : "memory"); +} + +void enable_serror_exceptions(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" : : "i" (DAIF_ABT_BIT) : "memory"); +} + +void enable_irq(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" : : "i" (DAIF_IRQ_BIT) : "memory"); +} + +void enable_fiq(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" : : "i" (DAIF_FIQ_BIT) : "memory"); +} + +void disable_debug_exceptions(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" : : "i" (DAIF_DBG_BIT) : "memory"); +} + +void disable_serror_exceptions(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" : : "i" (DAIF_ABT_BIT) : "memory"); +} + +void disable_irq(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" : : "i" (DAIF_IRQ_BIT) : "memory"); +} + +void disable_fiq(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" : : "i" (DAIF_FIQ_BIT) : "memory"); +} + +/* DLR_EL0 */ +uint64_t raw_read_dlr_el0(void) +{ + uint64_t dlr_el0; + + __asm__ __volatile__("mrs %0, DLR_EL0\n\t" : "=r" (dlr_el0) : : "memory"); + + return dlr_el0; +} +void raw_write_dlr_el0(uint64_t dlr_el0) +{ + __asm__ __volatile__("msr DLR_EL0, %0\n\t" : : "r" (dlr_el0) : "memory"); +} + +/* DSPSR_EL0 */ +uint64_t raw_read_dspsr_el0(void) +{ + uint64_t dspsr_el0; + + __asm__ __volatile__("mrs %0, DSPSR_EL0\n\t" : "=r" (dspsr_el0) : : "memory"); + + return dspsr_el0; +} +void raw_write_dspsr_el0(uint64_t dspsr_el0) +{ + __asm__ __volatile__("msr DSPSR_EL0, %0\n\t" : : "r" (dspsr_el0) : "memory"); +} + +/* ELR */ +uint64_t raw_read_elr_el1(void) +{ + uint64_t elr_el1; + + __asm__ __volatile__("mrs %0, ELR_EL1\n\t" : "=r" (elr_el1) : : "memory"); + + return elr_el1; +} + +void raw_write_elr_el1(uint64_t elr_el1) +{ + __asm__ __volatile__("msr ELR_EL1, %0\n\t" : : "r" (elr_el1) : "memory"); +} + +uint64_t raw_read_elr_el2(void) +{ + uint64_t elr_el2; + + __asm__ __volatile__("mrs %0, ELR_EL2\n\t" : "=r" (elr_el2) : : "memory"); + + return elr_el2; +} + +void raw_write_elr_el2(uint64_t elr_el2) +{ + __asm__ __volatile__("msr ELR_EL2, %0\n\t" : : "r" (elr_el2) : "memory"); +} + +uint64_t raw_read_elr_el3(void) +{ + uint64_t elr_el3; + + __asm__ __volatile__("mrs %0, ELR_EL3\n\t" : "=r" (elr_el3) : : "memory"); + + return elr_el3; +} + +void raw_write_elr_el3(uint64_t elr_el3) +{ + __asm__ __volatile__("msr ELR_EL3, %0\n\t" : : "r" (elr_el3) : "memory"); +} + +uint64_t raw_read_elr_current(void) +{ + SWITCH_CASE_READ(raw_read_elr,elr,uint64_t); +} + +void raw_write_elr_current(uint64_t elr) +{ + SWITCH_CASE_WRITE(raw_write_elr,elr); +} + +/* FPCR */ +uint32_t raw_read_fpcr(void) +{ + uint32_t fpcr; + + __asm__ __volatile__("mrs %0, FPCR\n\t" : "=r" (fpcr) : : "memory"); + + return fpcr; +} + +void raw_write_fpcr(uint32_t fpcr) +{ + __asm__ __volatile__("msr FPCR, %0\n\t" : : "r" (fpcr) : "memory"); +} + +/* FPSR */ +uint32_t raw_read_fpsr(void) +{ + uint32_t fpsr; + + __asm__ __volatile__("mrs %0, FPSR\n\t" : "=r" (fpsr) : : "memory"); + + return fpsr; +} + +void raw_write_fpsr(uint32_t fpsr) +{ + __asm__ __volatile__("msr FPSR, %0\n\t" : : "r" (fpsr) : "memory"); +} + +/* NZCV */ +uint32_t raw_read_nzcv(void) +{ + uint32_t nzcv; + + __asm__ __volatile__("mrs %0, NZCV\n\t" : "=r" (nzcv) : : "memory"); + + return nzcv; +} + +void raw_write_nzcv(uint32_t nzcv) +{ + __asm__ __volatile__("msr NZCV, %0\n\t" : : "r" (nzcv) : "memory"); +} + +/* SP */ +uint64_t raw_read_sp_el0(void) +{ + uint64_t sp_el0; + + __asm__ __volatile__("mrs %0, SP_EL0\n\t" : "=r" (sp_el0) : : "memory"); + + return sp_el0; +} + +void raw_write_sp_el0(uint64_t sp_el0) +{ + __asm__ __volatile__("msr SP_EL0, %0\n\t" : : "r" (sp_el0) : "memory"); +} + +uint64_t raw_read_sp_el1(void) +{ + uint64_t sp_el1; + + __asm__ __volatile__("mrs %0, SP_EL1\n\t" : "=r" (sp_el1) : : "memory"); + + return sp_el1; +} + +void raw_write_sp_el1(uint64_t sp_el1) +{ + __asm__ __volatile__("msr SP_EL1, %0\n\t" : : "r" (sp_el1) : "memory"); +} + +uint64_t raw_read_sp_el2(void) +{ + uint64_t sp_el2; + + __asm__ __volatile__("mrs %0, SP_EL2\n\t" : "=r" (sp_el2) : : "memory"); + + return sp_el2; +} + +void raw_write_sp_el2(uint64_t sp_el2) +{ + __asm__ __volatile__("msr SP_EL2, %0\n\t" : : "r" (sp_el2) : "memory"); +} + +/* SPSel */ +uint32_t raw_read_spsel(void) +{ + uint32_t spsel; + + __asm__ __volatile__("mrs %0, SPSel\n\t" : "=r" (spsel) : : "memory"); + + return spsel; +} + +void raw_write_spsel(uint32_t spsel) +{ + __asm__ __volatile__("msr SPSel, %0\n\t" : : "r" (spsel) : "memory"); +} + +uint64_t raw_read_sp_el3(void) +{ + uint64_t sp_el3; + uint32_t spsel; + + spsel = raw_read_spsel(); + if (!spsel) + raw_write_spsel(1); + + __asm__ __volatile__("mov %0, sp\n\t" : "=r" (sp_el3) : : "memory"); + + if (!spsel) + raw_write_spsel(spsel); + + return sp_el3; +} + +void raw_write_sp_el3(uint64_t sp_el3) +{ + uint32_t spsel; + + spsel = raw_read_spsel(); + if (!spsel) + raw_write_spsel(1); + + __asm__ __volatile__("mov sp, %0\n\t" : "=r" (sp_el3) : : "memory"); + + if (!spsel) + raw_write_spsel(spsel); +} + +/* SPSR */ +uint32_t raw_read_spsr_abt(void) +{ + uint32_t spsr_abt; + + __asm__ __volatile__("mrs %0, SPSR_abt\n\t" : "=r" (spsr_abt) : : "memory"); + + return spsr_abt; +} + +void raw_write_spsr_abt(uint32_t spsr_abt) +{ + __asm__ __volatile__("msr SPSR_abt, %0\n\t" : : "r" (spsr_abt) : "memory"); +} + +uint32_t raw_read_spsr_el1(void) +{ + uint32_t spsr_el1; + + __asm__ __volatile__("mrs %0, SPSR_EL1\n\t" : "=r" (spsr_el1) : : "memory"); + + return spsr_el1; +} + +void raw_write_spsr_el1(uint32_t spsr_el1) +{ + __asm__ __volatile__("msr SPSR_EL1, %0\n\t" : : "r" (spsr_el1) : "memory"); +} + +uint32_t raw_read_spsr_el2(void) +{ + uint32_t spsr_el2; + + __asm__ __volatile__("mrs %0, SPSR_EL2\n\t" : "=r" (spsr_el2) : : "memory"); + + return spsr_el2; +} + +void raw_write_spsr_el2(uint32_t spsr_el2) +{ + __asm__ __volatile__("msr SPSR_EL2, %0\n\t" : : "r" (spsr_el2) : "memory"); +} + +uint32_t raw_read_spsr_el3(void) +{ + uint32_t spsr_el3; + + __asm__ __volatile__("mrs %0, SPSR_EL3\n\t" : "=r" (spsr_el3) : : "memory"); + + return spsr_el3; +} + +void raw_write_spsr_el3(uint32_t spsr_el3) +{ + __asm__ __volatile__("msr SPSR_EL3, %0\n\t" : : "r" (spsr_el3) : "memory"); +} + +uint32_t raw_read_spsr_current(void) +{ + SWITCH_CASE_READ(raw_read_spsr,spsr,uint32_t); +} + +void raw_write_spsr_current(uint32_t spsr) +{ + SWITCH_CASE_WRITE(raw_write_spsr,spsr); +} + +uint32_t raw_read_spsr_fiq(void) +{ + uint32_t spsr_fiq; + + __asm__ __volatile__("mrs %0, SPSR_fiq\n\t" : "=r" (spsr_fiq) : : "memory"); + + return spsr_fiq; +} + +void raw_write_spsr_fiq(uint32_t spsr_fiq) +{ + __asm__ __volatile__("msr SPSR_fiq, %0\n\t" : : "r" (spsr_fiq) : "memory"); +} + +uint32_t raw_read_spsr_irq(void) +{ + uint32_t spsr_irq; + + __asm__ __volatile__("mrs %0, SPSR_irq\n\t" : "=r" (spsr_irq) : : "memory"); + + return spsr_irq; +} + +void raw_write_spsr_irq(uint32_t spsr_irq) +{ + __asm__ __volatile__("msr SPSR_irq, %0\n\t" : : "r" (spsr_irq) : "memory"); +} + +uint32_t raw_read_spsr_und(void) +{ + uint32_t spsr_und; + + __asm__ __volatile__("mrs %0, SPSR_und\n\t" : "=r" (spsr_und) : : "memory"); + + return spsr_und; +} + +void raw_write_spsr_und(uint32_t spsr_und) +{ + __asm__ __volatile__("msr SPSR_und, %0\n\t" : : "r" (spsr_und) : "memory"); +} diff --git a/src/arch/arm64/armv8/lib/sysctrl.c b/src/arch/arm64/armv8/lib/sysctrl.c new file mode 100644 index 0000000..deb991f --- /dev/null +++ b/src/arch/arm64/armv8/lib/sysctrl.c @@ -0,0 +1,871 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + * sysctrl.c: This file defines all the library functions for accessing system + * control registers in Aarch64 + */ + +#include <stdint.h> + +#include <arch/lib_helpers.h> + +/* ACTLR */ +uint32_t raw_read_actlr_el1(void) +{ + uint32_t actlr_el1; + + __asm__ __volatile__("mrs %0, ACTLR_EL1\n\t" : "=r" (actlr_el1) : : "memory"); + + return actlr_el1; +} + +void raw_write_actlr_el1(uint32_t actlr_el1) +{ + __asm__ __volatile__("msr ACTLR_EL1, %0\n\t" : : "r" (actlr_el1) : "memory"); +} + +uint32_t raw_read_actlr_el2(void) +{ + uint32_t actlr_el2; + + __asm__ __volatile__("mrs %0, ACTLR_EL2\n\t" : "=r" (actlr_el2) : : "memory"); + + return actlr_el2; +} + +void raw_write_actlr_el2(uint32_t actlr_el2) +{ + __asm__ __volatile__("msr ACTLR_EL2, %0\n\t" : : "r" (actlr_el2) : "memory"); +} + +uint32_t raw_read_actlr_el3(void) +{ + uint32_t actlr_el3; + + __asm__ __volatile__("mrs %0, ACTLR_EL3\n\t" : "=r" (actlr_el3) : : "memory"); + + return actlr_el3; +} + +void raw_write_actlr_el3(uint32_t actlr_el3) +{ + __asm__ __volatile__("msr ACTLR_EL3, %0\n\t" : : "r" (actlr_el3) : "memory"); +} + +uint32_t raw_read_actlr_current(void) +{ + SWITCH_CASE_READ(raw_read_actlr,actlr,uint32_t); +} + +void raw_write_actlr_current(uint32_t actlr) +{ + SWITCH_CASE_WRITE(raw_write_actlr,actlr); +} + +/* AFSR0 */ +uint32_t raw_read_afsr0_el1(void) +{ + uint32_t afsr0_el1; + + __asm__ __volatile__("mrs %0, AFSR0_EL1\n\t" : "=r" (afsr0_el1) : : "memory"); + + return afsr0_el1; +} + +void raw_write_afsr0_el1(uint32_t afsr0_el1) +{ + __asm__ __volatile__("msr AFSR0_EL1, %0\n\t" : : "r" (afsr0_el1) : "memory"); +} + +uint32_t raw_read_afsr0_el2(void) +{ + uint32_t afsr0_el2; + + __asm__ __volatile__("mrs %0, AFSR0_EL2\n\t" : "=r" (afsr0_el2) : : "memory"); + + return afsr0_el2; +} + +void raw_write_afsr0_el2(uint32_t afsr0_el2) +{ + __asm__ __volatile__("msr AFSR0_EL2, %0\n\t" : : "r" (afsr0_el2) : "memory"); +} + +uint32_t raw_read_afsr0_el3(void) +{ + uint32_t afsr0_el3; + + __asm__ __volatile__("mrs %0, AFSR0_EL3\n\t" : "=r" (afsr0_el3) : : "memory"); + + return afsr0_el3; +} + +void raw_write_afsr0_el3(uint32_t afsr0_el3) +{ + __asm__ __volatile__("msr AFSR0_EL3, %0\n\t" : : "r" (afsr0_el3) : "memory"); +} + +uint32_t raw_read_afsr0_current(void) +{ + SWITCH_CASE_READ(raw_read_afsr0,afsr0,uint32_t); +} + +void raw_write_afsr0_current(uint32_t afsr0) +{ + SWITCH_CASE_WRITE(raw_write_afsr0,afsr0); +} + +/* AFSR1 */ +uint32_t raw_read_afsr1_el1(void) +{ + uint32_t afsr1_el1; + + __asm__ __volatile__("mrs %0, AFSR1_EL1\n\t" : "=r" (afsr1_el1) : : "memory"); + + return afsr1_el1; +} + +void raw_write_afsr1_el1(uint32_t afsr1_el1) +{ + __asm__ __volatile__("msr AFSR1_EL1, %0\n\t" : : "r" (afsr1_el1) : "memory"); +} + +uint32_t raw_read_afsr1_el2(void) +{ + uint32_t afsr1_el2; + + __asm__ __volatile__("mrs %0, AFSR1_EL2\n\t" : "=r" (afsr1_el2) : : "memory"); + + return afsr1_el2; +} + +void raw_write_afsr1_el2(uint32_t afsr1_el2) +{ + __asm__ __volatile__("msr AFSR1_EL2, %0\n\t" : : "r" (afsr1_el2) : "memory"); +} + +uint32_t raw_read_afsr1_el3(void) +{ + uint32_t afsr1_el3; + + __asm__ __volatile__("mrs %0, AFSR1_EL3\n\t" : "=r" (afsr1_el3) : : "memory"); + + return afsr1_el3; +} + +void raw_write_afsr1_el3(uint32_t afsr1_el3) +{ + __asm__ __volatile__("msr AFSR1_EL3, %0\n\t" : : "r" (afsr1_el3) : "memory"); +} + +uint32_t raw_read_afsr1_current(void) +{ + SWITCH_CASE_READ(raw_read_afsr1,afsr1,uint32_t); +} + +void raw_write_afsr1_current(uint32_t afsr1) +{ + SWITCH_CASE_WRITE(raw_write_afsr1,afsr1); +} + +/* AIDR */ +uint32_t raw_read_aidr_el1(void) +{ + uint32_t aidr_el1; + + __asm__ __volatile__("mrs %0, AIDR_EL1\n\t" : "=r" (aidr_el1) : : "memory"); + + return aidr_el1; +} + +/* AMAIR */ +uint64_t raw_read_amair_el1(void) +{ + uint64_t amair_el1; + + __asm__ __volatile__("mrs %0, AMAIR_EL1\n\t" : "=r" (amair_el1) : : "memory"); + + return amair_el1; +} + +void raw_write_amair_el1(uint64_t amair_el1) +{ + __asm__ __volatile__("msr AMAIR_EL1, %0\n\t" : : "r" (amair_el1) : "memory"); +} + +uint64_t raw_read_amair_el2(void) +{ + uint64_t amair_el2; + + __asm__ __volatile__("mrs %0, AMAIR_EL2\n\t" : "=r" (amair_el2) : : "memory"); + + return amair_el2; +} + +void raw_write_amair_el2(uint64_t amair_el2) +{ + __asm__ __volatile__("msr AMAIR_EL2, %0\n\t" : : "r" (amair_el2) : "memory"); +} + +uint64_t raw_read_amair_el3(void) +{ + uint64_t amair_el3; + + __asm__ __volatile__("mrs %0, AMAIR_EL3\n\t" : "=r" (amair_el3) : : "memory"); + + return amair_el3; +} + +void raw_write_amair_el3(uint64_t amair_el3) +{ + __asm__ __volatile__("msr AMAIR_EL3, %0\n\t" : : "r" (amair_el3) : "memory"); +} + +uint64_t raw_read_amair_current(void) +{ + SWITCH_CASE_READ(raw_read_amair,amair,uint64_t); +} + +void raw_write_amair_current(uint64_t amair) +{ + SWITCH_CASE_WRITE(raw_write_amair,amair); +} + +/* CCSIDR */ +uint32_t raw_read_ccsidr_el1(void) +{ + uint32_t ccsidr_el1; + + __asm__ __volatile__("mrs %0, CCSIDR_EL1\n\t" : "=r" (ccsidr_el1) : : "memory"); + + return ccsidr_el1; +} + +/* CLIDR */ +uint32_t raw_read_clidr_el1(void) +{ + uint32_t clidr_el1; + + __asm__ __volatile__("mrs %0, CLIDR_EL1\n\t" : "=r" (clidr_el1) : : "memory"); + + return clidr_el1; +} + +/* CPACR */ +uint32_t raw_read_cpacr_el1(void) +{ + uint32_t cpacr_el1; + + __asm__ __volatile__("mrs %0, CPACR_EL1\n\t" : "=r" (cpacr_el1) : : "memory"); + + return cpacr_el1; +} + +void raw_write_cpacr_el1(uint32_t cpacr_el1) +{ + __asm__ __volatile__("msr CPACR_EL1, %0\n\t" : : "r" (cpacr_el1) : "memory"); +} + +/* CPTR */ +uint32_t raw_read_cptr_el2(void) +{ + uint32_t cptr_el2; + + __asm__ __volatile__("mrs %0, CPTR_EL2\n\t" : "=r" (cptr_el2) : : "memory"); + + return cptr_el2; +} + +void raw_write_cptr_el2(uint32_t cptr_el2) +{ + __asm__ __volatile__("msr CPTR_EL2, %0\n\t" : : "r" (cptr_el2) : "memory"); +} + +uint32_t raw_read_cptr_el3(void) +{ + uint32_t cptr_el3; + + __asm__ __volatile__("mrs %0, CPTR_EL3\n\t" : "=r" (cptr_el3) : : "memory"); + + return cptr_el3; +} + +void raw_write_cptr_el3(uint32_t cptr_el3) +{ + __asm__ __volatile__("msr CPTR_EL3, %0\n\t" : : "r" (cptr_el3) : "memory"); +} + +/* CSSELR */ +uint32_t raw_read_csselr_el1(void) +{ + uint32_t csselr_el1; + + __asm__ __volatile__("mrs %0, CSSELR_EL1\n\t" : "=r" (csselr_el1) : : "memory"); + + return csselr_el1; +} + +void raw_write_csselr_el1(uint32_t csselr_el1) +{ + __asm__ __volatile__("msr CSSELR_EL1, %0\n\t" : : "r" (csselr_el1) : "memory"); +} + +/* CTR */ +uint32_t raw_read_ctr_el0(void) +{ + uint32_t ctr_el0; + + __asm__ __volatile__("mrs %0, CTR_EL0\n\t" : "=r" (ctr_el0) : : "memory"); + + return ctr_el0; +} + +/* ESR */ +uint32_t raw_read_esr_el1(void) +{ + uint32_t esr_el1; + + __asm__ __volatile__("mrs %0, ESR_EL1\n\t" : "=r" (esr_el1) : : "memory"); + + return esr_el1; +} + +void raw_write_esr_el1(uint32_t esr_el1) +{ + __asm__ __volatile__("msr ESR_EL1, %0\n\t" : : "r" (esr_el1) : "memory"); +} + +uint32_t raw_read_esr_el2(void) +{ + uint32_t esr_el2; + + __asm__ __volatile__("mrs %0, ESR_EL2\n\t" : "=r" (esr_el2) : : "memory"); + + return esr_el2; +} + +void raw_write_esr_el2(uint32_t esr_el2) +{ + __asm__ __volatile__("msr ESR_EL2, %0\n\t" : : "r" (esr_el2) : "memory"); +} + +uint32_t raw_read_esr_el3(void) +{ + uint32_t esr_el3; + + __asm__ __volatile__("mrs %0, ESR_EL3\n\t" : "=r" (esr_el3) : : "memory"); + + return esr_el3; +} + +void raw_write_esr_el3(uint32_t esr_el3) +{ + __asm__ __volatile__("msr ESR_EL3, %0\n\t" : : "r" (esr_el3) : "memory"); +} + +uint32_t raw_read_esr_current(void) +{ + SWITCH_CASE_READ(raw_read_esr,esr,uint32_t); +} + +void raw_write_esr_current(uint32_t esr) +{ + SWITCH_CASE_WRITE(raw_write_esr,esr); +} + +/* FAR */ +uint64_t raw_read_far_el1(void) +{ + uint64_t far_el1; + + __asm__ __volatile__("mrs %0, FAR_EL1\n\t" : "=r" (far_el1) : : "memory"); + + return far_el1; +} + +void raw_write_far_el1(uint64_t far_el1) +{ + __asm__ __volatile__("msr FAR_EL1, %0\n\t" : : "r" (far_el1) : "memory"); +} + +uint64_t raw_read_far_el2(void) +{ + uint64_t far_el2; + + __asm__ __volatile__("mrs %0, FAR_EL2\n\t" : "=r" (far_el2) : : "memory"); + + return far_el2; +} + +void raw_write_far_el2(uint64_t far_el2) +{ + __asm__ __volatile__("msr FAR_EL2, %0\n\t" : : "r" (far_el2) : "memory"); +} + +uint64_t raw_read_far_el3(void) +{ + uint64_t far_el3; + + __asm__ __volatile__("mrs %0, FAR_EL3\n\t" : "=r" (far_el3) : : "memory"); + + return far_el3; +} + +void raw_write_far_el3(uint64_t far_el3) +{ + __asm__ __volatile__("msr FAR_EL3, %0\n\t" : : "r" (far_el3) : "memory"); +} + +uint64_t raw_read_far_current(void) +{ + SWITCH_CASE_READ(raw_read_far,far,uint64_t); +} + +void raw_write_far_current(uint64_t far) +{ + SWITCH_CASE_WRITE(raw_write_far,far); +} + +/* HCR */ +uint64_t raw_read_hcr_el2(void) +{ + uint64_t hcr_el2; + + __asm__ __volatile__("mrs %0, HCR_EL2\n\t" : "=r" (hcr_el2) : : "memory"); + + return hcr_el2; +} + +void raw_write_hcr_el2(uint64_t hcr_el2) +{ + __asm__ __volatile__("msr HCR_EL2, %0\n\t" : : "r" (hcr_el2) : "memory"); +} + +/* AA64PFR0 */ +uint64_t raw_read_aa64pfr0_el1(void) +{ + uint64_t aa64pfr0_el1; + + __asm__ __volatile__("mrs %0, ID_AA64PFR0_EL1\n\t" : "=r" (aa64pfr0_el1) : : "memory"); + + return aa64pfr0_el1; +} + +/* MAIR */ +uint64_t raw_read_mair_el1(void) +{ + uint64_t mair_el1; + + __asm__ __volatile__("mrs %0, MAIR_EL1\n\t" : "=r" (mair_el1) : : "memory"); + + return mair_el1; +} + +void raw_write_mair_el1(uint64_t mair_el1) +{ + __asm__ __volatile__("msr MAIR_EL1, %0\n\t" : : "r" (mair_el1) : "memory"); +} + +uint64_t raw_read_mair_el2(void) +{ + uint64_t mair_el2; + + __asm__ __volatile__("mrs %0, MAIR_EL2\n\t" : "=r" (mair_el2) : : "memory"); + + return mair_el2; +} + +void raw_write_mair_el2(uint64_t mair_el2) +{ + __asm__ __volatile__("msr MAIR_EL2, %0\n\t" : : "r" (mair_el2) : "memory"); +} + +uint64_t raw_read_mair_el3(void) +{ + uint64_t mair_el3; + + __asm__ __volatile__("mrs %0, MAIR_EL3\n\t" : "=r" (mair_el3) : : "memory"); + + return mair_el3; +} + +void raw_write_mair_el3(uint64_t mair_el3) +{ + __asm__ __volatile__("msr MAIR_EL3, %0\n\t" : : "r" (mair_el3) : "memory"); +} + +uint64_t raw_read_mair_current(void) +{ + SWITCH_CASE_READ(raw_read_mair,mair,uint64_t); +} + +void raw_write_mair_current(uint64_t mair) +{ + SWITCH_CASE_WRITE(raw_write_mair,mair); +} + +/* MPIDR */ +uint64_t raw_read_mpidr_el1(void) +{ + uint64_t mpidr_el1; + + __asm__ __volatile__("mrs %0, MPIDR_EL1\n\t" : "=r" (mpidr_el1) : : "memory"); + + return mpidr_el1; +} + +/* RMR */ +uint32_t raw_read_rmr_el1(void) +{ + uint32_t rmr_el1; + + __asm__ __volatile__("mrs %0, RMR_EL1\n\t" : "=r" (rmr_el1) : : "memory"); + + return rmr_el1; +} + +void raw_write_rmr_el1(uint32_t rmr_el1) +{ + __asm__ __volatile__("msr RMR_EL1, %0\n\t" : : "r" (rmr_el1) : "memory"); +} + +uint32_t raw_read_rmr_el2(void) +{ + uint32_t rmr_el2; + + __asm__ __volatile__("mrs %0, RMR_EL2\n\t" : "=r" (rmr_el2) : : "memory"); + + return rmr_el2; +} + +void raw_write_rmr_el2(uint32_t rmr_el2) +{ + __asm__ __volatile__("msr RMR_EL2, %0\n\t" : : "r" (rmr_el2) : "memory"); +} + +uint32_t raw_read_rmr_el3(void) +{ + uint32_t rmr_el3; + + __asm__ __volatile__("mrs %0, RMR_EL3\n\t" : "=r" (rmr_el3) : : "memory"); + + return rmr_el3; +} + +void raw_write_rmr_el3(uint32_t rmr_el3) +{ + __asm__ __volatile__("msr RMR_EL3, %0\n\t" : : "r" (rmr_el3) : "memory"); +} + +uint32_t raw_read_rmr_current(void) +{ + SWITCH_CASE_READ(raw_read_rmr,rmr,uint32_t); +} + +void raw_write_rmr_current(uint32_t rmr) +{ + SWITCH_CASE_WRITE(raw_write_rmr,rmr); +} + +/* RVBAR */ +uint64_t raw_read_rvbar_el1(void) +{ + uint64_t rvbar_el1; + + __asm__ __volatile__("mrs %0, RVBAR_EL1\n\t" : "=r" (rvbar_el1) : : "memory"); + + return rvbar_el1; +} + +void raw_write_rvbar_el1(uint64_t rvbar_el1) +{ + __asm__ __volatile__("msr RVBAR_EL1, %0\n\t" : : "r" (rvbar_el1) : "memory"); +} + +uint64_t raw_read_rvbar_el2(void) +{ + uint64_t rvbar_el2; + + __asm__ __volatile__("mrs %0, RVBAR_EL2\n\t" : "=r" (rvbar_el2) : : "memory"); + + return rvbar_el2; +} + +void raw_write_rvbar_el2(uint64_t rvbar_el2) +{ + __asm__ __volatile__("msr RVBAR_EL2, %0\n\t" : : "r" (rvbar_el2) : "memory"); +} + +uint64_t raw_read_rvbar_el3(void) +{ + uint64_t rvbar_el3; + + __asm__ __volatile__("mrs %0, RVBAR_EL3\n\t" : "=r" (rvbar_el3) : : "memory"); + + return rvbar_el3; +} + +void raw_write_rvbar_el3(uint64_t rvbar_el3) +{ + __asm__ __volatile__("msr RVBAR_EL3, %0\n\t" : : "r" (rvbar_el3) : "memory"); +} + +uint64_t raw_read_rvbar_current(void) +{ + SWITCH_CASE_READ(raw_read_rvbar,rvbar,uint64_t); +} + +void raw_write_rvbar_current(uint64_t rvbar) +{ + SWITCH_CASE_WRITE(raw_write_rvbar,rvbar); +} + +/* SCR */ +uint32_t raw_read_scr_el3(void) +{ + uint32_t scr_el3; + + __asm__ __volatile__("mrs %0, SCR_EL3\n\t" : "=r" (scr_el3) : : "memory"); + + return scr_el3; +} + +void raw_write_scr_el3(uint32_t scr_el3) +{ + __asm__ __volatile__("msr SCR_EL3, %0\n\t" : : "r" (scr_el3) : "memory"); +} + +/* SCTLR */ +uint32_t raw_read_sctlr_el1(void) +{ + uint32_t sctlr_el1; + + __asm__ __volatile__("mrs %0, SCTLR_EL1\n\t" : "=r" (sctlr_el1) : : "memory"); + + return sctlr_el1; +} + +void raw_write_sctlr_el1(uint32_t sctlr_el1) +{ + __asm__ __volatile__("msr SCTLR_EL1, %0\n\t" : : "r" (sctlr_el1) : "memory"); +} + +uint32_t raw_read_sctlr_el2(void) +{ + uint32_t sctlr_el2; + + __asm__ __volatile__("mrs %0, SCTLR_EL2\n\t" : "=r" (sctlr_el2) : : "memory"); + + return sctlr_el2; +} + +void raw_write_sctlr_el2(uint32_t sctlr_el2) +{ + __asm__ __volatile__("msr SCTLR_EL2, %0\n\t" : : "r" (sctlr_el2) : "memory"); +} + +uint32_t raw_read_sctlr_el3(void) +{ + uint32_t sctlr_el3; + + __asm__ __volatile__("mrs %0, SCTLR_EL3\n\t" : "=r" (sctlr_el3) : : "memory"); + + return sctlr_el3; +} + +void raw_write_sctlr_el3(uint32_t sctlr_el3) +{ + __asm__ __volatile__("msr SCTLR_EL3, %0\n\t" : : "r" (sctlr_el3) : "memory"); +} + +uint32_t raw_read_sctlr_current(void) +{ + SWITCH_CASE_READ(raw_read_sctlr,sctlr,uint32_t); +} + +void raw_write_sctlr_current(uint32_t sctlr) +{ + SWITCH_CASE_WRITE(raw_write_sctlr,sctlr); +} + +/* TCR */ +uint64_t raw_read_tcr_el1(void) +{ + uint64_t tcr_el1; + + __asm__ __volatile__("mrs %0, TCR_EL1\n\t" : "=r" (tcr_el1) : : "memory"); + + return tcr_el1; +} + +void raw_write_tcr_el1(uint64_t tcr_el1) +{ + __asm__ __volatile__("msr TCR_EL1, %0\n\t" : : "r" (tcr_el1) : "memory"); +} + +uint32_t raw_read_tcr_el2(void) +{ + uint32_t tcr_el2; + + __asm__ __volatile__("mrs %0, TCR_EL2\n\t" : "=r" (tcr_el2) : : "memory"); + + return tcr_el2; +} + +void raw_write_tcr_el2(uint32_t tcr_el2) +{ + __asm__ __volatile__("msr TCR_EL2, %0\n\t" : : "r" (tcr_el2) : "memory"); +} + +uint32_t raw_read_tcr_el3(void) +{ + uint32_t tcr_el3; + + __asm__ __volatile__("mrs %0, TCR_EL3\n\t" : "=r" (tcr_el3) : : "memory"); + + return tcr_el3; +} + +void raw_write_tcr_el3(uint32_t tcr_el3) +{ + __asm__ __volatile__("msr TCR_EL3, %0\n\t" : : "r" (tcr_el3) : "memory"); +} + +/* TTBR0 */ +uint64_t raw_read_ttbr0_el1(void) +{ + uint64_t ttbr0_el1; + + __asm__ __volatile__("mrs %0, TTBR0_EL1\n\t" : "=r" (ttbr0_el1) : : "memory"); + + return ttbr0_el1; +} + +void raw_write_ttbr0_el1(uint64_t ttbr0_el1) +{ + __asm__ __volatile__("msr TTBR0_EL1, %0\n\t" : : "r" (ttbr0_el1) : "memory"); +} + +uint64_t raw_read_ttbr0_el2(void) +{ + uint64_t ttbr0_el2; + + __asm__ __volatile__("mrs %0, TTBR0_EL2\n\t" : "=r" (ttbr0_el2) : : "memory"); + + return ttbr0_el2; +} + +void raw_write_ttbr0_el2(uint64_t ttbr0_el2) +{ + __asm__ __volatile__("msr TTBR0_EL2, %0\n\t" : : "r" (ttbr0_el2) : "memory"); +} + +uint64_t raw_read_ttbr0_el3(void) +{ + uint64_t ttbr0_el3; + + __asm__ __volatile__("mrs %0, TTBR0_EL3\n\t" : "=r" (ttbr0_el3) : : "memory"); + + return ttbr0_el3; +} + +void raw_write_ttbr0_el3(uint64_t ttbr0_el3) +{ + __asm__ __volatile__("msr TTBR0_EL3, %0\n\t" : : "r" (ttbr0_el3) : "memory"); +} + +uint64_t raw_read_ttbr0_current(void) +{ + SWITCH_CASE_READ(raw_read_ttbr0,ttbr0,uint64_t); +} + +void raw_write_ttbr0_current(uint64_t ttbr0) +{ + SWITCH_CASE_WRITE(raw_write_ttbr0,ttbr0); +} + +/* TTBR1 */ +uint64_t raw_read_ttbr1_el1(void) +{ + uint64_t ttbr1_el1; + + __asm__ __volatile__("mrs %0, TTBR1_EL1\n\t" : "=r" (ttbr1_el1) : : "memory"); + + return ttbr1_el1; +} + +void raw_write_ttbr1_el1(uint64_t ttbr1_el1) +{ + __asm__ __volatile__("msr TTBR1_EL1, %0\n\t" : : "r" (ttbr1_el1) : "memory"); +} + +/* VBAR */ +uint64_t raw_read_vbar_el1(void) +{ + uint64_t vbar_el1; + + __asm__ __volatile__("mrs %0, VBAR_EL1\n\t" : "=r" (vbar_el1) : : "memory"); + + return vbar_el1; +} + +void raw_write_vbar_el1(uint64_t vbar_el1) +{ + __asm__ __volatile__("msr VBAR_EL1, %0\n\t" : : "r" (vbar_el1) : "memory"); +} + +uint64_t raw_read_vbar_el2(void) +{ + uint64_t vbar_el2; + + __asm__ __volatile__("mrs %0, VBAR_EL2\n\t" : "=r" (vbar_el2) : : "memory"); + + return vbar_el2; +} + +void raw_write_vbar_el2(uint64_t vbar_el2) +{ + __asm__ __volatile__("msr VBAR_EL2, %0\n\t" : : "r" (vbar_el2) : "memory"); +} + +uint64_t raw_read_vbar_el3(void) +{ + uint64_t vbar_el3; + + __asm__ __volatile__("mrs %0, VBAR_EL3\n\t" : "=r" (vbar_el3) : : "memory"); + + return vbar_el3; +} + +void raw_write_vbar_el3(uint64_t vbar_el3) +{ + __asm__ __volatile__("msr VBAR_EL3, %0\n\t" : : "r" (vbar_el3) : "memory"); +} + +uint64_t raw_read_vbar_current(void) +{ + SWITCH_CASE_READ(raw_read_vbar,vbar,uint64_t); +} + +void raw_write_vbar_current(uint64_t vbar) +{ + SWITCH_CASE_WRITE(raw_write_vbar,vbar); +} diff --git a/src/arch/arm64/armv8/lib/tlb.c b/src/arch/arm64/armv8/lib/tlb.c new file mode 100644 index 0000000..36d1e70 --- /dev/null +++ b/src/arch/arm64/armv8/lib/tlb.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * tlb.c: System intructions for TLB maintenance. + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + */ + +#include <stdint.h> + +#include <arch/lib_helpers.h> + +/* TLBIALL */ +void tlbiall_el1(void) +{ + __asm__ __volatile__("tlbi alle1\n\t" : : : "memory"); +} + +void tlbiall_el2(void) +{ + __asm__ __volatile__("tlbi alle2\n\t" : : : "memory"); +} + +void tlbiall_el3(void) +{ + __asm__ __volatile__("tlbi alle3\n\t" : : : "memory"); +} + +void tlbiall_current(void) +{ + SWITCH_CASE_TLBI(tlbiall); +} + +/* TLBIALLIS */ +void tlbiallis_el1(void) +{ + __asm__ __volatile__("tlbi alle1is\n\t" : : : "memory"); +} + +void tlbiallis_el2(void) +{ + __asm__ __volatile__("tlbi alle2is\n\t" : : : "memory"); +} + +void tlbiallis_el3(void) +{ + __asm__ __volatile__("tlbi alle3is\n\t" : : : "memory"); +} + +void tlbiallis_current(void) +{ + SWITCH_CASE_TLBI(tlbiallis); +} + +/* TLBIVAA */ +void tlbivaa_el1(uint64_t va) +{ + __asm__ __volatile__("tlbi vaae1, %0\n\t" : : "r" (va) : "memory"); +} diff --git a/src/arch/arm64/include/armv8/arch/arch_io.h b/src/arch/arm64/include/armv8/arch/arch_io.h index 56ed86d..2876c8b 100644 --- a/src/arch/arm64/include/armv8/arch/arch_io.h +++ b/src/arch/arm64/include/armv8/arch/arch_io.h @@ -23,8 +23,8 @@ #ifndef __ASM_ARM64_ARCH_IO_H #define __ASM_ARM64_ARCH_IO_H -#include <arch/cache.h> /* for dmb() */ #include <stdint.h> +#include <arch/lib_helpers.h> static inline uint8_t read8(const void *addr) { diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 325b857..977edba 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -57,180 +57,6 @@ #define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */ #define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */ -/* - * Utility macro to choose an instruction according to the exception - * level (EL) passed, which number is concatenated between insa and insb parts - */ -#define SWITCH_EL(insa, insb, el) if (el == 1) asm volatile(insa "1" insb); \ - else if (el == 2) asm volatile (insa "2" insb); \ - else asm volatile (insa "3" insb) - -/* get current exception level (EL1-EL3) */ -static inline uint32_t current_el(void) -{ - uint32_t el; - asm volatile ("mrs %0, CurrentEL" : "=r" (el)); - return el >> 2; -} - -/* - * Sync primitives - */ - -/* data memory barrier */ -static inline void dmb(void) -{ - asm volatile ("dmb sy" : : : "memory"); -} - -/* data sync barrier */ -static inline void dsb(void) -{ - asm volatile ("dsb sy" : : : "memory"); -} - -/* instruction sync barrier */ -static inline void isb(void) -{ - asm volatile ("isb sy" : : : "memory"); -} - -/* - * Low-level TLB maintenance operations - */ - -/* invalidate entire unified TLB */ -static inline void tlbiall(uint32_t el) -{ - SWITCH_EL("tlbi alle", : : : "memory", el); -} - -/* invalidate unified TLB by VA, all ASID (EL1) */ -static inline void tlbivaa(uint64_t va) -{ - asm volatile("tlbi vaae1, %0" : : "r" (va) : "memory"); -} - -/* write translation table base register 0 (TTBR0_ELx) */ -static inline void write_ttbr0(uint64_t val, uint32_t el) -{ - SWITCH_EL("msr ttbr0_el", ", %0" : : "r" (val) : "memory", el); -} - -/* read translation control register (TCR_ELx) */ -static inline uint64_t read_tcr(uint32_t el) -{ - uint64_t val = 0; - SWITCH_EL("mrs %0, tcr_el", : "=r" (val), el); - return val; -} - -/* write translation control register (TCR_ELx) */ -static inline void write_tcr(uint64_t val, uint32_t el) -{ - SWITCH_EL("msr tcr_el", ", %0" : : "r" (val) : "memory", el); -} - -/* - * Low-level cache maintenance operations - */ - -/* data cache clean and invalidate by VA to PoC */ -static inline void dccivac(uint64_t va) -{ - asm volatile ("dc civac, %0" : : "r" (va) : "memory"); -} - -/* data cache clean and invalidate by set/way */ -static inline void dccisw(uint64_t val) -{ - asm volatile ("dc cisw, %0" : : "r" (val) : "memory"); -} - -/* data cache clean by VA to PoC */ -static inline void dccvac(uint64_t va) -{ - asm volatile ("dc cvac, %0" : : "r" (va) : "memory"); -} - -/* data cache clean by set/way */ -static inline void dccsw(uint64_t val) -{ - asm volatile ("dc csw, %0" : : "r" (val) : "memory"); -} - -/* data cache invalidate by VA to PoC */ -static inline void dcivac(uint64_t va) -{ - asm volatile ("dc ivac, %0" : : "r" (va) : "memory"); -} - -/* data cache invalidate by set/way */ -static inline void dcisw(uint64_t val) -{ - asm volatile ("dc isw, %0" : : "r" (val) : "memory"); -} - -/* instruction cache invalidate all */ -static inline void iciallu(void) -{ - asm volatile ("ic iallu" : : : "memory"); -} - -/* - * Cache registers functions - */ - -/* read cache level ID register (CLIDR_EL1) */ -static inline uint32_t read_clidr(void) -{ - uint32_t val = 0; - asm volatile ("mrs %0, clidr_el1" : "=r" (val)); - return val; -} - -/* read cache size ID register register (CCSIDR_EL1) */ -static inline uint32_t read_ccsidr(void) -{ - uint32_t val = 0; - asm volatile ("mrs %0, ccsidr_el1" : "=r" (val)); - return val; -} - -/* read cache size selection register (CSSELR_EL1) */ -static inline uint32_t read_csselr(void) -{ - uint32_t val = 0; - asm volatile ("mrs %0, csselr_el1" : "=r" (val)); - return val; -} - -/* write to cache size selection register (CSSELR_EL1) */ -static inline void write_csselr(uint32_t val) -{ - /* - * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) - * Bit 0 - 0 = data or unified cache, 1 = instruction cache - */ - asm volatile ("msr csselr_el1, %0" : : "r" (val)); - isb(); /* ISB to sync the change to CCSIDR_EL1 */ -} - -/* read system control register (SCTLR_ELx) */ -static inline uint32_t read_sctlr(uint32_t el) -{ - uint32_t val; - SWITCH_EL("mrs %0, sctlr_el", : "=r" (val), el); - return val; -} - -/* write system control register (SCTLR_ELx) */ -static inline void write_sctlr(uint32_t val, uint32_t el) -{ - SWITCH_EL("msr sctlr_el", ", %0" : : "r" (val) : "cc", el); - isb(); -} - /* dcache clean by virtual address to PoC */ void dcache_clean_by_va(void const *addr, size_t len); diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h new file mode 100644 index 0000000..8c6198f --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * lib_helpers.h: All library function prototypes and macros are defined in this + * file. + */ + +#define EL0 0 +#define EL1 1 +#define EL2 2 +#define EL3 3 + +#define CURRENT_EL_MASK 0x3 +#define CURRENT_EL_SHIFT 2 + +#define DAIF_DBG_BIT (1<<3) +#define DAIF_ABT_BIT (1<<2) +#define DAIF_IRQ_BIT (1<<1) +#define DAIF_FIQ_BIT (1<<0) + +#define SWITCH_CASE_READ(func,var,type) do { \ + type var = -1; \ + uint8_t current_el = get_current_el(); \ + switch(current_el) { \ + case EL1: \ + var = func##_el1(); \ + break; \ + case EL2: \ + var = func##_el2(); \ + break; \ + case EL3: \ + var = func##_el3(); \ + break; \ + } \ + return var; \ + } while(0) + +#define SWITCH_CASE_WRITE(func,var) do { \ + uint8_t current_el = get_current_el(); \ + switch(current_el) { \ + case EL1: \ + func##_el1(var); \ + break; \ + case EL2: \ + func##_el2(var); \ + break; \ + case EL3: \ + func##_el3(var); \ + break; \ + } \ + } while(0) + +#define SWITCH_CASE_TLBI(func) do { \ + uint8_t current_el = get_current_el(); \ + switch(current_el) { \ + case EL1: \ + func##_el1(); \ + break; \ + case EL2: \ + func##_el2(); \ + break; \ + case EL3: \ + func##_el3(); \ + break; \ + } \ + } while(0) + +/* PSTATE and special purpose register access functions */ +uint32_t raw_read_current_el(void); +uint32_t get_current_el(void); +uint32_t raw_read_daif(void); +void raw_write_daif(uint32_t daif); +void enable_debug_exceptions(void); +void enable_serror_exceptions(void); +void enable_irq(void); +void enable_fiq(void); +void disable_debug_exceptions(void); +void disable_serror_exceptions(void); +void disable_irq(void); +void disable_fiq(void); +uint64_t raw_read_dlr_el0(void); +void raw_write_dlr_el0(uint64_t dlr_el0); +uint64_t raw_read_dspsr_el0(void); +void raw_write_dspsr_el0(uint64_t dspsr_el0); +uint64_t raw_read_elr_el1(void); +void raw_write_elr_el1(uint64_t elr_el1); +uint64_t raw_read_elr_el2(void); +void raw_write_elr_el2(uint64_t elr_el2); +uint64_t raw_read_elr_el3(void); +void raw_write_elr_el3(uint64_t elr_el3); +uint64_t raw_read_elr_current(void); +void raw_write_elr_current(uint64_t elr); +uint32_t raw_read_fpcr(void); +void raw_write_fpcr(uint32_t fpcr); +uint32_t raw_read_fpsr(void); +void raw_write_fpsr(uint32_t fpsr); +uint32_t raw_read_nzcv(void); +void raw_write_nzcv(uint32_t nzcv); +uint64_t raw_read_sp_el0(void); +void raw_write_sp_el0(uint64_t sp_el0); +uint64_t raw_read_sp_el1(void); +void raw_write_sp_el1(uint64_t sp_el1); +uint64_t raw_read_sp_el2(void); +void raw_write_sp_el2(uint64_t sp_el2); +uint32_t raw_read_spsel(void); +void raw_write_spsel(uint32_t spsel); +uint64_t raw_read_sp_el3(void); +void raw_write_sp_el3(uint64_t sp_el3); +uint32_t raw_read_spsr_abt(void); +void raw_write_spsr_abt(uint32_t spsr_abt); +uint32_t raw_read_spsr_el1(void); +void raw_write_spsr_el1(uint32_t spsr_el1); +uint32_t raw_read_spsr_el2(void); +void raw_write_spsr_el2(uint32_t spsr_el2); +uint32_t raw_read_spsr_el3(void); +void raw_write_spsr_el3(uint32_t spsr_el3); +uint32_t raw_read_spsr_current(void); +void raw_write_spsr_current(uint32_t spsr); +uint32_t raw_read_spsr_fiq(void); +void raw_write_spsr_fiq(uint32_t spsr_fiq); +uint32_t raw_read_spsr_irq(void); +void raw_write_spsr_irq(uint32_t spsr_irq); +uint32_t raw_read_spsr_und(void); +void raw_write_spsr_und(uint32_t spsr_und); + +/* System control register access */ +uint32_t raw_read_actlr_el1(void); +void raw_write_actlr_el1(uint32_t actlr_el1); +uint32_t raw_read_actlr_el2(void); +void raw_write_actlr_el2(uint32_t actlr_el2); +uint32_t raw_read_actlr_el3(void); +void raw_write_actlr_el3(uint32_t actlr_el3); +uint32_t raw_read_actlr_current(void); +void raw_write_actlr_current(uint32_t actlr); +uint32_t raw_read_afsr0_el1(void); +void raw_write_afsr0_el1(uint32_t afsr0_el1); +uint32_t raw_read_afsr0_el2(void); +void raw_write_afsr0_el2(uint32_t afsr0_el2); +uint32_t raw_read_afsr0_el3(void); +void raw_write_afsr0_el3(uint32_t afsr0_el3); +uint32_t raw_read_afsr0_current(void); +void raw_write_afsr0_current(uint32_t afsr0); +uint32_t raw_read_afsr1_el1(void); +void raw_write_afsr1_el1(uint32_t afsr1_el1); +uint32_t raw_read_afsr1_el2(void); +void raw_write_afsr1_el2(uint32_t afsr1_el2); +uint32_t raw_read_afsr1_el3(void); +void raw_write_afsr1_el3(uint32_t afsr1_el3); +uint32_t raw_read_afsr1_current(void); +void raw_write_afsr1_current(uint32_t afsr1); +uint32_t raw_read_aidr_el1(void); +uint64_t raw_read_amair_el1(void); +void raw_write_amair_el1(uint64_t amair_el1); +uint64_t raw_read_amair_el2(void); +void raw_write_amair_el2(uint64_t amair_el2); +uint64_t raw_read_amair_el3(void); +void raw_write_amair_el3(uint64_t amair_el3); +uint64_t raw_read_amair_current(void); +void raw_write_amair_current(uint64_t amair); +uint32_t raw_read_ccsidr_el1(void); +uint32_t raw_read_clidr_el1(void); +uint32_t raw_read_cpacr_el1(void); +void raw_write_cpacr_el1(uint32_t cpacr_el1); +uint32_t raw_read_cptr_el2(void); +void raw_write_cptr_el2(uint32_t cptr_el2); +uint32_t raw_read_cptr_el3(void); +void raw_write_cptr_el3(uint32_t cptr_el3); +uint32_t raw_read_cptr_current(void); +void raw_write_cptr_current(uint32_t cptr); +uint32_t raw_read_csselr_el1(void); +void raw_write_csselr_el1(uint32_t csselr_el1); +uint32_t raw_read_ctr_el0(void); +uint32_t raw_read_esr_el1(void); +void raw_write_esr_el1(uint32_t esr_el1); +uint32_t raw_read_esr_el2(void); +void raw_write_esr_el2(uint32_t esr_el2); +uint32_t raw_read_esr_el3(void); +void raw_write_esr_el3(uint32_t esr_el3); +uint32_t raw_read_esr_current(void); +void raw_write_esr_current(uint32_t esr); +uint64_t raw_read_far_el1(void); +void raw_write_far_el1(uint64_t far_el1); +uint64_t raw_read_far_el2(void); +void raw_write_far_el2(uint64_t far_el2); +uint64_t raw_read_far_el3(void); +void raw_write_far_el3(uint64_t far_el3); +uint64_t raw_read_far_current(void); +void raw_write_far_current(uint64_t far); +uint64_t raw_read_hcr_el2(void); +void raw_write_hcr_el2(uint64_t hcr_el2); +uint64_t raw_read_aa64pfr0_el1(void); +uint64_t raw_read_mair_el1(void); +void raw_write_mair_el1(uint64_t mair_el1); +uint64_t raw_read_mair_el2(void); +void raw_write_mair_el2(uint64_t mair_el2); +uint64_t raw_read_mair_el3(void); +void raw_write_mair_el3(uint64_t mair_el3); +uint64_t raw_read_mair_current(void); +void raw_write_mair_current(uint64_t mair); +uint64_t raw_read_mpidr_el1(void); +uint32_t raw_read_rmr_el1(void); +void raw_write_rmr_el1(uint32_t rmr_el1); +uint32_t raw_read_rmr_el2(void); +void raw_write_rmr_el2(uint32_t rmr_el2); +uint32_t raw_read_rmr_el3(void); +void raw_write_rmr_el3(uint32_t rmr_el3); +uint32_t raw_read_rmr_current(void); +void raw_write_rmr_current(uint32_t rmr); +uint64_t raw_read_rvbar_el1(void); +void raw_write_rvbar_el1(uint64_t rvbar_el1); +uint64_t raw_read_rvbar_el2(void); +void raw_write_rvbar_el2(uint64_t rvbar_el2); +uint64_t raw_read_rvbar_el3(void); +void raw_write_rvbar_el3(uint64_t rvbar_el3); +uint64_t raw_read_rvbar_current(void); +void raw_write_rvbar_current(uint64_t rvbar); +uint32_t raw_read_scr_el3(void); +void raw_write_scr_el3(uint32_t scr_el3); +uint32_t raw_read_sctlr_el1(void); +void raw_write_sctlr_el1(uint32_t sctlr_el1); +uint32_t raw_read_sctlr_el2(void); +void raw_write_sctlr_el2(uint32_t sctlr_el2); +uint32_t raw_read_sctlr_el3(void); +void raw_write_sctlr_el3(uint32_t sctlr_el3); +uint32_t raw_read_sctlr_current(void); +void raw_write_sctlr_current(uint32_t sctlr); +uint64_t raw_read_tcr_el1(void); +void raw_write_tcr_el1(uint64_t tcr_el1); +uint32_t raw_read_tcr_el2(void); +void raw_write_tcr_el2(uint32_t tcr_el2); +uint32_t raw_read_tcr_el3(void); +void raw_write_tcr_el3(uint32_t tcr_el3); +uint64_t raw_read_ttbr0_el1(void); +void raw_write_ttbr0_el1(uint64_t ttbr0_el1); +uint64_t raw_read_ttbr0_el2(void); +void raw_write_ttbr0_el2(uint64_t ttbr0_el2); +uint64_t raw_read_ttbr0_el3(void); +void raw_write_ttbr0_el3(uint64_t ttbr0_el3); +uint64_t raw_read_ttbr0_current(void); +void raw_write_ttbr0_current(uint64_t ttbr0); +uint64_t raw_read_ttbr1_el1(void); +void raw_write_ttbr1_el1(uint64_t ttbr1_el1); +uint64_t raw_read_vbar_el1(void); +void raw_write_vbar_el1(uint64_t vbar_el1); +uint64_t raw_read_vbar_el2(void); +void raw_write_vbar_el2(uint64_t vbar_el2); +uint64_t raw_read_vbar_el3(void); +void raw_write_vbar_el3(uint64_t vbar_el3); +uint64_t raw_read_vbar_current(void); +void raw_write_vbar_current(uint64_t vbar); + +/* Cache maintenance system instructions */ +void dccisw(uint64_t cisw); +void dccivac(uint64_t civac); +void dccsw(uint64_t csw); +void dccvac(uint64_t cvac); +void dccvau(uint64_t cvau); +void dcisw(uint64_t isw); +void dcivac(uint64_t ivac); +void dczva(uint64_t zva); +void iciallu(void); +void icialluis(void); +void icivau(uint64_t ivau); + +/* TLB maintenance instructions */ +void tlbiall_el1(void); +void tlbiall_el2(void); +void tlbiall_el3(void); +void tlbiall_current(void); +void tlbiallis_el1(void); +void tlbiallis_el2(void); +void tlbiallis_el3(void); +void tlbiallis_current(void); +void tlbivaa_el1(uint64_t va); + +/* Memory barrier */ +void dmb(void); +void dsb(void); +void isb(void);

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coreboot-gerrit February 2015