the following patch was just integrated into master:
commit c684d05b0fa66f86b3c94ecd46388858d8e5dcaa
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Sat Feb 21 01:46:20 2015 -0600
mainboard/asus/kfsn4-dre: Enable W83793 fan controller
The Winbond W83793 fan controller is not automatically
configured correctly on power application, leading to
abnormal, and in some cases random, fan behaviour.
This commit enables the controller and sets sane default
values.
TEST: Booted mainboard and verified that the correct number
of fan speed sensors were visible from hwmon under Linux.
Also verified that, unlike before, the CPU fans were running
at a high enough speed to properly cool the CPUs. Verified
the 8 fan outputs under direct control of the W83793 device.
Verified voltage and temperature sensors and limits via output
of the 'sensors' command.
Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8503
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/8503 for details.
-gerrit
the following patch was just integrated into master:
commit d3e31be8c5509862b0e28ac49286c957a79faf33
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Sat Feb 21 01:45:35 2015 -0600
drivers/i2c/w83793: Use devicetree.cb to set additional values
This allows devicetree.cb to set:
Minimum PWM values
Temperature sensor source
Voltage sensor high/low limits
Fan pin routing
Default PWM values
Manual PWM values per-fan
Change-Id: I3a321406a26ae01a121289d24b41c9f988dd6f30
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8502
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/8502 for details.
-gerrit
Kevin Paul Herbert (kph(a)meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8530
-gerrit
commit 59927423db085ce2b442521a48fcdadf173e7624
Author: Kevin Paul Herbert <kph(a)meraki.net>
Date: Wed Feb 25 00:36:51 2015 -0800
x86: Fix pointer arithmetic regressions from MMIO changes
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).
Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph(a)meraki.net>
---
src/soc/intel/fsp_baytrail/southcluster.c | 4 ++--
src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 2 +-
src/southbridge/amd/amd8111/nic.c | 2 +-
src/southbridge/intel/fsp_rangeley/lpc.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 878535f..ec2f94f 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -91,8 +91,8 @@ static void sc_enable_ioapic(struct device *dev)
* Set SCI IRQ to IRQ9
*/
write32(ilb_base + ILB_OIC, 0x100); /* AEN */
- reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */
- write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */
+ reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
+ write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 5463d2b..9deeb45 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32);
+ write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index 21df6c0..05ca871 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -11,7 +11,7 @@
#include "amd8111.h"
-#define CMD3 (0x54/(sizeof(u32)))
+#define CMD3 0x54
typedef enum {
VAL3 = (1 << 31), /* VAL bit for byte 3 */
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 8f29670..80673a6 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev)
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
- u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f);
+ u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
the following patch was just integrated into master:
commit 1ecc8af5ce440003f32a66d3e0047150a7d4beab
Author: Lubomir Rintel <lkundrak(a)v3.sk>
Date: Tue Feb 24 20:33:35 2015 +0100
nvramcui: don't init curses too early
Init curses as late as possible and tear them down early. There are possible
error outs after that and they don't look nice with curses initialized.
Change-Id: I9128ae8eee25940716b8d223cc7ec6c0abb6838e
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
Reviewed-on: http://review.coreboot.org/8528
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/8528 for details.
-gerrit
the following patch was just integrated into master:
commit 18860d7a4f06c5b48dcd7ef90e3039cf44b4e57f
Author: Lubomir Rintel <lkundrak(a)v3.sk>
Date: Sun Feb 1 16:56:58 2015 +0100
nvramcui: fix a buffer overflow
Missing parentheses around addition.
==22611== Invalid write of size 8
==22611== at 0x401B26: main (nvramcui.c:146)
==22611== Address 0x5a67c40 is 32 bytes inside a block of size 33 alloc'd
==22611== at 0x4C2BC0F: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so)
==22611== by 0x401AA9: main (nvramcui.c:137)
Change-Id: I9fd6a619dd03ebaaa066bca8fa5838e76374c984
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
Reviewed-on: http://review.coreboot.org/8527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/8527 for details.
-gerrit
the following patch was just integrated into master:
commit 68009e98ab7172325da4c5482166a2515a3763ac
Author: Lubomir Rintel <lkundrak(a)v3.sk>
Date: Sun Feb 1 15:24:43 2015 +0100
nvramcui: don't wait for the first key update to render the form
Flush out the initial screen window and render the form before the first
keypress. It looks overly weird otherwise and is very likely unintended.
Change-Id: I8700e36e608f2ba115359070f75b7dc9f230291e
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
Reviewed-on: http://review.coreboot.org/8526
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/8526 for details.
-gerrit
the following patch was just integrated into master:
commit a63da6f97e54f102f068c19befbd6072c13a00f7
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jun 24 14:22:36 2014 -0500
rush: Correct version field to match t132
The version field for t132 cpus is 0x00130001. Update it to
the correct version.
BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and was able to see serial with subsequent changes.
Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205435
Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
(cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46)
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a
Reviewed-on: http://review.coreboot.org/8467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/8467 for details.
-gerrit
the following patch was just integrated into master:
commit 595a40cfc92baecca9c58a7a95ae38ce72582f39
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Sun Feb 22 23:07:48 2015 -0700
tegra124: Clean up ARM UART driver build
CONFIG_CONSOLE_SERIAL_UART has been updated to
CONFIG_DRIVER_UART. The UART may be used for more than serial console.
Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/8516
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/8516 for details.
-gerrit
the following patch was just integrated into master:
commit d8ea0ba5a8e338a07e1b8736d37b952ce531018d
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Tue Feb 24 16:24:25 2015 -0700
arm64: Remove early_console.c
The early_console.c file isn't used or built. It has been replaced
by the generic uart and console drivers.
Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/8529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/8529 for details.
-gerrit