coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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509 discussions

Patch merged into coreboot/master: a9330e0 crossgcc: Add mips target
by gerrit＠coreboot.org 28 Feb '15

28 Feb '15

the following patch was just integrated into master: commit a9330e051a1c8057b7a625470b8244655c62e066 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Feb 27 23:41:15 2015 +0100 crossgcc: Add mips target Change-Id: I7fae2e9c417a7880bfa28739afa6020820fcd360 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8546 for details. -gerrit

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Patch merged into coreboot/master: 6321f52 crossgcc: Clean GNU make context so builds succeed
by gerrit＠coreboot.org 28 Feb '15

28 Feb '15

the following patch was just integrated into master: commit 6321f523e73c06953c8c6b0a24e06ef312490452 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Feb 27 23:36:26 2015 +0100 crossgcc: Clean GNU make context so builds succeed GCC's build system is sometimes confused by our build system's configuration: make crossgcc failed, while util/crossgcc/buildgcc -p armv7-a-eabi didn't. Make sure the GCC build system runs independently from ours by breaking any ties. Change-Id: I563e17b22127bc8c83ebfb17252184a3b6e0e58b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8545 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8545 for details. -gerrit

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Patch merged into coreboot/master: 81dd46f build system: make crosstools should build all supported compilers
by gerrit＠coreboot.org 28 Feb '15

28 Feb '15

the following patch was just integrated into master: commit 81dd46ff2a8563dfbeb286df177f2ab558eefa3c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 28 12:53:53 2015 +0100 build system: make crosstools should build all supported compilers It only built i386-elf Change-Id: I02f94d12297901136e1c17c63bbeb103c1d93e8d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8548 for details. -gerrit

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Patch set updated for coreboot: 107f144 cpu/x86/car: Remove printk in car_get_var_ptr()
by Timothy Pearson 28 Feb '15

28 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8493 -gerrit commit 107f1449946fba89f9b831c273ab01f4beafdde9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 19 17:51:02 2015 -0600 cpu/x86/car: Remove printk in car_get_var_ptr() Use of printk in car_get_var_ptr() will cause infinite recursion. This caused an immediate crash on AMD K10 platforms after setting car_get_var_ptr, causing a failure to boot. TEST: With other patches under review booted KFSN4-DRE successfully and gained access to romstage console logs and timestamps. Change-Id: I883df807932b7b78d176882f6f4b121a8b7e2e52 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/x86/car.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 9f1a26e..1458560 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2013 Google, Inc. * * This program is free software; you can redistribute it and/or modify @@ -22,6 +23,7 @@ #include <console/console.h> #include <cbmem.h> #include <arch/early_variables.h> +#include <include/smp/node.h> #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) #include <drivers/intel/fsp/fsp_util.h> @@ -50,6 +52,9 @@ static int car_migrated CAR_GLOBAL; */ void *car_get_var_ptr(void *var) { + if (!boot_cpu()) + return var; + char *migrated_base = NULL; int offset; void * _car_start = &_car_data_start; @@ -60,12 +65,8 @@ void *car_get_var_ptr(void *var) if (!car_migrated) return var; - if (var < _car_start || var >= _car_end) { - printk(BIOS_ERR, - "Requesting CAR variable outside of CAR region: %p\n", - var); + if (var < _car_start || var >= _car_end) return var; - } #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) migrated_base=(char *)find_saved_temp_mem(

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Patch set updated for coreboot: 9f7437f mainboards/amd/fam10: Initialize cbmem area after raminit
by Timothy Pearson 28 Feb '15

28 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit 9f7437fb2375da41c31ade0efea1367eacdd2eb5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Feb 18 18:24:45 2015 -0600 mainboards/amd/fam10: Initialize cbmem area after raminit TEST: With other patches under review booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + 21 files changed, 21 insertions(+) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.

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Patch set updated for coreboot: 13d7426 cpu/amd/model_10xxx: Add support for early cbmem
by Timothy Pearson 28 Feb '15

28 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8488 -gerrit commit 13d74267d7335b9dae160266e7567f916d6dba75 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Feb 18 18:26:31 2015 -0600 cpu/amd/model_10xxx: Add support for early cbmem Change-Id: I80622b1998ad77c8e2f5ae94bf28bdb704a41eb9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 2 + src/cpu/amd/model_10xxx/ram_calc.c | 59 ++++++++++++++++++++++++++++++ src/cpu/amd/model_10xxx/ram_calc.h | 25 +++++++++++++ src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 20 +--------- src/southbridge/amd/sb700/early_setup.c | 5 +++ src/southbridge/amd/sb700/lpc.c | 5 +++ src/southbridge/amd/sb800/early_setup.c | 5 +++ 8 files changed, 103 insertions(+), 19 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index ba12dcd..c17e66c 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +romstage-y += ram_calc.c +ramstage-y += ram_calc.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c new file mode 100644 index 0000000..1b1d2c6 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include <cbmem.h> + +#include "ram_calc.h" + +uint64_t get_uma_memory_size(uint64_t topmem) +{ + uint64_t uma_size = 0; + if (IS_ENABLED(CONFIG_GFXUMA)) { + /* refer to UMA Size Consideration in 780 BDG. */ + switch (topmem) { + case 0x10000000: /* 256M system memory */ + uma_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_size = 0x8000000; /* 128M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_size = 0x10000000; /* 256M recommended UMA */ + break; + } + } + + return uma_size; +} + +void *cbmem_top(void) +{ + uint32_t topmem = (uint32_t) rdmsr(TOP_MEM).lo; + + topmem = topmem - get_uma_memory_size(topmem); + + return (void *) topmem; +} diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h new file mode 100644 index 0000000..7ece338 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_MODEL_10XXX_MEM_CALC_H_ +#define _AMD_MODEL_10XXX_MEM_CALC_H_ + +uint64_t get_uma_memory_size(uint64_t topmem); + +#endif diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 8e1c4f8..96d2904 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f28c726..60296dd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -32,6 +32,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/model_10xxx/ram_calc.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -828,21 +829,7 @@ static void setup_uma_memory(void) { #if CONFIG_GFXUMA uint32_t topmem = (uint32_t) bsp_topmem(); - /* refer to UMA Size Consideration in 780 BDG. */ - switch (topmem) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } - + uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); @@ -1052,10 +1039,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 94f33b7..0c37840 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -728,6 +728,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 658e954..a5f11a6 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -88,6 +88,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; @@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop) nvram_pos++; } } +#endif static void sb700_lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 69bc3bd..300b54e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,6 +673,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif

1 0

Patch set updated for coreboot: 9bcc6ef AMD K8 fam10: Drop redundant parameters on scan_chain()
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8563 -gerrit commit 9bcc6ef05578f65e60c59e83faa2c66bfc27962f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 28 12:03:20 2015 +0200 AMD K8 fam10: Drop redundant parameters on scan_chain() Change-Id: I6041b666e6792cf97b8273ed54832d86af8ed23e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 16 +++++----------- src/northbridge/amd/amdk8/northbridge.c | 16 ++++++---------- 2 files changed, 11 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c63b293..0f60d21 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -152,16 +152,15 @@ static void ht_route_link(struct bus *link) pci_write_config32(link->dev, link->cap + 0x14, busses); } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, - u32 max) +static u32 amdfam10_scan_chain(struct bus *link, u32 max) { -// I want to put sb chain in bus 0 can I? - - int i; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; + u32 nodeid = amdfam10_nodeid(dev); + bool is_sblink = (nodeid == 0) && (link->link_num == sysconf.sblk); + /* See if there is an available configuration space mapping * register in function 1. */ @@ -264,18 +263,13 @@ static void trim_ht_chain(struct device *dev) static unsigned amdfam10_scan_chains(device_t dev, unsigned max) { - unsigned nodeid; struct bus *link; - unsigned sblink = sysconf.sblk; - - nodeid = amdfam10_nodeid(dev); trim_ht_chain(dev); for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); if (link->ht_link_up) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + max = amdfam10_scan_chain(link, max); } return max; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 3c81342..a6f7797 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -100,8 +100,7 @@ static u32 amdk8_nodeid(device_t dev) return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, - u32 max) +static u32 amdk8_scan_chain(struct bus *link, u32 max) { int i; u32 config_busses; @@ -109,6 +108,10 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; + u32 nodeid = amdk8_nodeid(link->dev); + unsigned int sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + /* See if there is an available configuration space mapping * register in function 1. */ @@ -240,20 +243,13 @@ static void trim_ht_chain(struct device *dev) static unsigned amdk8_scan_chains(device_t dev, unsigned max) { - unsigned nodeid; struct bus *link; - unsigned sblink = 0; - - nodeid = amdk8_nodeid(dev); - if (nodeid == 0) - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; trim_ht_chain(dev); for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); if (link->ht_link_up) - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); + max = amdk8_scan_chain(link, max); } return max; }

1 0

Patch set updated for coreboot: d5e548d AMD K8 fam10: Drop local is_sblink in scan_chain()
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8564 -gerrit commit d5e548dc343515f372a8c9ebf188a2408ca2882d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 08:54:45 2015 +0200 AMD K8 fam10: Drop local is_sblink in scan_chain() We can define is_sblink = (max == 0) as sblink is always the very first chain we scan. Change-Id: Ibd6b3ea23954ca919ae148604bca2495e9f8753b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 9 +++------ src/northbridge/amd/amdk8/northbridge.c | 9 +++------ 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 0f60d21..7ff33cb 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -158,9 +158,6 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; - u32 nodeid = amdfam10_nodeid(dev); - bool is_sblink = (nodeid == 0) && (link->link_num == sysconf.sblk); - /* See if there is an available configuration space mapping * register in function 1. */ @@ -172,11 +169,11 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) * so we set the subordinate bus number to 0xff for the moment. */ - if (!is_sblink) + if (max != 0) max++; /* One node can have 8 link and segn is the same. */ - if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE) max = ALIGN_UP(max, 8); link->secondary = max; @@ -200,7 +197,7 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(link->secondary == 0)); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a6f7797..cb37749 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -107,10 +107,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; - u32 nodeid = amdk8_nodeid(link->dev); - unsigned int sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); /* See if there is an available configuration space mapping * register in function 1. @@ -144,11 +141,11 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) * so we set the subordinate bus number to 0xff for the moment. */ - if (!is_sblink) + if (max != 0) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE) max = ALIGN_UP(max, 0x40); link->secondary = max; @@ -178,7 +175,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(link->secondary == 0)); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value

1 0

Patch set updated for coreboot: 3b2bdf3 AMD K8 fam10: Drop extra HT scan_chain() parameters
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8565 -gerrit commit 3b2bdf39797aa7c82076ef549a80d0d35d47d733 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 08:27:13 2015 +0200 AMD K8 fam10: Drop extra HT scan_chain() parameters Change-Id: Ice7cb89c19585cf725b6f73c33443050f8d65418 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 28 ++++++++++++++++++++++++++-- src/include/device/hypertransport.h | 3 +-- src/northbridge/amd/amdfam10/northbridge.c | 21 +-------------------- src/northbridge/amd/amdk8/northbridge.c | 23 +++-------------------- 4 files changed, 31 insertions(+), 44 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 40cc2d5..ec0601b 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -248,7 +248,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, } } -unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, +static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid) @@ -479,6 +479,30 @@ end_of_chain: return max; } +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max) +{ + int i; + unsigned int max_devfn; + u32 ht_unitid_base[4]; + + for (i = 0; i < 4; i++) + ht_unitid_base[i] = 0x20; + + if (bus->secondary == 0) + max_devfn = (CONFIG_CDB << 3) - 1; + else + max_devfn = (0x20 << 3) - 1; + + max = do_hypertransport_scan_chain(bus, 0, max_devfn, max, + ht_unitid_base, offset_unit_id(bus->secondary == 0)); + + bus->hcdn_reg = 0; + for (i = 0; i < 4; i++) + bus->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + return max; +} + /** * Scan a PCI bridge and the buses behind the bridge. * @@ -498,7 +522,7 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, { unsigned int ht_unitid_base[4]; unsigned int offset_unitid = 1; - return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, + return do_hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid); } diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index 0080e8d..6034b27 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -10,8 +10,7 @@ #define ConnectionPending (1 << 4) bool ht_is_non_coherent_link(struct bus *link); -unsigned int hypertransport_scan_chain(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max); unsigned int ht_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_ht_ops_bus; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 7ff33cb..cf47a78 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -154,10 +154,6 @@ static void ht_route_link(struct bus *link) static u32 amdfam10_scan_chain(struct bus *link, u32 max) { - int i; - u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_devfn; - /* See if there is an available configuration space mapping * register in function 1. */ @@ -187,17 +183,7 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link */ - for(i=0;i<4;i++) { - ht_unitid_base[i] = 0x20; - } - - //if ext conf is enabled, only need use 0x1f - if (link->secondary == 0) - max_devfn = (0x17<<3) | 7; - else - max_devfn = (0x1f<<3) | 7; - - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(link->secondary == 0)); + max = hypertransport_scan_chain(link, max); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -211,11 +197,6 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) set_config_map_reg(link); - /* Use ht_unitid_base to update hcdn_reg. */ - link->hcdn_reg = 0; - for (i = 0; i < 4;i++) - link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); - store_ht_c_conf_bus(link); return max; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index cb37749..d19fb34 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -102,11 +102,9 @@ static u32 amdk8_nodeid(device_t dev) static u32 amdk8_scan_chain(struct bus *link, u32 max) { - int i; + int index; u32 config_busses; u32 free_reg, config_reg; - u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_devfn; u32 nodeid = amdk8_nodeid(link->dev); /* See if there is an available configuration space mapping @@ -166,16 +164,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link */ - for(i=0;i<4;i++) { - ht_unitid_base[i] = 0x20; - } - - if (link->secondary == 0) - max_devfn = (0x17<<3) | 7; - else - max_devfn = (0x1f<<3) | 7; - - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(link->secondary == 0)); + max = hypertransport_scan_chain(link, max); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -188,13 +177,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) (link->subordinate << 24); f1_write_config32(config_reg, config_busses); - - // use config_reg and ht_unitid_base to update hcdn_reg - link->hcdn_reg = 0; - for (i = 0; i < 4; i++) - link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); - - int index = (config_reg-0xe0) >> 2; + index = (config_reg-0xe0) >> 2; sysconf.hcdn_reg[index] = link->hcdn_reg; return max;

1 0

Patch set updated for coreboot: 3fdb198 AMD K8 fam10: HT link subordinate FIXME
by Kyösti Mälkki 28 Feb '15

28 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8566 -gerrit commit 3fdb19877acee42be390af6da38cb5f9b272c2bc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 11:37:41 2015 +0200 AMD K8 fam10: HT link subordinate FIXME Change-Id: I930f2beacdc95d0a7edd07db66a1c2e58bb2f3cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 43 +++++++++++++--------- src/northbridge/amd/amdk8/northbridge.c | 57 ++++++++++++++++++++---------- 2 files changed, 65 insertions(+), 35 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index cf47a78..68c79c0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -138,10 +138,23 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static void ht_route_link(struct bus *link) +#define HT_ROUTE_SCAN 0 +#define HT_ROUTE_FINAL 1 + +static void ht_route_link(struct bus *link, int mode) { +#if 0 u32 busses; + if (mode == HT_ROUTE_SCAN) { + if (link->dev->bus->subordinate == 0) + link->secondary = 0; + else + link->secondary = link->dev->bus->subordinate + 1; + + link->subordinate = link->secondary; + } + /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagated by the bridge if it is * not correctly configured @@ -150,6 +163,14 @@ static void ht_route_link(struct bus *link) busses &= 0xffff00ff; busses |= ((u32)(link->secondary) << 8); pci_write_config32(link->dev, link->cap + 0x14, busses); + + if (mode == HT_ROUTE_FINAL) { + if (CONFIG_HT_CHAIN_DISTRIBUTE) + link->dev->bus->subordinate = ALIGN_UP(link->subordinate, 8) - 1; + else + link->dev->bus->subordinate = link->subordinate; + } +#endif } static u32 amdfam10_scan_chain(struct bus *link, u32 max) @@ -165,17 +186,7 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) * so we set the subordinate bus number to 0xff for the moment. */ - if (max != 0) - max++; - - /* One node can have 8 link and segn is the same. */ - if (CONFIG_HT_CHAIN_DISTRIBUTE) - max = ALIGN_UP(max, 8); - - link->secondary = max; - link->subordinate = 0xfc; - - ht_route_link(link); + ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ set_config_map_reg(link); @@ -183,22 +194,22 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link */ - max = hypertransport_scan_chain(link, max); + + link->subordinate = hypertransport_scan_chain(link, link->secondary); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - link->subordinate = max; - if (0) { /* Clear the extend reg. */ clear_config_map_reg(link); } + ht_route_link(link, HT_ROUTE_FINAL); set_config_map_reg(link); store_ht_c_conf_bus(link); - return max; + return link->subordinate; } /* Do sb ht chain at first, in case s2885 put sb chain diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d19fb34..c1c52c5 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -79,20 +79,50 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static void ht_route_link(struct bus *link) +#define HT_ROUTE_SCAN 0 +#define HT_ROUTE_FINAL 1 + +static void ht_route_link(struct bus *link, int mode) { +#if 0 u32 busses; + if (mode == HT_ROUTE_SCAN) { + if (link->dev->bus->subordinate == 0) + link->secondary = 0; + else + link->secondary = link->dev->bus->subordinate + 1; + + link->subordinate = link->secondary; + } + /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagated by the bridge if it is * not correctly configured */ busses = pci_read_config32(link->dev, link->cap + 0x14); busses &= 0xff000000; - busses |= (((unsigned int)(link->dev->bus->secondary) << 0) | - ((unsigned int)(link->secondary) << 8) | - ((unsigned int)(link->subordinate) << 16)); + busses |= link->dev->bus->secondary & 0xff; + if (mode == HT_ROUTE_CLOSE) { + busses |= 0xfeff << 8; + } else if (mode == HT_ROUTE_SCAN) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= 0xff << 16; /* MAX PCI_BUS number here */ + } else if (mode == HT_ROUTE_FINAL) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->subordinate & 0xff) << 16; + } + pci_write_config32(link->dev, link->cap + 0x14, busses); + + if (mode == HT_ROUTE_FINAL) { + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + if (CONFIG_HT_CHAIN_DISTRIBUTE) + link->dev->bus->subordinate = ALIGN_UP(link->subordinate, 0x40) - 1; + else + link->dev->bus->subordinate = link->subordinate; + } +#endif } static u32 amdk8_nodeid(device_t dev) @@ -139,17 +169,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) * so we set the subordinate bus number to 0xff for the moment. */ - if (max != 0) - max++; - - /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - if (CONFIG_HT_CHAIN_DISTRIBUTE) - max = ALIGN_UP(max, 0x40); - - link->secondary = max; - link->subordinate = 0xff; - - ht_route_link(link); + ht_route_link(link, HT_ROUTE_SCAN); config_busses = f1_read_config32(config_reg); config_busses &= 0x000fc88; @@ -164,14 +184,13 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link */ - max = hypertransport_scan_chain(link, max); + link->subordinate = hypertransport_scan_chain(link, link->secondary); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - link->subordinate = max; - ht_route_link(link); + ht_route_link(link, HT_ROUTE_FINAL); config_busses = (config_busses & 0x00ffffff) | (link->subordinate << 24); @@ -180,7 +199,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) index = (config_reg-0xe0) >> 2; sysconf.hcdn_reg[index] = link->hcdn_reg; - return max; + return link->subordinate; } /* Do sb ht chain at first, in case s2885 put sb chain

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coreboot-gerrit February 2015