coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: fe710ae rmodule: Correct the typecast with proper parenthesis
by Marc Jones 19 Jan '15

19 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8237 -gerrit commit fe710ae77f245bfd536c8ef2d1df2cc3884a70b7 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 04:44:09 2014 -0700 rmodule: Correct the typecast with proper parenthesis BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I67801f96ec63a3150263ce3d6a4a7556092c6be5 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209505 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 71cd62740e150cb5b5adc1b20c7f13fa8c51b7e3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0c3f5f10a3af7028728dadca539681a081d858e0 --- src/lib/rmodule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 828a63d..d7c2326 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -162,7 +162,7 @@ static int rmodule_relocate(const struct rmodule *module) adjust_loc = rmodule_load_addr(module, *reloc); printk(PK_ADJ_LEVEL, "Adjusting %p: 0x%08lx -> 0x%08lx\n", adjust_loc, (unsigned long) *adjust_loc, - (unsigned long) *adjust_loc + adjustment); + (unsigned long) (*adjust_loc + adjustment)); *adjust_loc += adjustment; reloc++;

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Patch merged into coreboot/master: 7e72abe samus: Update indices of ramstage and refcode blobs
by gerrit＠coreboot.org 19 Jan '15

19 Jan '15

the following patch was just integrated into master: commit 7e72abef1b74e30fe9dcfe7dd1c90778388f15f3 Author: Randall Spangler <rspangler(a)chromium.org> Date: Fri Jul 18 12:45:08 2014 -0700 samus: Update indices of ramstage and refcode blobs This must be committed at the same time as the corresponding depthcharge change which updates the fmap. BUG=chrome-os-partner:30079 BRANCH=none TEST=Build samus firmware. dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and PD_MAIN_B sections. Boot samus. 'crossystem mainfw_act' -> A As root, 'crossystem fwb_tries=1' Reboot samus. 'crossystem mainfw_act' -> B CQ-DEPEND=CL:208984,CL:*169850,CL:208989 Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e Original-Signed-off-by: Randall Spangler <rspangler(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208899 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837 Reviewed-on: http://review.coreboot.org/8219 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8219 for details. -gerrit

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Patch merged into coreboot/master: 808a254 samus: Delay bringing SSD out of reset
by gerrit＠coreboot.org 19 Jan '15

19 Jan '15

the following patch was just integrated into master: commit 808a254c3f38e85d97758d8551bd423ab5e9ef05 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 15 13:41:18 2014 -0700 samus: Delay bringing SSD out of reset In order to ensure that we meet timing requirements for the SSD power sequencing delay bringing the SSD out of reset until after memory training. BUG=chrome-os-partner:29914 BRANCH=None TEST=build and boot on samus Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208155 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317 Reviewed-on: http://review.coreboot.org/8215 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8215 for details. -gerrit

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Patch merged into coreboot/master: 6a342cb samus: Disable self refresh and MRC cache on broadwell
by gerrit＠coreboot.org 19 Jan '15

19 Jan '15

the following patch was just integrated into master: commit 6a342cb699d3573e366053076df5808c738de7e6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 15 13:40:21 2014 -0700 samus: Disable self refresh and MRC cache on broadwell Add workarounds for power and/or lpddr3 issues on Broadwell SKU. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build and boot on samus Original-Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208154 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit c3ee57114315320b542f53645ffb168ad654b756) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie28f3ad65000a627ba64486e0f16493e8101cef3 Reviewed-on: http://review.coreboot.org/8214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8214 for details. -gerrit

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New patch to review for coreboot: e78b547 arm64: Prepare ARM64 for building
by Marc Jones 19 Jan '15

19 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8236 -gerrit commit e78b547c3cd241d8ca946d1882c5c1a2af0dada5 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jan 16 13:45:23 2015 -0700 arm64: Prepare ARM64 for building There were a number of issues with the ARM64 build files. This patch ports the following changes from ARMV4/V7 to ARMV8: - make armv8 Kconfig options consistent with armv4/v7 - fix build include issues in boot.c, tables.c, and early_variables.h by matching armv4/v7. Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iacd95d336559c45458784d1da67bde62a0956620 --- src/arch/arm64/Makefile.inc | 35 ++++++++++++++------------- src/arch/arm64/armv8/Kconfig | 8 +++--- src/arch/arm64/armv8/Makefile.inc | 9 ++++--- src/arch/arm64/boot.c | 7 +++--- src/arch/arm64/include/arch/early_variables.h | 4 --- src/arch/arm64/tables.c | 10 +++++--- 6 files changed, 39 insertions(+), 34 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 5bf72b2..75c256a 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -37,6 +37,16 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) CBFSTOOL_PRE1_OPTS = -m arm64 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) endif +ifeq ($(CONFIG_ARCH_ARM64),y) +stages_c = $(src)/arch/arm/stages.c +stages_o = $(obj)/arch/arm/stages.o + +$(stages_o): $(stages_c) $(obj)/config.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_arm) -I. $(CPPFLAGS_arm) -c -o $@ $< -marm + +endif + ################################################################################ # bootblock ################################################################################ @@ -44,14 +54,11 @@ endif ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM64),y) bootblock-y += div0.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c - bootblock-y += id.S $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h bootblock-y += stages.c bootblock-y += eabi_compat.c - bootblock-y += memset.S bootblock-y += memcpy.S bootblock-y += memmove.S @@ -60,7 +67,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -72,7 +79,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) romstage-y += stages.c romstage-y += div0.c -romstage-y += early_console.c romstage-y += eabi_compat.c romstage-y += memset.S romstage-y += memcpy.S @@ -80,6 +86,7 @@ romstage-y += memmove.S romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c # Build the romstage +VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm64/romstage.ld $(obj)/ldoptions @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -102,24 +109,18 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S - -rmodules_$(ARCH-ramstage-y) += memset.S -rmodules_$(ARCH-ramstage-y) += memcpy.S -rmodules_$(ARCH-ramstage-y) += memmove.S -rmodules_$(ARCH-ramstage-y) += eabi_compat.c - -VBOOT_STUB_DEPS += $(obj)/arch/arm64/eabi_compat.rmodules.o - -$(eval $(call create_class_compiler,rmodules,arm64)) - ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) # Build the ramstage $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm64/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld + +$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index fc2e668..1dd2576 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,9 +1,11 @@ -config ARCH_BOOTBLOCK_ARM_V8_64 +config ARCH_BOOTBLOCK_ARMV8_64 def_bool n select ARCH_BOOTBLOCK_ARM64 -config ARCH_ROMSTAGE_ARM_V8_64 + +config ARCH_ROMSTAGE_ARMV8_64 def_bool n select ARCH_ROMSTAGE_ARM64 -config ARCH_RAMSTAGE_ARM_V8_64 + +config ARCH_RAMSTAGE_ARMV8_64 def_bool n select ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 973b391..c5f7a80 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -26,7 +26,7 @@ armv8_asm_flags = $(armv8_flags) ################################################################################ ## bootblock ################################################################################ -ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock.S @@ -46,7 +46,7 @@ endif ################################################################################ ## romstage ################################################################################ -ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += cache.c romstage-y += cpu.S @@ -61,7 +61,7 @@ endif ################################################################################ ## ramstage ################################################################################ -ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += cache.c ramstage-y += cpu.S @@ -71,4 +71,7 @@ ramstage-y += exception_asm.S ramstage-c-ccopts += $(armv8_flags) ramstage-S-ccopts += $(armv8_asm_flags) +rmodules_arm64-c-ccopts += $(armv8_flags) +rmodules_arm64-S-ccopts += $(armv8_asm_flags) + endif diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 6fb0e65..85b2cce 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -21,13 +21,14 @@ #include <arch/stages.h> #include <cbmem.h> #include <console/console.h> +#include <payload_loader.h> -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +void arch_payload_run(const struct payload *payload) { - void (*doit)(void *) = entry; + void (*doit)(void *) = payload->entry; void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); - printk(BIOS_SPEW, "entry = %p\n", entry); + printk(BIOS_SPEW, "entry = %p\n", payload->entry); cache_sync_instructions(); doit(cb_tables); } diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..5b58baa 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -20,10 +20,6 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if CONFIG_CAR_MIGRATION - #error "This is ARM, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ce7ad5a..a2b7b9b 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -33,7 +33,11 @@ void cbmem_arch_init(void) { } -struct lb_memory *write_tables(void) +void cbmem_fail_resume(void) +{ +} + +void write_tables(void) { unsigned long table_pointer, new_table_pointer; @@ -43,7 +47,7 @@ struct lb_memory *write_tables(void) MAX_COREBOOT_TABLE_SIZE); if (!table_pointer) { printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return NULL; + return; } new_table_pointer = write_coreboot_table(0UL, 0UL, @@ -61,6 +65,4 @@ struct lb_memory *write_tables(void) /* Print CBMEM sections */ cbmem_list(); - - return get_lb_mem(); }

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New patch to review for coreboot: 15adf87 xcompile: Rename aarch64 to arm64
by Marc Jones 19 Jan '15

19 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8235 -gerrit commit 15adf8702bdf06eb7c3d68d87d5203425b87aa88 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jan 16 13:19:04 2015 -0700 xcompile: Rename aarch64 to arm64 coreboot toolchain.inc uses the ARCH_SUPPORTED variable set by xcompile. This change allows for consistent naming in the toolchain.inc generated variables. Change-Id: Iafed06cf2d19a533f99e10b76aca82adc3e09fa8 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/xcompile/xcompile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 45dae8c..47e4338 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -168,7 +168,7 @@ EOF } # Architecture definition -SUPPORTED_ARCHITECTURE="x86 arm aarch64 riscv" +SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv" arch_config_arm() { TARCH="arm" @@ -179,8 +179,8 @@ arch_config_arm() { TABI="eabi" } -arch_config_aarch64() { - TARCH="aarch64" +arch_config_arm64() { + TARCH="arm64" TBFDARCH="littleaarch64" TCLIST="aarch64" TWIDTH="64"

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Patch set updated for coreboot: 080b0cc tegra132: Add support for tegra132 soc
by Marc Jones 19 Jan '15

19 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8040 -gerrit commit 080b0ccab7b89c00b638b41c56c37d9c7d86c333 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:43:07 2014 -0700 tegra132: Add support for tegra132 soc Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 --- src/soc/nvidia/Kconfig | 1 + src/soc/nvidia/Makefile.inc | 1 + src/soc/nvidia/tegra132/Kconfig | 24 ++ src/soc/nvidia/tegra132/Kconfig.orig | 132 +++++++++++ src/soc/nvidia/tegra132/Makefile.inc | 12 + src/soc/nvidia/tegra132/Makefile.inc.orig | 18 ++ src/soc/nvidia/tegra132/cbfs.c | 26 +++ src/soc/nvidia/tegra132/cbmem.c | 26 +++ src/soc/nvidia/tegra132/chip.h | 31 +++ src/soc/nvidia/tegra132/include/soc/addressmap.h | 83 +++++++ src/soc/nvidia/tegra132/include/soc/clock.h | 276 +++++++++++++++++++++++ src/soc/nvidia/tegra132/include/soc/display.h | 202 +++++++++++++++++ src/soc/nvidia/tegra132/timer.c | 31 +++ 13 files changed, 863 insertions(+) diff --git a/src/soc/nvidia/Kconfig b/src/soc/nvidia/Kconfig index 836edeb..cb1f468 100644 --- a/src/soc/nvidia/Kconfig +++ b/src/soc/nvidia/Kconfig @@ -1 +1,2 @@ source src/soc/nvidia/tegra124/Kconfig +source src/soc/nvidia/tegra132/Kconfig diff --git a/src/soc/nvidia/Makefile.inc b/src/soc/nvidia/Makefile.inc index 34feb0a..100cb94 100644 --- a/src/soc/nvidia/Makefile.inc +++ b/src/soc/nvidia/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124 +subdirs-$(CONFIG_SOC_NVIDIA_TEGRA132) += tegra132 diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig new file mode 100644 index 0000000..df58f06 --- /dev/null +++ b/src/soc/nvidia/tegra132/Kconfig @@ -0,0 +1,24 @@ +config SOC_NVIDIA_TEGRA132 + bool + default n + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM_LPAE + select DYNAMIC_CBMEM + +if SOC_NVIDIA_TEGRA132 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +endif diff --git a/src/soc/nvidia/tegra132/Kconfig.orig b/src/soc/nvidia/tegra132/Kconfig.orig new file mode 100644 index 0000000..7507e60 --- /dev/null +++ b/src/soc/nvidia/tegra132/Kconfig.orig @@ -0,0 +1,132 @@ +config SOC_NVIDIA_TEGRA132 + bool + default n + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM_LPAE +<<<<<<< HEAD +======= + select BOOTBLOCK_CONSOLE + select HAVE_UART_SPECIAL + select HAVE_UART_MEMORY_MAPPED + select EARLY_CONSOLE + select ARM_BOOTBLOCK_CUSTOM + select DYNAMIC_CBMEM +>>>>>>> f552197... t132: enable cbmem console support + +if SOC_NVIDIA_TEGRA132 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" +<<<<<<< HEAD + default 0x18080 +======= + default 0x22080 + +config BOOTBLOCK_BASE + hex + default 0x40020000 + +config ROMSTAGE_BASE + hex + default 0x4002c000 + +config SYS_SDRAM_BASE + hex + default 0x80000000 + +config RAMSTAGE_BASE + hex + default 0x80200000 + +config BOOTBLOCK_STACK_TOP + hex + default 0x40020000 + +config BOOTBLOCK_STACK_BOTTOM + hex + default 0x4001c000 + +config ROMSTAGE_STACK_TOP + hex + default 0x40020000 + +config ROMSTAGE_STACK_BOTTOM + hex + default 0x4001c000 + +config RAMSTAGE_STACK_TOP + hex + default 0x80020000 + +config RAMSTAGE_STACK_BOTTOM + hex + default 0x8001c000 + +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0x40006000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00016000 + +config CBMEM_CONSOLE_PRERAM_BASE + hex "memory address of the CBMEM console buffer" + default 0x40004020 + +choice CONSOLE_SERIAL_TEGRA132_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_TEGRA132_UARTA + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_TEGRA132_UARTA + bool "UARTA" + default y + help + Serial console on UART A. + +config CONSOLE_SERIAL_TEGRA132_UARTB + bool "UARTB" + help + Serial console on UART B. + +config CONSOLE_SERIAL_TEGRA132_UARTC + bool "UARTC" + help + Serial console on UART C. + +config CONSOLE_SERIAL_TEGRA132_UARTD + bool "UARTD" + help + Serial console on UART D. + +config CONSOLE_SERIAL_TEGRA132_UARTE + bool "UARTE" + help + Serial console on UART E. + +endchoice + +config CONSOLE_SERIAL_TEGRA132_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x70006000 if CONSOLE_SERIAL_TEGRA132_UARTA + default 0x70006040 if CONSOLE_SERIAL_TEGRA132_UARTB + default 0x70006200 if CONSOLE_SERIAL_TEGRA132_UARTC + default 0x70006300 if CONSOLE_SERIAL_TEGRA132_UARTD + default 0x70006400 if CONSOLE_SERIAL_TEGRA132_UARTE + help + Map the UART names to the respective MMIO addres. +>>>>>>> f552197... t132: enable cbmem console support + +endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc new file mode 100644 index 0000000..e31bbb6 --- /dev/null +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -0,0 +1,12 @@ +bootblock-y += cbfs.c +bootblock-y += timer.c + +romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += timer.c + +ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += timer.c + +CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/Makefile.inc.orig b/src/soc/nvidia/tegra132/Makefile.inc.orig new file mode 100644 index 0000000..327442f --- /dev/null +++ b/src/soc/nvidia/tegra132/Makefile.inc.orig @@ -0,0 +1,18 @@ +bootblock-y += cbfs.c +bootblock-y += timer.c + +<<<<<<< HEAD +======= +romstage-y += romstage_asm.S +romstage-y += addressmap.c +>>>>>>> f552197... t132: enable cbmem console support +romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += timer.c + +ramstage-y += addressmap.c +ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += timer.c + +CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c new file mode 100644 index 0000000..ac4a557 --- /dev/null +++ b/src/soc/nvidia/tegra132/cbfs.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbfs.h> /* This driver serves as a CBFS media source. */ + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c new file mode 100644 index 0000000..495fcba --- /dev/null +++ b/src/soc/nvidia/tegra132/cbmem.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ +/* TODO: update with real cbmem_top function. */ + return NULL; +} diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h new file mode 100644 index 0000000..394f0a4 --- /dev/null +++ b/src/soc/nvidia/tegra132/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__ +#define __SOC_NVIDIA_TEGRA132_CHIP_H__ +#include <arch/cache.h> +#include <soc/addressmap.h> + +#define EFAULT 1 +#define EINVAL 2 + +struct soc_nvidia_tegra132_config { +}; + +#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h new file mode 100644 index 0000000..d9d970a --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ +#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ + +#include <stddef.h> + +enum { + TEGRA_SRAM_BASE = 0x40000000, + TEGRA_SRAM_SIZE = 0x40000 +}; + +enum { + TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_ARM_DISPLAYA = 0x54200000, + TEGRA_ARM_DISPLAYB = 0x54240000, + TEGRA_ARM_SOR = 0x54540000, + TEGRA_ARM_DPAUX = 0x545c0000, + TEGRA_PG_UP_BASE = 0x60000000, + TEGRA_TMRUS_BASE = 0x60005010, + TEGRA_CLK_RST_BASE = 0x60006000, + TEGRA_FLOW_BASE = 0x60007000, + TEGRA_GPIO_BASE = 0x6000D000, + TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_DMA_BASE = 0x60020000, + TEGRA_APB_MISC_BASE = 0x70000000, + TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, + TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, + TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, + TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, + TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, + TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, + TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, + TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, + TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, + TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000, + TEGRA_I2C_BASE = TEGRA_APB_MISC_BASE + 0xC000, + TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, + TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400, + TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500, + TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, + TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, + TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, + TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, + TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, + TEGRA_MC_BASE = 0x70019000, + TEGRA_EMC_BASE = 0x7001B000, + TEGRA_CSITE_BASE = 0x70040000, + TEGRA_SYSCTR0_BASE = 0x700F0000, + TEGRA_USBD_BASE = 0x7D000000, + TEGRA_USB2_BASE = 0x7D004000, + TEGRA_USB3_BASE = 0x7D008000, +}; + +enum { + TEGRA_I2C_BASE_COUNT = 6, +}; + +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h new file mode 100644 index 0000000..5fc10c3 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -0,0 +1,276 @@ +/* + * Copyright 2014 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CLOCK_H__ +#define __SOC_NVIDIA_TEGRA132_CLOCK_H__ + +#include <stdint.h> + +enum { + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S1 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S2 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S0 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, + + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, + + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, + + // Clock reset. + CLK_U_EMUCIF = 0x1 << 23, + // Clock enable. + CLK_U_IRAMD = 0x1 << 23, + + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, + + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S3 = 0x1 << 5, + CLK_V_I2S4 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AUDIO = 0x1 << 10, + CLK_V_APBIF = 0x1 << 11, + CLK_V_DAM0 = 0x1 << 12, + CLK_V_DAM1 = 0x1 << 13, + CLK_V_DAM2 = 0x1 << 14, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_EXTPERIPH1 = 0x1 << 24, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, + + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_AMX0 = 0x1 << 25, + CLK_W_ADX0 = 0x1 << 26, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + CLK_W_MC1 = 0x1 << 30, + CLK_W_EMC1 = 0x1 << 31, + + CLK_X_AFC0 = 0x1 << 31, + CLK_X_AFC1 = 0x1 << 30, + CLK_X_AFC2 = 0x1 << 29, + CLK_X_AFC3 = 0x1 << 28, + CLK_X_AFC4 = 0x1 << 27, + CLK_X_AFC5 = 0x1 << 26, + CLK_X_AMX1 = 0x1 << 25, + CLK_X_GPU = 0x1 << 24, + CLK_X_SOR0 = 0x1 << 22, + CLK_X_DPAUX = 0x1 << 21, + CLK_X_ADX1 = 0x1 << 20, + CLK_X_VIC = 0x1 << 18, + CLK_X_CLK72MHZ = 0x1 << 17, + CLK_X_HDMI_AUDIO = 0x1 << 16, + CLK_X_EMC_DLL = 0x1 << 14, + CLK_X_VIM2_CLK = 0x1 << 11, + CLK_X_I2C6 = 0x1 << 6, + CLK_X_CAM_MCLK2 = 0x1 << 5, + CLK_X_CAM_MCLK = 0x1 << 4, + CLK_X_SPARE = 0x1 << 0, +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +/* Calculate clock fractional divider value from ref and target frequencies. + * This is for a U7.1 format. This is not well written up in the book and + * there have been some questions about this macro, so here we go. + * U7.1 format is defined as (ddddddd+1) + (h*.5) + * The lowest order bit is actually a fractional bit. + * Hence, the divider can be thought of as 9 bits. + * So: + * divider = ((ref/freq) << 1 - 1) (upper 7 bits) | + * (ref/freq & 1) (low order half-bit) + * however we can't do fractional arithmetic ... these are integers! + * So we normalize by shifting the result left 1 bit, and extracting + * ddddddd and h directly to the returned u8. + * divider = 2*(ref/freq); + * We want to + * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as + * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely + * situated in the upper 7 bits, and the h is sitting there in the low order + * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number + * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you + * will assign this to a u8, it gets nicely truncated for you. + */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2) + +/* Calculate clock frequency value from reference and clock divider value + * The discussion in the book is pretty lacking. + * The idea is that we need to divide a ref clock by a divisor + * in U7.1 format, where 7 upper bits are the integer + * and lowest order bit is a fraction. + * from the book, U7.1 is (ddddddd+1) + (h*.5) + * To normalize to an actual number, we might do this: + * ((d>>7+1)&0x7f) + (d&1 >> 1) + * but as you might guess, the low order bit would be lost. + * Since we can't express the fractional bit, we need to multiply it all by 2. + * ((d + 2)&0xfe) + (d & 1) + * Since we're just adding +2, the lowest order bit is preserved. Hence + * (d+2) is the same as ((d + 2)&0xfe) + (d & 1) + * + * Since you multiply denominator * 2 (by NOT shifting it), + * you multiply numerator * 2 to cancel it out. + */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) + +#define clock_configure_irregular_source(device, src, freq, src_id) \ + clrsetbits_le32(&clk_rst->clk_src_##device, \ + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \ + src_id << CLK_SOURCE_SHIFT | \ + CLK_DIVIDER(TEGRA_##src##_KHZ, freq)) + +/* Warning: Some devices just use different bits for the same sources for no + * apparent reason. *Always* double-check the TRM before trusting this macro. */ +#define clock_configure_source(device, src, freq) \ + clock_configure_irregular_source(device, src, freq, src) + +/* The I2C divisors are not 7.1 divisors like the others, they divide by n + 1 + * directly. Also, there are internal divisors in the I2C controller itself. + * We can deal with those here and make it easier to select what the actual + * bus frequency will be. The 0x19 value is the default divisor in the + * clk_divisor register in the controller, and 8 is just a magic number in the + * documentation. Multiplying by 2 compensates for the different format of the + * divisor. + */ +#define clock_configure_i2c_scl_freq(device, src, freq) \ + clock_configure_source(device, src, (freq) * (0x19 + 1) * 8 * 2) + +enum clock_source { /* Careful: Not true for all sources, always check TRM! */ + PLLP = 0, + PLLC2 = 1, + PLLC = 2, + PLLD = 2, + PLLC3 = 3, + PLLA = 3, + PLLM = 4, + PLLD2 = 5, + CLK_M = 6, +}; + +/* soc-specific */ +#define TEGRA_CLK_M_KHZ clock_get_osc_khz() +#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ +#define TEGRA_PLLP_KHZ (408000) +#define TEGRA_PLLC_KHZ (600000) +#define TEGRA_PLLD_KHZ (925000) +#define TEGRA_PLLU_KHZ (960000) + +int clock_get_osc_khz(void); +void clock_early_uart(void); +void clock_external_output(int clk_id); +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq); +void clock_cpu0_config_and_reset(void * entry); +void clock_halt_avp(void); +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); +void clock_init(void); +void clock_init_arm_generic_timer(void); +void sor_clock_stop(void); +void sor_clock_start(void); + +#endif /* __SOC_NVIDIA_TEGRA132_CLOCK_H__ */ + diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h new file mode 100644 index 0000000..2c21292 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/display.h @@ -0,0 +1,202 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ +#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ + +/* ardisplay.h */ +#define DC_CMD_DISPLAY_WINDOW_HEADER_0 0x42 +#define DC_COM_CRC_CONTROL_0 0x300 +#define DC_COM_CRC_CHECKSUM_0 0x301 +#define DC_COM_PIN_OUTPUT_ENABLE0_0 0x302 +#define DC_COM_PIN_OUTPUT_ENABLE1_0 0x303 +#define DC_COM_PIN_OUTPUT_ENABLE2_0 0x304 +#define DC_COM_PIN_OUTPUT_ENABLE3_0 0x305 +#define DC_CMD_STATE_ACCESS_0 0x40 +#define DC_DISP_DISP_CLOCK_CONTROL_0 0x42e +#define DC_DISP_DISP_TIMING_OPTIONS_0 0x405 +#define DC_DISP_REF_TO_SYNC_0 0x406 +#define DC_DISP_SYNC_WIDTH_0 0x407 +#define DC_DISP_BACK_PORCH_0 0x408 +#define DC_DISP_DISP_ACTIVE_0 0x409 +#define DC_DISP_FRONT_PORCH_0 0x40a +#define DC_DISP_DISP_WIN_OPTIONS_0 0x402 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT 25 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD (0x1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 0x400 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0 0x4e4 +#define DC_CMD_DISPLAY_COMMAND_0 0x32 +#define DC_CMD_STATE_CONTROL_0 0x41 +#define DC_CMD_DISPLAY_POWER_CONTROL_0 0x36 + +/* ardisplay_a.h */ +#define DC_WIN_A_WIN_OPTIONS_0 0x700 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1) +#define DC_WIN_A_BYTE_SWAP_0 0x701 +#define DC_WIN_A_BUFFER_CONTROL_0 0x702 +#define DC_WIN_A_COLOR_DEPTH_0 0x703 +#define DC_WIN_A_POSITION_0 0x704 +#define DC_WIN_A_SIZE_0 0x705 +#define DC_WIN_A_PRESCALED_SIZE_0 0x706 +#define DC_WIN_A_H_INITIAL_DDA_0 0x707 +#define DC_WIN_A_V_INITIAL_DDA_0 0x708 +#define DC_WIN_A_DDA_INCREMENT_0 0x709 +#define DC_WIN_A_LINE_STRIDE_0 0x70a +#define DC_WIN_A_DV_CONTROL_0 0x70e +#define DC_WIN_A_BLEND_LAYER_CONTROL_0 0x716 +#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719 +#define DC_WINBUF_A_START_ADDR_LO_0 0x800 +#define DC_WINBUF_A_START_ADDR_HI_0 0x80d +#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806 +#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808 + +/* ardisplay_bd.h */ +#define DC_B_WIN_BD_SIZE_0 0xd85 +#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86 +#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a +#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83 +#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0 +#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89 +#define DC_B_WIN_BD_WIN_OPTIONS_0 0xd80 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT 30 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD (0x1 << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE (1) + +/* arsor.h */ +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c +#define SOR_NV_PDISP_SOR_PLL0_0 0x17 +#define SOR_NV_PDISP_SOR_PLL1_0 0x18 +#define SOR_NV_PDISP_SOR_PLL2_0 0x19 +#define SOR_NV_PDISP_SOR_PLL3_0 0x1a +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT 22 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT 0 +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT 2 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT 24 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT 23 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT 25 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 0x4e +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 0x52 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 0x56 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT 8 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD (0xff << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT 22 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0 0x1c +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 0x4c +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 0x21 +#define SOR_NV_PDISP_SOR_DP_TPG_0 0x6d +#define SOR_NV_PDISP_HEAD_STATE1_0 0x7 +#define SOR_NV_PDISP_HEAD_STATE2_0 0x9 +#define SOR_NV_PDISP_HEAD_STATE3_0 0xb +#define SOR_NV_PDISP_HEAD_STATE4_0 0xd +#define SOR_NV_PDISP_SOR_STATE1_0 0x4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT 12 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT 13 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT 8 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A (8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B (9) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM (15) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT 6 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT 4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH (3) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT 0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 (2) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 0x58 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT 24 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT 16 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD (0xf << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT 8 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT 0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD (0x3f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT 2 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT 17 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 (3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 (4) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 (5) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 (6) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 (7) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 (8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 (9) + +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 0x11 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 0x64 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0 0x60 +#define SOR_NV_PDISP_SOR_PWR_0 0x15 +#define SOR_NV_PDISP_SOR_STATE0_0 0x3 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 0x2 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 0x1 + +/* ardpaux.h */ +#define DPAUX_DP_AUXDATA_READ_W0 0x19 + +#define DP_LVDS_SHIFT 25 +#define DP_LVDS (1 << DP_LVDS_SHIFT) + +#define SRC_BPP 16 +#define COLORDEPTH 0x6 +#define COLOR_WHITE 0xFFFFFF + +struct soc_nvidia_tegra132_config; /* forward declaration */ +void setup_display(struct soc_nvidia_tegra132_config *config); +void init_dca_regs(void); +void dp_io_powerup(void); +u32 dp_setup_timing(u32 width, u32 height); +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + +#define FB_SIZE_MB (32) + +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra132/timer.c b/src/soc/nvidia/tegra132/timer.c new file mode 100644 index 0000000..e2b0b82 --- /dev/null +++ b/src/soc/nvidia/tegra132/timer.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void init_timer(void) +{ +} + +void udelay(unsigned usec) +{ +}

1 0

Patch set updated for coreboot: 6acfffb rush: Add support for rush board
by Marc Jones 19 Jan '15

19 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8041 -gerrit commit 6acfffb8309b69aeb2d004c7afdc3640f2ed69b3 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:44:21 2014 -0700 rush: Add support for rush board Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 --- configs/config.rush | 4 ++++ src/mainboard/google/Kconfig | 3 +++ src/mainboard/google/rush/Kconfig | 39 +++++++++++++++++++++++++++++++++ src/mainboard/google/rush/Makefile.inc | 22 +++++++++++++++++++ src/mainboard/google/rush/devicetree.cb | 22 +++++++++++++++++++ src/mainboard/google/rush/mainboard.c | 35 +++++++++++++++++++++++++++++ src/mainboard/google/rush/romstage.c | 30 +++++++++++++++++++++++++ 7 files changed, 155 insertions(+) diff --git a/configs/config.rush b/configs/config.rush new file mode 100644 index 0000000..e34f216 --- /dev/null +++ b/configs/config.rush @@ -0,0 +1,4 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_RUSH=y +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_CONSOLE_SERIAL=y diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index e84cd7c..dd77bf3 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -47,6 +47,8 @@ config BOARD_GOOGLE_PEPPY bool "Peppy" config BOARD_GOOGLE_RAMBI bool "Rambi" +config BOARD_GOOGLE_RUSH + bool "Rush" config BOARD_GOOGLE_SAMUS bool "Samus" config BOARD_GOOGLE_SLIPPY @@ -71,6 +73,7 @@ source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peach_pit/Kconfig" source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/rambi/Kconfig" +source "src/mainboard/google/rush/Kconfig" source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig new file mode 100644 index 0000000..10654e4 --- /dev/null +++ b/src/mainboard/google/rush/Kconfig @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_RUSH + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_NVIDIA_TEGRA132 + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default google/rush + +config MAINBOARD_PART_NUMBER + string + default "Rush" + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc new file mode 100644 index 0000000..94a0e28 --- /dev/null +++ b/src/mainboard/google/rush/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c + +ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb new file mode 100644 index 0000000..73836a4 --- /dev/null +++ b/src/mainboard/google/rush/devicetree.cb @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/nvidia/tegra132 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c new file mode 100644 index 0000000..9b8e354 --- /dev/null +++ b/src/mainboard/google/rush/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "rush", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c new file mode 100644 index 0000000..e2b75f6 --- /dev/null +++ b/src/mainboard/google/rush/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +}

1 0

Patch set updated for coreboot: 5656b0e intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 19 Jan '15

19 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit 5656b0ecd0a6ed8ada86ee8f29bc536751bbafeb Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. It intend to be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/southbridge/intel/fsp_rangeley/chip.h | 8 ++++++++ src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/fsp_rangeley/chip.h b/src/southbridge/intel/fsp_rangeley/chip.h old mode 100644 new mode 100755 index 215454c..975f762 --- a/src/southbridge/intel/fsp_rangeley/chip.h +++ b/src/southbridge/intel/fsp_rangeley/chip.h @@ -83,6 +83,14 @@ struct southbridge_intel_fsp_rangeley_config { uint8_t fadt_pm_profile; uint16_t fadt_boot_arch; + /* PCIe port de-emphasis control */ + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; + #define DE_EMPHASIS_MINUS_6_0_DB 0 + #define DE_EMPHASIS_MINUS_3_5_DB 1 + }; #endif /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */ diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h old mode 100644 new mode 100755 index 12ac2be..fba38a0 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

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Patch set updated for coreboot: 08185cc samus: Disable self refresh and MRC cache on broadwell
by Marc Jones 19 Jan '15

19 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8214 -gerrit commit 08185cc0d22f47e7abfb8dc02a7e5e78d8c5f2b6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 15 13:40:21 2014 -0700 samus: Disable self refresh and MRC cache on broadwell Add workarounds for power and/or lpddr3 issues on Broadwell SKU. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build and boot on samus Original-Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208154 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit c3ee57114315320b542f53645ffb168ad654b756) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie28f3ad65000a627ba64486e0f16493e8101cef3 --- src/mainboard/google/samus/romstage.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index d652859..c0c7200 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> +#include <broadwell/cpu.h> #include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> @@ -54,6 +55,15 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; + /* + * Disable use of PEI saved data to work around memory issues. + */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) { + pei_data.disable_self_refresh = 1; + pei_data.disable_saved_data = 1; + } + + /* Initalize memory */ romstage_common(rp); /*

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coreboot-gerrit January 2015